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84 lines
2.2 KiB
Verilog
84 lines
2.2 KiB
Verilog
//--------------------------------------------------------------------------------
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// UartRxExtreme.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Extreme minimal UART receiver optimized for 20MHz/115200 data rate
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//
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// CAUTION:
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// optimized for 20MHz/115200
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// rx_sample_cntr[7:0] does never stop, but reloads on sequense start condition
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// initial rx_sample_cntr[7:0] value has been made 255 instead of 257 to save one precious counter register
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// rx_busy and rx_done fall simultaneously 0,5 bit before stop bit time end
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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UartRxExtreme UR1 (
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.clk(),
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.rx_data(),
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.rx_busy(),
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.rx_done(),
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.rxd()
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module UartRxExtreme(clk, rx_data, rx_busy, rx_done, rxd);
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input wire clk;
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output reg [7:0] rx_data = 0;
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reg rx_data_9th_bit = 0; // {rx_data[7:0],rx_data_9th_bit} is actually a shift register
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output reg rx_busy = 0; // sequence control is done by rx_busy and unique high logic state of rx_data_9th_bit register
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output wire rx_done;
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input wire rxd;
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// Falling edge detector
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reg rxd_prev = 0;
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always @ (posedge clk) begin
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rxd_prev <= rxd;
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end
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wire start_bit_strobe = ~rx_busy && (~rxd & rxd_prev);
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// Sample counter
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reg [7:0] rx_sample_cntr = 0;
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always @ (posedge clk) begin
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if (start_bit_strobe) begin
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rx_sample_cntr[7:0] <= (86 * 3 - 1) - 2;
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end else begin
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if (rx_sample_cntr[7:0] == 0) begin
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rx_sample_cntr[7:0] <= (86 * 2 - 1);
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end else begin
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rx_sample_cntr[7:0] <= rx_sample_cntr[7:0] - 1;
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end // rx_sample_cntr
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end // start_bit_strobe
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end
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wire rx_do_sample = (rx_sample_cntr[7:0] == 0);
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// Data shifting
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always @ (posedge clk) begin
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if (start_bit_strobe) begin
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{rx_data[7:0],rx_data_9th_bit} <= 9'b100000000;
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rx_busy <= 1;
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end // start_bit_strobe
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if (rx_busy && rx_do_sample) begin
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if (rx_data_9th_bit) begin
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rx_busy <= 0;
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end else begin
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{rx_data[7:0],rx_data_9th_bit} <= {rxd,rx_data[7:0]};
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end
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end // (rx_busy && rx_do_sample)
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end
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assign
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rx_done = (rx_busy && rx_do_sample && rx_data_9th_bit) && rxd;
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endmodule
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