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86 lines
2.3 KiB
Verilog
86 lines
2.3 KiB
Verilog
//--------------------------------------------------------------------------------
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// ActionBurst.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Module is designed to generate one-shot trigger pulses on multiple channels (default is 8)
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// Every output channel is triggered only once
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// Channels get triggered in sequense with mutual delay of step_wdth[] clock cycles
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// That is useful when you need to start some tasks in exact order, but there are no convinient signals to line them up.
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// Instance of ActionBurst() is started by high level on start input and the only way to stop generation before all channels get triggered is to reset the instance
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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wire [7:0] actions;
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ActionBurst AB1 (
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.clk(clk200pll),
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.nrst(1'b1),
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.step_wdth(32'b1),
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.start(E_ClockDivider[24]),
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.busy(),
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.out(actions[7:0])
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);
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defparam AB1.WIDTH = 8;
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--- INSTANTIATION TEMPLATE END ---*/
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module ActionBurst(clk,nrst,step_wdth,start,busy,out);
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parameter WIDTH = 8;
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input wire clk;
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input wire nrst;
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input wire [31:0] step_wdth; // Module buffers step_wdth in PG instance on the SECOND cycle ater start applyed!
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input wire start;
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output reg busy = 0;
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output wire [(WIDTH-1):0] out;
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wire PgOut;
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PulseGen PG(
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.clk(clk),
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.nrst(busy),
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.low_wdth(step_wdth[31:0]),
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.high_wdth(32'b1),
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.rpt(1'b1),
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.start(1'b1),
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.busy(),
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.out(PgOut)
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);
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reg [31:0] state = 0;
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//reg [31:0] step_wdth_buf = 0; // buffering is done in PG
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always @ (posedge clk) begin
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if (~nrst) begin
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state[31:0] <= 0;
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end else begin
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if (~busy) begin
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if (start) begin // buffering input values
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state[31:0] <= 0;
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//step_wdth_buf[31:0] <= step_wdth[31:0]; // buffering is done in PG
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busy <= 1;
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end // start
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end else begin
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if (PgOut) begin
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if (state != (WIDTH-1)) begin
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state[31:0] <= state[31:0] + 1'b1;
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end else begin
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busy <= 0;
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end // state
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end // PgOut
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end // busy
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end // nrst
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end
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genvar i;
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generate
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for (i=0; i<WIDTH; i=i+1) begin
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assign out[i] = PgOut && ( i == state[31:0] );
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end
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endgenerate
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endmodule |