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63 lines
2.0 KiB
Verilog
63 lines
2.0 KiB
Verilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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//baeckler - 12-05-2007
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module clock_mux_tb ();
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reg [7:0] clk;
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reg [7:0] clk_sel;
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wire clk_out;
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clock_mux dut (
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.clk(clk),
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.clk_select(clk_sel),
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.clk_out(clk_out)
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);
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defparam dut .NUM_CLOCKS = 8;
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initial begin
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#200
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clk_sel = 8'b00000001;
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#200
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clk_sel = 8'b10000000;
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#200
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clk_sel = 8'b01000000;
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#400
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clk_sel = 8'b00000100;
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end
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initial clk = 0;
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initial clk_sel = 0;
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always #13 clk[0] = ~clk[0];
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always #10 clk[1] = ~clk[1];
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always #23 clk[2] = ~clk[2];
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always #11 clk[3] = ~clk[3];
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always #100 clk[4] = ~clk[4];
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always #21 clk[5] = ~clk[5];
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always #50 clk[6] = ~clk[6];
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always #5 clk[7] = ~clk[7];
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endmodule |