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101 lines
3.3 KiB
Verilog
101 lines
3.3 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 02-15-2006
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// recursive sorting network implementation of rotate right
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// for Stratix II
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module rotate_internal (din,dout,distance);
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`include "log2.inc"
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parameter WIDTH = 16;
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parameter DIST_WIDTH = log2(WIDTH-1);
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parameter GENERIC = 0;
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localparam MAX_D = 1 << DIST_WIDTH; // The shifting range described by
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// the distance.
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// this subdesign does not allow shifting beyond the data width
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// e.g. rotating an 8 bit value 100 steps.
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initial begin
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#10
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if (MAX_D > WIDTH) begin
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$display ("Error - Rotation by distance greater than data width not supported");
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$stop();
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end
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end
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input [WIDTH-1:0] din;
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output [WIDTH-1:0] dout;
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input [DIST_WIDTH-1:0] distance;
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wire [WIDTH-1:0] dout;
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wire [2*WIDTH-1:0] double_din = {din,din};
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genvar i;
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generate
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if (GENERIC) begin
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assign dout = double_din >> distance;
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end
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else begin
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wire [WIDTH-1:0] layer;
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if (DIST_WIDTH == 0) begin
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// degenerate case
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assign dout = din;
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end
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else if (DIST_WIDTH == 1) begin
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// knock out the last distance line
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for (i=0;i<WIDTH;i=i+1)
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begin : two_to_one
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assign layer[i] = distance[0] ? double_din[i+1] : double_din[i];
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end
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assign dout = layer;
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end
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else begin
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// knock out 2 more distance lines
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for (i=0;i<WIDTH;i=i+1)
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begin : four_to_one
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wire [3:0] dt;
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wire [1:0] st;
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assign dt[0] = double_din[i];
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assign dt[1] = double_din[i+MAX_D/4];
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assign dt[2] = double_din[i+MAX_D/2];
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assign dt[3] = double_din[i+MAX_D/2+MAX_D/4];
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assign st = {distance[DIST_WIDTH-1],distance[DIST_WIDTH-2]};
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assign layer[i] = dt[st];
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end
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if (DIST_WIDTH == 2) assign dout = layer;
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else begin
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// recurse to build the rest of the network
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rotate_internal r (.din(layer),.dout(dout),
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.distance(distance[DIST_WIDTH-3:0]));
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defparam r .WIDTH = WIDTH;
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defparam r .DIST_WIDTH = DIST_WIDTH-2;
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end
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end
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end
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endgenerate
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endmodule
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