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126 lines
4.5 KiB
Verilog
126 lines
4.5 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module mask_16 (in,mask);
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input [3:0] in;
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output [15:0] mask;
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reg [15:0] mask;
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parameter FROM_MSB = 1'b1;
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parameter DIAG_ONES = 1'b1;
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generate
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if (!FROM_MSB && !DIAG_ONES) begin
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always @(in) begin
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case (in)
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4'd0: mask=16'b0000000000000000;
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4'd1: mask=16'b0000000000000001;
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4'd2: mask=16'b0000000000000011;
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4'd3: mask=16'b0000000000000111;
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4'd4: mask=16'b0000000000001111;
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4'd5: mask=16'b0000000000011111;
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4'd6: mask=16'b0000000000111111;
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4'd7: mask=16'b0000000001111111;
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4'd8: mask=16'b0000000011111111;
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4'd9: mask=16'b0000000111111111;
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4'd10: mask=16'b0000001111111111;
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4'd11: mask=16'b0000011111111111;
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4'd12: mask=16'b0000111111111111;
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4'd13: mask=16'b0001111111111111;
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4'd14: mask=16'b0011111111111111;
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4'd15: mask=16'b0111111111111111;
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default: mask=0;
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endcase
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end
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end
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else if ( FROM_MSB && !DIAG_ONES) begin
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always @(in) begin
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case (in)
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4'd0: mask=16'b0000000000000000;
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4'd1: mask=16'b1000000000000000;
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4'd2: mask=16'b1100000000000000;
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4'd3: mask=16'b1110000000000000;
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4'd4: mask=16'b1111000000000000;
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4'd5: mask=16'b1111100000000000;
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4'd6: mask=16'b1111110000000000;
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4'd7: mask=16'b1111111000000000;
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4'd8: mask=16'b1111111100000000;
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4'd9: mask=16'b1111111110000000;
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4'd10: mask=16'b1111111111000000;
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4'd11: mask=16'b1111111111100000;
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4'd12: mask=16'b1111111111110000;
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4'd13: mask=16'b1111111111111000;
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4'd14: mask=16'b1111111111111100;
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4'd15: mask=16'b1111111111111110;
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default: mask=0;
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endcase
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end
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end
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else if (!FROM_MSB && DIAG_ONES) begin
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always @(in) begin
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case (in)
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4'd0: mask=16'b0000000000000001;
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4'd1: mask=16'b0000000000000011;
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4'd2: mask=16'b0000000000000111;
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4'd3: mask=16'b0000000000001111;
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4'd4: mask=16'b0000000000011111;
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4'd5: mask=16'b0000000000111111;
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4'd6: mask=16'b0000000001111111;
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4'd7: mask=16'b0000000011111111;
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4'd8: mask=16'b0000000111111111;
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4'd9: mask=16'b0000001111111111;
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4'd10: mask=16'b0000011111111111;
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4'd11: mask=16'b0000111111111111;
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4'd12: mask=16'b0001111111111111;
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4'd13: mask=16'b0011111111111111;
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4'd14: mask=16'b0111111111111111;
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4'd15: mask=16'b1111111111111111;
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default: mask=0;
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endcase
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end
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end
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else if ( FROM_MSB && DIAG_ONES) begin
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always @(in) begin
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case (in)
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4'd0: mask=16'b1000000000000000;
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4'd1: mask=16'b1100000000000000;
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4'd2: mask=16'b1110000000000000;
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4'd3: mask=16'b1111000000000000;
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4'd4: mask=16'b1111100000000000;
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4'd5: mask=16'b1111110000000000;
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4'd6: mask=16'b1111111000000000;
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4'd7: mask=16'b1111111100000000;
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4'd8: mask=16'b1111111110000000;
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4'd9: mask=16'b1111111111000000;
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4'd10: mask=16'b1111111111100000;
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4'd11: mask=16'b1111111111110000;
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4'd12: mask=16'b1111111111111000;
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4'd13: mask=16'b1111111111111100;
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4'd14: mask=16'b1111111111111110;
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4'd15: mask=16'b1111111111111111;
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default: mask=0;
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endcase
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end
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end
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endgenerate
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endmodule
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