basic_verilog/scripts_for_xilinx_hls at d046210740c71f28308c786c4b68ae95db80ebe0 - basic_verilog - Gitea: Git with a cup of tea

FPGA/basic_verilog

mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

History

Konstantin Pavlov d046210740 Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00

..

run_hls.tcl

Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00

vitis_hls_clean.sh

Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00

vitis_hls_cosim.sh

Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00

vitis_hls_csim.sh

Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00

vitis_hls_csynth.sh

Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00

vitis_hls_export.sh

Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00

vitis_hls_impl.sh

Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00

vitis_hls_open_gui.sh

Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00

vitis_hls_syn.sh

Added Vitis HLS scripts and example

2023-02-24 06:01:53 +03:00