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FPGA
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basic_verilog
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basic_verilog
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example_projects
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vivado_benchmark
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vivado_benchmark.srcs
History
Konstantin Pavlov
573cc6e6b8
Added benchmark project for Vivado IDE
2020-04-07 14:29:25 +03:00
..
constrs_1
Added benchmark project for Vivado IDE
2020-04-07 14:29:25 +03:00
sources_1
Added benchmark project for Vivado IDE
2020-04-07 14:29:25 +03:00