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basic_verilog/scripts/set_project_directory.tcl
2020-04-07 14:30:32 +03:00

15 lines
613 B
Tcl

#------------------------------------------------------------------------------
# set_project_directory.tcl
# Konstantin Pavlov, pavlovconst@gmail.com
#------------------------------------------------------------------------------
# INFO ------------------------------------------------------------------------
# Sets the working directory to the project so that if you generate files they
# are writen to the directory
#
# Place this script as a pre-tcl-script for "Synthesis" step
set work_directory [get_property DIRECTORY [current_project]]
cd $work_directory
puts -nonewline "Changing Directory to " ; pwd