1
0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
basic_verilog/scripts/program_all.bat
2021-10-18 09:23:55 +03:00

22 lines
709 B
Batchfile

@echo off
rem ------------------------------------------------------------------------------
rem program_all.bat
rem Konstantin Pavlov, pavlovconst@gmail.com
rem ------------------------------------------------------------------------------
echo "Listing programmers"
C:\intelFPGA_lite\17.0\quartus\bin64\quartus_pgm -l
echo "Programming first FPGA in the chain"
C:\intelFPGA_lite\17.0\quartus\bin64\quartus_pgm -c ^
"USB-Blaster on 192.168.0.182 [USB-1]" -m jtag -o ^
"P;%~dp0out\main.sof@1"
echo "Programming second FPGA in the chain"
C:\intelFPGA_lite\17.0\quartus\bin64\quartus_pgm -c ^
"USB-Blaster on 192.168.0.182 [USB-1]" -m jtag -o ^
"P;%~dp0out\main.sof@2"
pause
exit