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129 lines
4.0 KiB
Verilog
129 lines
4.0 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 03-01-2006
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module carry_and (dat,out);
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parameter WIDTH = 32;
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parameter METHOD = 4;
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input [WIDTH-1:0] dat;
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output out;
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// figure out pairs and triples of inputs
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localparam NEXT_EVEN_WIDTH = (WIDTH & 1) ? WIDTH + 1 : WIDTH;
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localparam HALF_WIDTH = NEXT_EVEN_WIDTH >> 1;
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localparam NEXT_DIV3_WIDTH = WIDTH + (((WIDTH % 3) & 1) << 1) + (((WIDTH % 3) & 2) >> 1);
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localparam THIRD_WIDTH = NEXT_DIV3_WIDTH / 3;
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wire [WIDTH + 2 : 0] ext_dat = {3'b111,dat};
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genvar i;
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generate
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if (METHOD == 0) begin
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///////////////////////
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// Generic style
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///////////////////////
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assign out = &dat;
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end
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else if (METHOD == 1) begin
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///////////////////////
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// 1 bit per cell carry chain
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///////////////////////
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wire [WIDTH:0] result;
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assign result = dat + 1'b1;
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assign out = result[WIDTH];
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end
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else if (METHOD == 2) begin
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////////////////////////////////
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// 2 bit per cell carry chain
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////////////////////////////////
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wire [HALF_WIDTH-1:0] pairs;
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wire [HALF_WIDTH:0] result;
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assign pairs = ext_dat[HALF_WIDTH-1:0] &
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ext_dat[2*HALF_WIDTH-1:HALF_WIDTH];
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assign result = pairs + 1'b1;
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assign out = result[HALF_WIDTH];
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end
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else if (METHOD == 3) begin
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////////////////////////////////
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// 3 bit per cell carry chain
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// may not absorb fully.
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// it will also be very tempting
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// for synthesit to unmap to 6 LUT.
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// Use Method = 4;
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////////////////////////////////
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wire [THIRD_WIDTH-1:0] triplets;
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wire [THIRD_WIDTH:0] result;
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assign triplets = ext_dat[THIRD_WIDTH-1:0] &
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ext_dat[2*THIRD_WIDTH-1:THIRD_WIDTH] &
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ext_dat[3*THIRD_WIDTH-1:2*THIRD_WIDTH];
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assign result = triplets + 1'b1;
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assign out = result[THIRD_WIDTH];
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end
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else if (METHOD == 4) begin
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//////////////////////////////////////////
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// 3 bit per cell Wide AND carry chain
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// WYSIWYG version
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//////////////////////////////////////////
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wire [THIRD_WIDTH:0] result;
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wire [THIRD_WIDTH+1:0] cin;
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assign cin[0] = 1'b0;
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for (i=0; i<THIRD_WIDTH; i=i+1)
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begin : third
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stratixii_lcell_comb w (
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.dataa(1'b0),
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.datab(ext_dat[i*3+0]),
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.datac(ext_dat[i*3+1]),
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.datad(ext_dat[i*3+2]),
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// unused
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.datae(1'b0),
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.dataf(1'b0),
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.datag(1'b0),
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.cin(cin[i]),
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.sumout(result[i]),
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.cout(cin[i+1]),
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.sharein(1'b0),
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.combout(),
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.shareout()
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);
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defparam w .shared_arith = "off";
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defparam w .extended_lut = "off";
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// 1 + B&C&D (quad 3 is inverted)
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defparam w .lut_mask =
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i == 0 ? 64'h000000000000c000 :
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64'h0000ffff0000c000;
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end
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assign out = cin[THIRD_WIDTH];
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end
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endgenerate
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endmodule |