basic_verilog/README.md

basic_verilog

Some basic must-have verilog modules

####(licensed under CC BY-SA 4_0)

/Advanced Synthesis Cookbook/ useful code from Altera`s cookbook

Main_TB.v* - basic testbench template

ClkDivider.v - wide reference clock divider
DeBounce.v - two-cycle debounce for input buttons
EdgeDetect.v - edge detector, gives one-tick pulses on every signal edge
ResetSet.v - SR trigger variant w/o metastable state, set dominates here
SetReset.v - SR trigger variant w/o metastable state, reset dominates here
Synch.v - input syncnronizer, standard way to get rid of metastability issues