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27 lines
1.1 KiB
Markdown
27 lines
1.1 KiB
Markdown
# basic_verilog
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### Some basic must-have verilog modules
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####(licensed under CC BY-SA 4_0)
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**/Advanced Synthesis Cookbook/** useful code from Altera`s cookbook
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**Main_tb.v** - basic testbench template
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**ClkDivider.v** - wide reference clock divider
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**DeBounce.v** - two-cycle debounce for input buttons
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**DynDelay.v** - dynamic delay made on general-purpose trigger elements
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**EdgeDetect.v** - edge detector, gives one-tick pulses on every signal edge
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**Encoder.v** encoder input module
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**PulseGen.v** - generates pulses with given width and delay
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**ResetSet.v** - SR trigger variant w/o metastable state, set dominates here
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**SetReset.v** - SR trigger variant w/o metastable state, reset dominates here
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**SimplePulseGen.v** - generates one-cycle pulse with given delay
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**StaticDelay.v** static delay made on Xilinx`s SRL16E primitives
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**Synch.v** - input syncnronizer (and also "static delay module"), standard way to get rid of metastability issues
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Also added some simple testbenches for selected modules
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Author: Konstantin Pavlov, pavlovconst@gmail.com
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