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74 lines
2.6 KiB
Verilog
74 lines
2.6 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 02-16-2006
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// placing the ternary add in a sub module
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// is not strictly necessary, but makes the
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// grouping clear and unambiguous if you
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// want to remove the pipeline registers.
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module tern_node (clk,a,b,c,o);
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parameter WIDTH = 8;
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input clk;
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input [WIDTH-1:0] a;
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input [WIDTH-1:0] b;
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input [WIDTH-1:0] c;
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output [WIDTH+2-1:0] o;
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reg [WIDTH+2-1:0] o;
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always @(posedge clk) begin
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o <= a+b+c;
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end
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endmodule
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//
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// pipelined sum of 9 binary words using
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// 4 ternary adder chains.
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// This WIDTH 8 example should use 42 DFF and 42
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// arithmetic logic cells. This would require roughly
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// 80 arithmetic cells on a binary adder device.
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//
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module ternary_sum_nine (clk,a,b,c,d,e,f,g,h,i,out);
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parameter WIDTH = 8;
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input clk;
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input [WIDTH-1:0] a,b,c,d,e,f,g,h,i;
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output [WIDTH+4-1:0] out;
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wire [WIDTH+2-1:0] part0,part1,part2;
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// entry layer, 9 => 3
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tern_node x (.clk(clk),.a(a),.b(b),.c(c),.o(part0));
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defparam x .WIDTH = WIDTH;
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tern_node y (.clk(clk),.a(d),.b(e),.c(f),.o(part1));
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defparam y .WIDTH = WIDTH;
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tern_node z (.clk(clk),.a(g),.b(h),.c(i),.o(part2));
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defparam z .WIDTH = WIDTH;
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// output layer 3=> 1
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tern_node o (.clk(clk),.a(part0),.b(part1),.c(part2),.o(out));
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defparam o .WIDTH = WIDTH+2;
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endmodule |