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92 lines
2.8 KiB
Verilog
92 lines
2.8 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 7-20-2006
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module ecc_2bit_tb ();
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reg [1:0] dat;
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wire [5:0] code;
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reg [5:0] err;
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wire [5:0] damaged_code;
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wire [1:0] recovered;
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wire [2:0] err_flag;
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// encode - corrupt - decode
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ecc_encode_2bit enc (.d(dat), .c(code));
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assign damaged_code = code ^ err;
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ecc_decode_2bit dec (.c(damaged_code),.d(recovered), .err_flag (err_flag));
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integer n,i,j;
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initial begin
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// test the four no-error cases
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for (n=0; n<4; n=n+1) begin
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dat = n[1:0];
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err = 0;
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#1
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// you must recover data and flag no-error
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if ((recovered !== dat) || (err_flag !== 3'b001)) begin
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$display ("Mismatch in no-error cases");
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$stop();
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end
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end
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// test the twenty four one-error cases
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for (n=0; n<4; n=n+1) begin
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for (i=0; i<6; i=i+1) begin
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dat = n[1:0];
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err = 1'b1 << i;
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#1
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// you must recover the data and flag correctly
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if ((recovered !== dat) || (err_flag !== 3'b010)) begin
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$display ("Mismatch in one-error cases");
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$stop();
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end
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end
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end
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// test the (144? but overlapping) two-error cases
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for (n=0; n<4; n=n+1) begin
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for (i=0; i<6; i=i+1) begin
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for (j=0; j<6; j=j+1) begin
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if (j != i) begin
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dat = n[1:0];
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err = 1'b1 << i;
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err = err | (1'b1 << j);
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#1
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// you must flag correctly
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if (err_flag !== 3'b100) begin
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$display ("Mismatch in two-error cases");
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$stop();
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end
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end
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end
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end
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end
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#10 $display ("PASS");
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$stop();
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end
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endmodule
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