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114 lines
3.8 KiB
Verilog
114 lines
3.8 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 07-10-2006
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// Vanilla dual port RAM
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// use the quartus/eda/sim_lib/altera_mf.v library to simulate
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//
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module ram_block (
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aclr_a,
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aclr_b,
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address_a,
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address_b,
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clock_a,
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clock_b,
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data_a,
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data_b,
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wren_a,
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wren_b,
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q_a,
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q_b
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);
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`include "log2.inc"
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parameter NUM_WORDS = 512;
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parameter DAT_WIDTH = 72;
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localparam ADDR_WIDTH = log2(NUM_WORDS-1);
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input aclr_a;
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input aclr_b;
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input [ADDR_WIDTH-1:0] address_a;
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input [ADDR_WIDTH-1:0] address_b;
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input clock_a;
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input clock_b;
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input [DAT_WIDTH-1:0] data_a;
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input [DAT_WIDTH-1:0] data_b;
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input wren_a;
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input wren_b;
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output [DAT_WIDTH-1:0] q_a;
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output [DAT_WIDTH-1:0] q_b;
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altsyncram altsyncram_component (
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.wren_a (wren_a),
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.aclr0 (aclr_a),
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.clock0 (clock_a),
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.wren_b (wren_b),
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.aclr1 (aclr_b),
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.clock1 (clock_b),
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.address_a (address_a),
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.address_b (address_b),
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.data_a (data_a),
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.data_b (data_b),
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.q_a (q_a),
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.q_b (q_b),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.eccstatus (),
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.rden_a (1'b1),
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.rden_b (1'b1)
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);
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defparam
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altsyncram_component.address_reg_b = "CLOCK1",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.indata_reg_b = "CLOCK1",
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altsyncram_component.intended_device_family = "Stratix II",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = NUM_WORDS,
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altsyncram_component.numwords_b = NUM_WORDS,
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altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
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altsyncram_component.outdata_aclr_a = "CLEAR0",
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altsyncram_component.outdata_aclr_b = "CLEAR1",
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altsyncram_component.outdata_reg_a = "CLOCK0",
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altsyncram_component.outdata_reg_b = "CLOCK1",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.ram_block_type = "AUTO",
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altsyncram_component.widthad_a = ADDR_WIDTH,
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altsyncram_component.widthad_b = ADDR_WIDTH,
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altsyncram_component.width_a = DAT_WIDTH,
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altsyncram_component.width_b = DAT_WIDTH,
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altsyncram_component.width_byteena_a = 1,
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altsyncram_component.width_byteena_b = 1,
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altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
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endmodule
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