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51 lines
2.0 KiB
Verilog
51 lines
2.0 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module synchronizer #(
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parameter WIDTH = 16,
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parameter STAGES = 3 // should not be less than 2
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)
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(
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input clk_in,arst_in,
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input clk_out,arst_out,
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input [WIDTH-1:0] dat_in,
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output [WIDTH-1:0] dat_out
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);
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// launch register
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reg [WIDTH-1:0] d /* synthesis preserve */;
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always @(posedge clk_in or posedge arst_in) begin
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if (arst_in) d <= 0;
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else d <= dat_in;
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end
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// capture registers
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reg [STAGES*WIDTH-1:0] c /* synthesis preserve */;
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always @(posedge clk_out or posedge arst_out) begin
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if (arst_out) c <= 0;
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else c <= {c[(STAGES-1)*WIDTH-1:0],d};
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end
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assign dat_out = c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
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endmodule |