FPGA/basic_verilog
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basic_verilog/example_projects/testbench_template_tb
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Konstantin Pavlov 66ff427e1e Added error suppression for Modelsim script
2022-04-25 01:03:37 +03:00
..
.gitignore
Added testbench template
2021-11-01 14:47:08 +03:00
c_rand.v
Added testbench template
2021-11-01 14:47:08 +03:00
clk_divider.sv
Added testbench template
2021-11-01 14:47:08 +03:00
compile.bat
Added testbench template
2021-11-01 14:47:08 +03:00
compile.tcl
Added error suppression for Modelsim script
2022-04-25 01:03:37 +03:00
delay.sv
Added testbench template
2021-11-01 14:47:08 +03:00
edge_detect.sv
Added testbench template
2021-11-01 14:47:08 +03:00
main_tb.sv
Added error suppression for Modelsim script
2022-04-25 01:03:37 +03:00