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41 lines
1.8 KiB
Verilog
41 lines
1.8 KiB
Verilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 09-16-2008
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// 67 to 64 decoder
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module dec_67_64 (
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input clk, arst,
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input [66:0] din,
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input pn_reverse,
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output [64:0] dout, // bit 64=1 indicates control word
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output framing_error
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);
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assign dout[63:0] = din[63:0] ^ {64{din[66]}}; // +/- data
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assign dout[64] = din[65] ^ pn_reverse; // 1 for control words
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assign framing_error = ~din[64] ^ din[65];
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endmodule
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