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109 lines
2.8 KiB
Verilog
109 lines
2.8 KiB
Verilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 05-13-2005
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//
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// Six input three output compressor (non-carry adder)
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//
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// Maps to 3 Stratix II six luts. Use optimize = speed
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//
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module six_three_comp (data,sum);
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input [5:0] data;
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output [2:0] sum;
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reg [2:0] sum /* synthesis keep */;
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always @(data) begin
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case (data)
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0: sum=0;
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1: sum=1;
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2: sum=1;
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3: sum=2;
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4: sum=1;
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5: sum=2;
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6: sum=2;
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7: sum=3;
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8: sum=1;
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9: sum=2;
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10: sum=2;
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11: sum=3;
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12: sum=2;
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13: sum=3;
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14: sum=3;
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15: sum=4;
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16: sum=1;
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17: sum=2;
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18: sum=2;
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19: sum=3;
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20: sum=2;
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21: sum=3;
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22: sum=3;
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23: sum=4;
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24: sum=2;
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25: sum=3;
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26: sum=3;
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27: sum=4;
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28: sum=3;
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29: sum=4;
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30: sum=4;
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31: sum=5;
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32: sum=1;
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33: sum=2;
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34: sum=2;
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35: sum=3;
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36: sum=2;
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37: sum=3;
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38: sum=3;
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39: sum=4;
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40: sum=2;
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41: sum=3;
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42: sum=3;
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43: sum=4;
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44: sum=3;
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45: sum=4;
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46: sum=4;
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47: sum=5;
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48: sum=2;
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49: sum=3;
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50: sum=3;
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51: sum=4;
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52: sum=3;
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53: sum=4;
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54: sum=4;
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55: sum=5;
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56: sum=3;
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57: sum=4;
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58: sum=4;
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59: sum=5;
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60: sum=4;
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61: sum=5;
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62: sum=5;
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63: sum=6;
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default: sum=0;
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endcase
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end
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endmodule |