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58 lines
1.2 KiB
Systemverilog
58 lines
1.2 KiB
Systemverilog
//--------------------------------------------------------------------------------
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// EdgeDetect.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Variable width edge detector
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// One tick propagation time
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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EdgeDetect #(
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.WIDTH( 32 )
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) ED1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.in( ),
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.rising( ),
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.falling( ),
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.both( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module EdgeDetect #(
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WIDTH = 1
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)(
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input clk,
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input nrst,
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input [(WIDTH-1):0] in,
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output logic [(WIDTH-1):0] rising = 0,
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output logic [(WIDTH-1):0] falling = 0,
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output [(WIDTH-1):0] both
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);
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logic [(WIDTH-1):0] in_prev = 0;
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always_ff @(posedge clk) begin
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if ( ~nrst ) begin
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in_prev <= 0;
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rising <= 0;
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falling <= 0;
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end
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else begin
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in_prev <= in;
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rising[(WIDTH-1):0] <= in[(WIDTH-1):0] & ~in_prev[(WIDTH-1):0];
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falling[(WIDTH-1):0] <= ~in[(WIDTH-1):0] & in_prev[(WIDTH-1):0];
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end
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end
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assign both[(WIDTH-1):0] = rising[(WIDTH-1):0] | falling[(WIDTH-1):0];
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endmodule
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