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95 lines
2.8 KiB
Verilog
95 lines
2.8 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 01-02-2007
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module adder_tree_tb ();
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reg [7:0] a,b,c;
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reg clk;
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wire [3*8-1:0] in_words;
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assign in_words = {c,b,a};
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initial begin
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a = 0;
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b = 0;
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c = 0;
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clk = 0;
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#10000000
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$display ("PASS");
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$stop();
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end
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wire [9:0] out_at0, simple_sum;
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assign simple_sum = a + b + c;
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adder_tree at0 (.clk(clk),.in_words(in_words),.out(out_at0),
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.extra_bit_in(1'b0),.extra_bit_out());
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defparam at0 .NUM_IN_WORDS = 3;
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defparam at0 .BITS_PER_IN_WORD = 8;
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defparam at0 .OUT_BITS = 10;
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defparam at0 .SIGN_EXT = 0;
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defparam at0 .REGISTER_OUTPUT = 0;
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defparam at0 .REGISTER_MIDDLE = 0;
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defparam at0 .SHIFT_DIST = 0;
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defparam at0 .EXTRA_BIT_USED = 0;
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wire [11:0] out_at1, shifted_sum;
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assign shifted_sum = a + (b << 1) + (c << 2);
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adder_tree at1 (.clk(clk),.in_words(in_words),.out(out_at1),
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.extra_bit_in(1'b0),.extra_bit_out());
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defparam at1 .NUM_IN_WORDS = 3;
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defparam at1 .BITS_PER_IN_WORD = 8;
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defparam at1 .OUT_BITS = 12;
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defparam at1 .SIGN_EXT = 0;
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defparam at1 .REGISTER_OUTPUT = 0;
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defparam at1 .REGISTER_MIDDLE = 0;
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defparam at1 .SHIFT_DIST = 1;
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defparam at1 .EXTRA_BIT_USED = 0;
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always @(negedge clk) begin
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a = $random();
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b = $random();
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c = $random();
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end
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always begin
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#100 clk = ~clk;
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end
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always @(posedge clk) begin
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#10
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if (out_at0 !== simple_sum) begin
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$display ("Mismatch on no-shift addition at time %d",$time);
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$stop();
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end
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if (out_at1 !== shifted_sum) begin
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$display ("Mismatch on shift addition at time %d",$time);
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$stop();
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end
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end
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endmodule
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