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97 lines
2.6 KiB
Verilog
97 lines
2.6 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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module uart_tb ();
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reg clk, rst;
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reg [7:0] tx_data;
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reg tx_data_valid;
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wire tx_data_ack;
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wire txd,rxd;
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wire [7:0] rx_data;
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wire rx_data_fresh;
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uart u (
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.clk(clk),
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.rst(rst),
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.tx_data(tx_data),
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.tx_data_valid(tx_data_valid),
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.tx_data_ack(tx_data_ack),
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.txd(txd),
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.rx_data(rx_data),
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.rx_data_fresh(rx_data_fresh),
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.rxd(rxd)
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);
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assign rxd = txd;
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initial begin
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clk = 0;
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rst = 1;
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tx_data_valid = 1'b0;
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@(posedge clk);
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@(negedge clk);
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rst = 0;
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end
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always begin
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#50 clk = ~clk;
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end
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// tx data driver
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always begin
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#1000 @(negedge clk) tx_data_valid = $random;
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end
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always @(posedge clk) begin
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if (rst) tx_data <= "a";
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else if (tx_data_ack) begin
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if (tx_data == "z") tx_data <= "a";
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else tx_data <= tx_data + 1'b1;
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end
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end
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// rx data checker
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reg fail = 0;
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reg [7:0] expected_rx;
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always @(posedge clk) begin
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if (rst) expected_rx <= "a";
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else if (rx_data_fresh) begin
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if (rx_data !== expected_rx) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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#1000
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$stop();
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end
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if (expected_rx == "z") expected_rx <= "a";
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else expected_rx <= expected_rx + 1'b1;
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end
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end
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initial begin
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#1000000 if (!fail) $display ("PASS");
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$stop();
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end
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endmodule |