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85 lines
2.7 KiB
Verilog
85 lines
2.7 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 02-23-2006
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// 64 bit equality compare with latency 3
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// Max 1 level of LUT logic between registers
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// Area - 21 6-LUT 5-5LUT 2-2LUT
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module pipe_equal (a,b,clk,rst,eq);
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input [63:0] a;
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input [63:0] b;
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input clk,rst;
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output eq;
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wire eq;
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wire [21:0] level_0;
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reg [21:0] level_0_r;
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reg [4:0] level_1_r;
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reg level_2_r;
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// Compute equality in 3 bit segments.
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genvar i;
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generate
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for (i=0; i<21; i=i+1)
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begin : l0
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wire [2:0] tmp_a;
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wire [2:0] tmp_b;
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assign tmp_a = a[3*i+2 : 3*i];
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assign tmp_b = b[3*i+2 : 3*i];
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assign level_0[i] = (tmp_a == tmp_b);
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end
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endgenerate
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assign level_0[21] = (a[63] == b[63]);
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// First pipe register stage
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always @(posedge clk or posedge rst) begin
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if (rst) level_0_r <= 22'b0;
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else level_0_r <= level_0;
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end
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// Start ANDing together the equality leaves
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// we need 2 levels of LUT, so relaxed to 5 LUT
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always @(posedge clk or posedge rst) begin
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if (rst) level_1_r <= 5'b0;
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else begin
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level_1_r[0] <= & level_0_r[4:0];
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level_1_r[1] <= & level_0_r[9:5];
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level_1_r[2] <= & level_0_r[14:10];
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level_1_r[3] <= & level_0_r[19:15];
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level_1_r[4] <= & level_0_r[21:20];
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end
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end
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// final AND
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always @(posedge clk or posedge rst) begin
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if (rst) level_2_r <= 1'b0;
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else begin
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level_2_r <= & level_1_r;
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end
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end
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assign eq = level_2_r;
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endmodule
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