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88 lines
3.1 KiB
Verilog
88 lines
3.1 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module lfsr (clk,rst,out);
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parameter WIDTH = 32;
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input clk,rst;
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output [WIDTH-1:0] out;
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reg [WIDTH-1:0] myreg;
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// nice looking max period polys selected from
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// the internet
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wire [WIDTH-1:0] poly =
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(WIDTH == 4) ? 4'hc :
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(WIDTH == 5) ? 5'h1b :
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(WIDTH == 6) ? 6'h33 :
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(WIDTH == 7) ? 7'h65 :
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(WIDTH == 8) ? 8'hc3 :
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(WIDTH == 9) ? 9'h167 :
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(WIDTH == 10) ? 10'h309 :
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(WIDTH == 11) ? 11'h4ec :
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(WIDTH == 12) ? 12'hac9 :
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(WIDTH == 13) ? 13'h124d :
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(WIDTH == 14) ? 14'h2367 :
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(WIDTH == 15) ? 15'h42f9 :
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(WIDTH == 16) ? 16'h847d :
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(WIDTH == 17) ? 17'h101f5 :
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(WIDTH == 18) ? 18'h202c9 :
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(WIDTH == 19) ? 19'h402fa :
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(WIDTH == 20) ? 20'h805c1 :
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(WIDTH == 21) ? 21'h1003cb :
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(WIDTH == 22) ? 22'h20029f :
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(WIDTH == 23) ? 23'h4003da :
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(WIDTH == 24) ? 24'h800a23 :
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(WIDTH == 25) ? 25'h10001a5 :
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(WIDTH == 26) ? 26'h2000155 :
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(WIDTH == 27) ? 27'h4000227 :
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(WIDTH == 28) ? 28'h80007db :
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(WIDTH == 29) ? 29'h100004f3 :
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(WIDTH == 30) ? 30'h200003ab :
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(WIDTH == 31) ? 31'h40000169 :
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(WIDTH == 32) ? 32'h800007c3 : 0;
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initial begin
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// unsupported width? Fatality.
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#100 if (poly == 0) begin
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$display ("Illegal polynomial selected");
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$stop;
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end
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end
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wire [WIDTH-1:0] feedback;
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assign feedback = {WIDTH{myreg[WIDTH-1]}} & poly;
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// the inverter on the LSB causes 000... to be a
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// sequence member rather than the frozen state
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always @(posedge clk or posedge rst) begin
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if (rst) myreg <= 0;
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else begin
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myreg <= ((myreg ^ feedback) << 1) | !myreg[WIDTH-1];
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end
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end
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assign out = myreg;
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endmodule
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