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306 lines
11 KiB
Verilog
306 lines
11 KiB
Verilog
/*
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Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
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use of Altera Corporation's design tools, logic functions and other
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software and tools, and its AMPP partner logic functions, and any
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output files any of the foregoing (including device programming or
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simulation files), and any associated documentation or information are
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expressly subject to the terms and conditions of the Altera Program
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License Subscription Agreement or other applicable license agreement,
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including, without limitation, that your use is for the sole purpose
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of programming logic devices manufactured by Altera and sold by Altera
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or its authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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/*
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Author: JCJB
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Date: 11/04/2007
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This bursting write master is passed a word aligned address, length in bytes,
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and a 'go' bit. The master will continue to post full length bursts until
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the length register reaches a value less than a full burst. A single final
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burst is then posted when enough data has been buffered and then the done bit
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will be asserted.
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To use this master you must simply drive the control signals into this block,
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and also write the data to the exposed write FIFO. To read from the exposed FIFO
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use the 'user_write_buffer' signal to push data into the FIFO 'user_buffer_data'.
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The signal 'user_buffer_full' is asserted whenever the exposed buffer is full.
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You should not attempt to write data to the exposed FIFO if it is full.
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*/
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// altera message_off 10230
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module burst_write_master (
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clk,
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reset,
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// control inputs and outputs
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control_fixed_location,
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control_write_base,
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control_write_length,
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control_go,
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control_done,
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// user logic inputs and outputs
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user_write_buffer,
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user_buffer_data,
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user_buffer_full,
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// master inputs and outputs
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master_address,
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master_write,
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master_byteenable,
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master_writedata,
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master_burstcount,
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master_waitrequest
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);
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parameter DATAWIDTH = 32;
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parameter MAXBURSTCOUNT = 4;
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parameter BURSTCOUNTWIDTH = 3;
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parameter BYTEENABLEWIDTH = 4;
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parameter ADDRESSWIDTH = 32;
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parameter FIFODEPTH = 32; // must be at least twice MAXBURSTCOUNT in order to be efficient
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parameter FIFODEPTH_LOG2 = 5;
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parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
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input clk;
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input reset;
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// control inputs and outputs
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input control_fixed_location; // this only makes sense to enable when MAXBURSTCOUNT = 1
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input [ADDRESSWIDTH-1:0] control_write_base;
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input [ADDRESSWIDTH-1:0] control_write_length;
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input control_go;
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output wire control_done;
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// user logic inputs and outputs
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input user_write_buffer;
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input [DATAWIDTH-1:0] user_buffer_data;
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output wire user_buffer_full;
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// master inputs and outputs
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input master_waitrequest;
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output reg [ADDRESSWIDTH-1:0] master_address;
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output wire master_write;
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output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
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output wire [DATAWIDTH-1:0] master_writedata;
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output reg [BURSTCOUNTWIDTH-1:0] master_burstcount;
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// internal control signals
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reg control_fixed_location_d1;
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reg [ADDRESSWIDTH-1:0] length;
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wire final_short_burst_enable; // when the length is less than MAXBURSTCOUNT * # of bytes per word (BYTEENABLEWIDTH) (i.e. end of the transfer)
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wire final_short_burst_ready; // when there is enough data in the FIFO for the final burst
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wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address; // represents the word offset within the burst boundary
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wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
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wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
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wire first_short_burst_enable; // when the transfer doesn't start on a burst boundary
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wire first_short_burst_ready; // when there is enough data in the FIFO to get the master back into burst alignment
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wire full_burst_ready; // when there is enough data in the FIFO for a full burst
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wire increment_address; // this increments the 'address' register when write is asserted and waitrequest is de-asserted
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wire burst_begin; // used to register the registers 'burst_address' and 'burst_count_d1' as well as drive the master_address and burst_count muxes
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wire read_fifo;
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wire [FIFODEPTH_LOG2-1:0] fifo_used; // going to combined used with the full bit
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wire [BURSTCOUNTWIDTH-1:0] burst_count; // watermark of the FIFO, it has a latency of 2 cycles
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reg [BURSTCOUNTWIDTH-1:0] burst_counter;
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reg first_transfer; // need to keep track of the first burst so that we don't incorrectly increment the address
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// registering the control_fixed_location bit
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always @ (posedge clk or posedge reset)
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begin
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if (reset == 1)
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begin
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control_fixed_location_d1 <= 0;
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end
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else
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begin
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if (control_go == 1)
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begin
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control_fixed_location_d1 <= control_fixed_location;
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end
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end
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end
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// set when control_go fires, and reset once the first burst starts
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always @ (posedge clk or posedge reset)
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begin
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if (reset == 1)
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begin
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first_transfer <= 0;
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end
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else
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begin
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if (control_go == 1)
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begin
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first_transfer <= 1;
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end
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else if (burst_begin == 1)
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begin
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first_transfer <= 0;
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end
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end
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end
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// master address (held constant during burst)
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always @ (posedge clk or posedge reset)
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begin
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if (reset == 1)
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begin
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master_address <= 0;
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end
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else
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begin
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if (control_go == 1)
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begin
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master_address <= control_write_base;
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end
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else if ((first_transfer == 0) & (burst_begin == 1) & (control_fixed_location_d1 == 0))
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begin
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master_address <= master_address + (master_burstcount * BYTEENABLEWIDTH); // we don't want address + BYTEENABLEWIDTH for the first access
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end
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end
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end
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// master length logic
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always @ (posedge clk or posedge reset)
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begin
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if (reset == 1)
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begin
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length <= 0;
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end
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else
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begin
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if (control_go == 1)
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begin
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length <= control_write_length;
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end
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else if (increment_address == 1)
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begin
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length <= length - BYTEENABLEWIDTH; // always performing word size accesses
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end
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end
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end
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// register the master burstcount (held constant during burst)
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always @ (posedge clk or posedge reset)
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begin
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if (reset == 1)
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begin
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master_burstcount <= 0;
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end
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else
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begin
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if (burst_begin == 1)
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begin
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master_burstcount <= burst_count;
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end
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end
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end
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// burst counter. This is set to the burst count being posted then counts down when each word
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// of data goes out. If it reaches 0 (i.e. not reloaded after 1) then the master stalls due to
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// a lack of data to post a new burst.
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always @ (posedge clk or posedge reset)
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begin
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if (reset == 1)
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begin
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burst_counter <= 0;
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end
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else
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begin
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if (control_go == 1)
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begin
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burst_counter <= 0;
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end
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else if (burst_begin == 1)
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begin
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burst_counter <= burst_count;
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end
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else if (increment_address == 1) // decrements each write, burst_counter will only hit 0 if burst begin doesn't fire on the next cycle
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begin
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burst_counter <= burst_counter - 1;
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end
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end
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end
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// burst boundaries are on the master "width * maximum burst count". The burst boundary word address will be used to determine how far off the boundary the transfer starts from.
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assign burst_boundary_word_address = ((master_address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
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// first short burst enable will only be active on the first transfer (if applicable). It will either post the amount of words remaining to reach the end of the burst
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// boundary or post the remainder of the transfer whichever is shorter. If the transfer is very short and not aligned on a burst boundary then the same logic as the final short transfer is used
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assign first_short_burst_enable = (burst_boundary_word_address != 0) & (first_transfer == 1);
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assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
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(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
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(MAXBURSTCOUNT - burst_boundary_word_address) : final_short_burst_count);
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assign first_short_burst_ready = (fifo_used > first_short_burst_count) | ((fifo_used == first_short_burst_count) & (burst_counter == 0));
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// when there isn't enough data for a full burst at the end of the transfer a short burst is sent out instead
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assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
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assign final_short_burst_count = (length/BYTEENABLEWIDTH);
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assign final_short_burst_ready = (fifo_used > final_short_burst_count) | ((fifo_used == final_short_burst_count) & (burst_counter == 0)); // this will add a one cycle stall between bursts, since fifo_used has a cycle of latency, this only affects the last burst
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// since the fifo has a latency of 1 we need to make sure we don't under flow
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assign full_burst_ready = (fifo_used > MAXBURSTCOUNT) | ((fifo_used == MAXBURSTCOUNT) & (burst_counter == 0)); // when fifo used watermark equals the burst count the statemachine must stall for one cycle, this will make sure that when a burst begins there really is enough data present in the FIFO
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assign master_byteenable = -1; // all ones, always performing word size accesses
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assign control_done = (length == 0);
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assign master_write = (control_done == 0) & (burst_counter != 0); // burst_counter = 0 means the transfer is done, or not enough data in the fifo for a new burst
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// fifo controls and the burst_begin responsible for timing most of the circuit, burst_begin starts the writing statemachine
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assign burst_begin = (((first_short_burst_enable == 1) & (first_short_burst_ready == 1))
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| ((final_short_burst_enable == 1) & (final_short_burst_ready == 1))
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| (full_burst_ready == 1))
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& (control_done == 0) // since the FIFO can have data before the master starts we need to disable this bit from firing when length = 0
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& ((burst_counter == 0) | ((burst_counter == 1) & (master_waitrequest == 0) & (length > (MAXBURSTCOUNT * BYTEENABLEWIDTH)))); // need to make a short final burst doesn't start right after a full burst completes.
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assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // alignment correction gets priority, if the transfer is short and unaligned this will cover both
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(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
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assign increment_address = (master_write == 1) & (master_waitrequest == 0); // writing is occuring without wait states
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assign read_fifo = increment_address;
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// write data feed by user logic
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scfifo the_user_to_master_fifo (
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.aclr (reset),
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.usedw (fifo_used),
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.clock (clk),
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.data (user_buffer_data),
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.almost_full (user_buffer_full),
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.q (master_writedata),
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.rdreq (read_fifo),
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.wrreq (user_write_buffer)
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);
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defparam the_user_to_master_fifo.lpm_width = DATAWIDTH;
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defparam the_user_to_master_fifo.lpm_numwords = FIFODEPTH;
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defparam the_user_to_master_fifo.lpm_showahead = "ON";
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defparam the_user_to_master_fifo.almost_full_value = (FIFODEPTH - 2);
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defparam the_user_to_master_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
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defparam the_user_to_master_fifo.add_ram_output_register = "OFF"; // makes timing the burst begin single simplier
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defparam the_user_to_master_fifo.underflow_checking = "OFF";
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defparam the_user_to_master_fifo.overflow_checking = "OFF";
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endmodule
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