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53 lines
1.5 KiB
Verilog
53 lines
1.5 KiB
Verilog
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT2.v,v 1.6 2005/03/14 22:32:54 yanx Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.13)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / 2-input Look-Up-Table with General Output
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// /___/ /\ Filename : LUT2.v
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// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf.
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// End Revision
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`timescale 100 ps / 10 ps
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module LUT2 (O, I0, I1);
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parameter INIT = 4'h0;
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input I0, I1;
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output O;
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reg O;
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wire [1:0] s;
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assign s = {I1, I0};
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always @(s)
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if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
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O = INIT[s];
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else if ((INIT[0] == INIT[1]) && (INIT[2] == INIT[3]) && (INIT[0] == INIT[2]))
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O = INIT[0];
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else if ((s[1] == 0) && (INIT[0] == INIT[1]))
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O = INIT[0];
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else if ((s[1] == 1) && (INIT[2] == INIT[3]))
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O = INIT[2];
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else if ((s[0] == 0) && (INIT[0] == INIT[2]))
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O = INIT[0];
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else if ((s[0] == 1) && (INIT[1] == INIT[3]))
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O = INIT[1];
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else
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O = 1'bx;
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endmodule
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