2023-06-26 11:44:57 -07:00
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// SPDX-License-Identifier: BSD-2-Clause-Views
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2022-07-29 12:02:50 -07:00
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/*
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2023-06-26 11:44:57 -07:00
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* Copyright (c) 2022-2023 The Regents of the University of California
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*/
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2022-07-29 12:02:50 -07:00
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#ifndef XCVR_GTHE3_H
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#define XCVR_GTHE3_H
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#include "xcvr_gt.h"
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#include "gt/gthe3_regs.h"
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// signals
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#define GTHE3_COM_QPLL0_RESET_ADDR 0x10000
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#define GTHE3_COM_QPLL0_RESET_MSB 0
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#define GTHE3_COM_QPLL0_RESET_LSB 0
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#define GTHE3_COM_QPLL0_RESET_MASK BIT_MASK(GTHE3_COM_QPLL0_RESET_MSB, GTHE3_COM_QPLL0_RESET_LSB)
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#define GTHE3_COM_QPLL0_LOCK_ADDR 0x10000
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#define GTHE3_COM_QPLL0_LOCK_MSB 8
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#define GTHE3_COM_QPLL0_LOCK_LSB 8
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#define GTHE3_COM_QPLL0_LOCK_MASK BIT_MASK(GTHE3_COM_QPLL0_LOCK_MSB, GTHE3_COM_QPLL0_LOCK_LSB)
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#define GTHE3_COM_QPLL0_PD_ADDR 0x10001
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#define GTHE3_COM_QPLL0_PD_MSB 0
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#define GTHE3_COM_QPLL0_PD_LSB 0
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#define GTHE3_COM_QPLL0_PD_MASK BIT_MASK(GTHE3_COM_QPLL0_PD_MSB, GTHE3_COM_QPLL0_PD_LSB)
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#define GTHE3_COM_QPLL1_RESET_ADDR 0x11000
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#define GTHE3_COM_QPLL1_RESET_MSB 0
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#define GTHE3_COM_QPLL1_RESET_LSB 0
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#define GTHE3_COM_QPLL1_RESET_MASK BIT_MASK(GTHE3_COM_QPLL0_RESET_MSB, GTHE3_COM_QPLL0_RESET_LSB)
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#define GTHE3_COM_QPLL1_LOCK_ADDR 0x11000
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#define GTHE3_COM_QPLL1_LOCK_MSB 8
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#define GTHE3_COM_QPLL1_LOCK_LSB 8
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#define GTHE3_COM_QPLL1_LOCK_MASK BIT_MASK(GTHE3_COM_QPLL0_LOCK_MSB, GTHE3_COM_QPLL0_LOCK_LSB)
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#define GTHE3_COM_QPLL1_PD_ADDR 0x11001
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#define GTHE3_COM_QPLL1_PD_MSB 0
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#define GTHE3_COM_QPLL1_PD_LSB 0
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#define GTHE3_COM_QPLL1_PD_MASK BIT_MASK(GTHE3_COM_QPLL1_PD_MSB, GTHE3_COM_QPLL1_PD_LSB)
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#define GTHE3_CH_TX_RESET_ADDR 0x10000
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#define GTHE3_CH_TX_RESET_MSB 0
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#define GTHE3_CH_TX_RESET_LSB 0
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#define GTHE3_CH_TX_RESET_MASK BIT_MASK(GTHE3_CH_TX_RESET_MSB, GTHE3_CH_TX_RESET_LSB)
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#define GTHE3_CH_TX_PMA_RESET_ADDR 0x10000
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#define GTHE3_CH_TX_PMA_RESET_MSB 1
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#define GTHE3_CH_TX_PMA_RESET_LSB 1
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#define GTHE3_CH_TX_PMA_RESET_MASK BIT_MASK(GTHE3_CH_TX_PMA_RESET_MSB, GTHE3_CH_TX_PMA_RESET_LSB)
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#define GTHE3_CH_TX_PCS_RESET_ADDR 0x10000
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#define GTHE3_CH_TX_PCS_RESET_MSB 2
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#define GTHE3_CH_TX_PCS_RESET_LSB 2
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#define GTHE3_CH_TX_PCS_RESET_MASK BIT_MASK(GTHE3_CH_TX_PCS_RESET_MSB, GTHE3_CH_TX_PCS_RESET_LSB)
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#define GTHE3_CH_TX_RESET_DONE_ADDR 0x10000
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#define GTHE3_CH_TX_RESET_DONE_MSB 8
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#define GTHE3_CH_TX_RESET_DONE_LSB 8
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#define GTHE3_CH_TX_RESET_DONE_MASK BIT_MASK(GTHE3_CH_TX_RESET_DONE_MSB, GTHE3_CH_TX_RESET_DONE_LSB)
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#define GTHE3_CH_TX_GT_RESET_DONE_ADDR 0x10000
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#define GTHE3_CH_TX_GT_RESET_DONE_MSB 9
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#define GTHE3_CH_TX_GT_RESET_DONE_LSB 9
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#define GTHE3_CH_TX_GT_RESET_DONE_MASK BIT_MASK(GTHE3_CH_TX_GT_RESET_DONE_MSB, GTHE3_CH_TX_GT_RESET_DONE_LSB)
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#define GTHE3_CH_TX_PMA_RESET_DONE_ADDR 0x10000
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#define GTHE3_CH_TX_PMA_RESET_DONE_MSB 10
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#define GTHE3_CH_TX_PMA_RESET_DONE_LSB 10
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#define GTHE3_CH_TX_PMA_RESET_DONE_MASK BIT_MASK(GTHE3_CH_TX_PMA_RESET_DONE_MSB, GTHE3_CH_TX_PMA_RESET_DONE_LSB)
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#define GTHE3_CH_TX_PRGDIV_RESET_DONE_ADDR 0x10000
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#define GTHE3_CH_TX_PRGDIV_RESET_DONE_MSB 11
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#define GTHE3_CH_TX_PRGDIV_RESET_DONE_LSB 11
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#define GTHE3_CH_TX_PRGDIV_RESET_DONE_MASK BIT_MASK(GTHE3_CH_TX_PRGDIV_RESET_DONE_MSB, GTHE3_CH_TX_PRGDIV_RESET_DONE_LSB)
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#define GTHE3_CH_TX_USRCLK_ACT_ADDR 0x10000
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#define GTHE3_CH_TX_USRCLK_ACT_MSB 12
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#define GTHE3_CH_TX_USRCLK_ACT_LSB 12
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#define GTHE3_CH_TX_USRCLK_ACT_MASK BIT_MASK(GTHE3_CH_TX_USRCLK_ACT_MSB, GTHE3_CH_TX_USRCLK_ACT_LSB)
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#define GTHE3_CH_TX_PD_ADDR 0x10001
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#define GTHE3_CH_TX_PD_MSB 0
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#define GTHE3_CH_TX_PD_LSB 0
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#define GTHE3_CH_TX_PD_MASK BIT_MASK(GTHE3_CH_TX_PD_MSB, GTHE3_CH_TX_PD_LSB)
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#define GTHE3_CH_TX_QPLL_SEL_ADDR 0x10001
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#define GTHE3_CH_TX_QPLL_SEL_MSB 1
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#define GTHE3_CH_TX_QPLL_SEL_LSB 1
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#define GTHE3_CH_TX_QPLL_SEL_MASK BIT_MASK(GTHE3_CH_TX_QPLL_SEL_MSB, GTHE3_CH_TX_QPLL_SEL_LSB)
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#define GTHE3_CH_TX_POLARITY_ADDR 0x10010
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#define GTHE3_CH_TX_POLARITY_MSB 0
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#define GTHE3_CH_TX_POLARITY_LSB 0
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#define GTHE3_CH_TX_POLARITY_MASK BIT_MASK(GTHE3_CH_TX_POLARITY_MSB, GTHE3_CH_TX_POLARITY_LSB)
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#define GTHE3_CH_TX_ELECIDLE_ADDR 0x10010
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#define GTHE3_CH_TX_ELECIDLE_MSB 1
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#define GTHE3_CH_TX_ELECIDLE_LSB 1
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#define GTHE3_CH_TX_ELECIDLE_MASK BIT_MASK(GTHE3_CH_TX_ELECIDLE_MSB, GTHE3_CH_TX_ELECIDLE_LSB)
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#define GTHE3_CH_TX_INHIBIT_ADDR 0x10010
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#define GTHE3_CH_TX_INHIBIT_MSB 2
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#define GTHE3_CH_TX_INHIBIT_LSB 2
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#define GTHE3_CH_TX_INHIBIT_MASK BIT_MASK(GTHE3_CH_TX_INHIBIT_MSB, GTHE3_CH_TX_INHIBIT_LSB)
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#define GTHE3_CH_TX_DIFFCTRL_ADDR 0x10011
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#define GTHE3_CH_TX_DIFFCTRL_MSB 4
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#define GTHE3_CH_TX_DIFFCTRL_LSB 0
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#define GTHE3_CH_TX_DIFFCTRL_MASK BIT_MASK(GTHE3_CH_TX_DIFFCTRL_MSB, GTHE3_CH_TX_DIFFCTRL_LSB)
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#define GTHE3_CH_TX_MAINCURSOR_ADDR 0x10012
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#define GTHE3_CH_TX_MAINCURSOR_MSB 6
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#define GTHE3_CH_TX_MAINCURSOR_LSB 0
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#define GTHE3_CH_TX_MAINCURSOR_MASK BIT_MASK(GTHE3_CH_TX_MAINCURSOR_MSB, GTHE3_CH_TX_MAINCURSOR_LSB)
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#define GTHE3_CH_TX_PRECURSOR_ADDR 0x10013
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#define GTHE3_CH_TX_PRECURSOR_MSB 4
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#define GTHE3_CH_TX_PRECURSOR_LSB 0
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#define GTHE3_CH_TX_PRECURSOR_MASK BIT_MASK(GTHE3_CH_TX_PRECURSOR_MSB, GTHE3_CH_TX_PRECURSOR_LSB)
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#define GTHE3_CH_TX_POSTCURSOR_ADDR 0x10014
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#define GTHE3_CH_TX_POSTCURSOR_MSB 4
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#define GTHE3_CH_TX_POSTCURSOR_LSB 0
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#define GTHE3_CH_TX_POSTCURSOR_MASK BIT_MASK(GTHE3_CH_TX_POSTCURSOR_MSB, GTHE3_CH_TX_POSTCURSOR_LSB)
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#define GTHE3_CH_TX_PRBS_SEL_ADDR 0x10040
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#define GTHE3_CH_TX_PRBS_SEL_MSB 3
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#define GTHE3_CH_TX_PRBS_SEL_LSB 0
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#define GTHE3_CH_TX_PRBS_SEL_MASK BIT_MASK(GTHE3_CH_TX_PRBS_SEL_MSB, GTHE3_CH_TX_PRBS_SEL_LSB)
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#define GTHE3_CH_TX_PRBS_FORCERR_ADDR 0x10040
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#define GTHE3_CH_TX_PRBS_FORCERR_MSB 15
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#define GTHE3_CH_TX_PRBS_FORCERR_LSB 0
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#define GTHE3_CH_TX_PRBS_FORCERR_MASK BIT_MASK(GTHE3_CH_TX_PRBS_FORCERR_MSB, GTHE3_CH_TX_PRBS_FORCERR_LSB)
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#define GTHE3_CH_RX_RESET_ADDR 0x11000
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#define GTHE3_CH_RX_RESET_MSB 0
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#define GTHE3_CH_RX_RESET_LSB 0
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#define GTHE3_CH_RX_RESET_MASK BIT_MASK(GTHE3_CH_RX_RESET_MSB, GTHE3_CH_RX_RESET_LSB)
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#define GTHE3_CH_RX_PMA_RESET_ADDR 0x11000
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#define GTHE3_CH_RX_PMA_RESET_MSB 1
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#define GTHE3_CH_RX_PMA_RESET_LSB 1
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#define GTHE3_CH_RX_PMA_RESET_MASK BIT_MASK(GTHE3_CH_RX_PMA_RESET_MSB, GTHE3_CH_RX_PMA_RESET_LSB)
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#define GTHE3_CH_RX_PCS_RESET_ADDR 0x11000
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#define GTHE3_CH_RX_PCS_RESET_MSB 2
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#define GTHE3_CH_RX_PCS_RESET_LSB 2
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#define GTHE3_CH_RX_PCS_RESET_MASK BIT_MASK(GTHE3_CH_RX_PCS_RESET_MSB, GTHE3_CH_RX_PCS_RESET_LSB)
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#define GTHE3_CH_RX_DFE_LPM_RESET_ADDR 0x11000
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#define GTHE3_CH_RX_DFE_LPM_RESET_MSB 3
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#define GTHE3_CH_RX_DFE_LPM_RESET_LSB 3
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#define GTHE3_CH_RX_DFE_LPM_RESET_MASK BIT_MASK(GTHE3_CH_RX_DFE_LPM_RESET_MSB, GTHE3_CH_RX_DFE_LPM_RESET_LSB)
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#define GTHE3_CH_EYESCAN_RESET_ADDR 0x11000
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#define GTHE3_CH_EYESCAN_RESET_MSB 4
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#define GTHE3_CH_EYESCAN_RESET_LSB 4
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#define GTHE3_CH_EYESCAN_RESET_MASK BIT_MASK(GTHE3_CH_EYESCAN_RESET_MSB, GTHE3_CH_EYESCAN_RESET_LSB)
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#define GTHE3_CH_RX_RESET_DONE_ADDR 0x11000
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#define GTHE3_CH_RX_RESET_DONE_MSB 8
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#define GTHE3_CH_RX_RESET_DONE_LSB 8
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#define GTHE3_CH_RX_RESET_DONE_MASK BIT_MASK(GTHE3_CH_RX_RESET_DONE_MSB, GTHE3_CH_RX_RESET_DONE_LSB)
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#define GTHE3_CH_RX_GT_RESET_DONE_ADDR 0x11000
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#define GTHE3_CH_RX_GT_RESET_DONE_MSB 9
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#define GTHE3_CH_RX_GT_RESET_DONE_LSB 9
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#define GTHE3_CH_RX_GT_RESET_DONE_MASK BIT_MASK(GTHE3_CH_RX_GT_RESET_DONE_MSB, GTHE3_CH_RX_GT_RESET_DONE_LSB)
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#define GTHE3_CH_RX_PMA_RESET_DONE_ADDR 0x11000
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#define GTHE3_CH_RX_PMA_RESET_DONE_MSB 10
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#define GTHE3_CH_RX_PMA_RESET_DONE_LSB 10
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#define GTHE3_CH_RX_PMA_RESET_DONE_MASK BIT_MASK(GTHE3_CH_RX_PMA_RESET_DONE_MSB, GTHE3_CH_RX_PMA_RESET_DONE_LSB)
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#define GTHE3_CH_RX_PRGDIV_RESET_DONE_ADDR 0x11000
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#define GTHE3_CH_RX_PRGDIV_RESET_DONE_MSB 11
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#define GTHE3_CH_RX_PRGDIV_RESET_DONE_LSB 11
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#define GTHE3_CH_RX_PRGDIV_RESET_DONE_MASK BIT_MASK(GTHE3_CH_RX_PRGDIV_RESET_DONE_MSB, GTHE3_CH_RX_PRGDIV_RESET_DONE_LSB)
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#define GTHE3_CH_RX_USRCLK_ACT_ADDR 0x11000
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#define GTHE3_CH_RX_USRCLK_ACT_MSB 12
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#define GTHE3_CH_RX_USRCLK_ACT_LSB 12
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#define GTHE3_CH_RX_USRCLK_ACT_MASK BIT_MASK(GTHE3_CH_RX_USRCLK_ACT_MSB, GTHE3_CH_RX_USRCLK_ACT_LSB)
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#define GTHE3_CH_RX_PD_ADDR 0x11001
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#define GTHE3_CH_RX_PD_MSB 0
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#define GTHE3_CH_RX_PD_LSB 0
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#define GTHE3_CH_RX_PD_MASK BIT_MASK(GTHE3_CH_RX_PD_MSB, GTHE3_CH_RX_PD_LSB)
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#define GTHE3_CH_RX_QPLL_SEL_ADDR 0x11001
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#define GTHE3_CH_RX_QPLL_SEL_MSB 1
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#define GTHE3_CH_RX_QPLL_SEL_LSB 1
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#define GTHE3_CH_RX_QPLL_SEL_MASK BIT_MASK(GTHE3_CH_RX_QPLL_SEL_MSB, GTHE3_CH_RX_QPLL_SEL_LSB)
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#define GTHE3_CH_LOOPBACK_ADDR 0x11002
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#define GTHE3_CH_LOOPBACK_MSB 2
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#define GTHE3_CH_LOOPBACK_LSB 0
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#define GTHE3_CH_LOOPBACK_MASK BIT_MASK(GTHE3_CH_LOOPBACK_MSB, GTHE3_CH_LOOPBACK_LSB)
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#define GTHE3_CH_RX_POLARITY_ADDR 0x11010
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#define GTHE3_CH_RX_POLARITY_MSB 0
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#define GTHE3_CH_RX_POLARITY_LSB 0
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#define GTHE3_CH_RX_POLARITY_MASK BIT_MASK(GTHE3_CH_RX_POLARITY_MSB, GTHE3_CH_RX_POLARITY_LSB)
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#define GTHE3_CH_RX_CDR_HOLD_ADDR 0x11020
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#define GTHE3_CH_RX_CDR_HOLD_MSB 0
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#define GTHE3_CH_RX_CDR_HOLD_LSB 0
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#define GTHE3_CH_RX_CDR_HOLD_MASK BIT_MASK(GTHE3_CH_RX_CDR_HOLD_MSB, GTHE3_CH_RX_CDR_HOLD_LSB)
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#define GTHE3_CH_RX_CDR_LOCK_ADDR 0x11020
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#define GTHE3_CH_RX_CDR_LOCK_MSB 8
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#define GTHE3_CH_RX_CDR_LOCK_LSB 8
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#define GTHE3_CH_RX_CDR_LOCK_MASK BIT_MASK(GTHE3_CH_RX_CDR_LOCK_MSB, GTHE3_CH_RX_CDR_LOCK_LSB)
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#define GTHE3_CH_RX_LPM_EN_ADDR 0x11024
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#define GTHE3_CH_RX_LPM_EN_MSB 0
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#define GTHE3_CH_RX_LPM_EN_LSB 0
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#define GTHE3_CH_RX_LPM_EN_MASK BIT_MASK(GTHE3_CH_RX_LPM_EN_MSB, GTHE3_CH_RX_LPM_EN_LSB)
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#define GTHE3_CH_RX_DMONITOR_ADDR 0x11028
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#define GTHE3_CH_RX_DMONITOR_MSB 7
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#define GTHE3_CH_RX_DMONITOR_LSB 0
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#define GTHE3_CH_RX_DMONITOR_MASK BIT_MASK(GTHE3_CH_RX_DMONITOR_MSB, GTHE3_CH_RX_DMONITOR_LSB)
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#define GTHE3_CH_RX_PRBS_SEL_ADDR 0x11040
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#define GTHE3_CH_RX_PRBS_SEL_MSB 3
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#define GTHE3_CH_RX_PRBS_SEL_LSB 0
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#define GTHE3_CH_RX_PRBS_SEL_MASK BIT_MASK(GTHE3_CH_RX_PRBS_SEL_MSB, GTHE3_CH_RX_PRBS_SEL_LSB)
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#define GTHE3_CH_RX_PRBS_CNT_RESET_ADDR 0x11041
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#define GTHE3_CH_RX_PRBS_CNT_RESET_MSB 0
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#define GTHE3_CH_RX_PRBS_CNT_RESET_LSB 0
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#define GTHE3_CH_RX_PRBS_CNT_RESET_MASK BIT_MASK(GTHE3_CH_RX_PRBS_CNT_RESET_MSB, GTHE3_CH_RX_PRBS_CNT_RESET_LSB)
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#define GTHE3_CH_RX_PRBS_LOCKED_ADDR 0x11041
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#define GTHE3_CH_RX_PRBS_LOCKED_MSB 8
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#define GTHE3_CH_RX_PRBS_LOCKED_LSB 8
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#define GTHE3_CH_RX_PRBS_LOCKED_MASK BIT_MASK(GTHE3_CH_RX_PRBS_LOCKED_MSB, GTHE3_CH_RX_PRBS_LOCKED_LSB)
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#define GTHE3_CH_RX_PRBS_ERROR_ADDR 0x11041
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#define GTHE3_CH_RX_PRBS_ERROR_MSB 9
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#define GTHE3_CH_RX_PRBS_ERROR_LSB 9
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#define GTHE3_CH_RX_PRBS_ERROR_MASK BIT_MASK(GTHE3_CH_RX_PRBS_ERROR_MSB, GTHE3_CH_RX_PRBS_ERROR_LSB)
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_reset, GTHE3_COM_QPLL0_RESET_ADDR, GTHE3_COM_QPLL0_RESET_MASK, GTHE3_COM_QPLL0_RESET_LSB);
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int gthe3_pll_qpll0_reset(struct gt_pll *pll);
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def_gt_pll_masked_reg_read16(gthe3, qpll0_lock, GTHE3_COM_QPLL0_LOCK_ADDR, GTHE3_COM_QPLL0_LOCK_MASK, GTHE3_COM_QPLL0_LOCK_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_pd, GTHE3_COM_QPLL0_PD_ADDR, GTHE3_COM_QPLL0_PD_MASK, GTHE3_COM_QPLL0_PD_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_reset, GTHE3_COM_QPLL1_RESET_ADDR, GTHE3_COM_QPLL1_RESET_MASK, GTHE3_COM_QPLL1_RESET_LSB);
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int gthe3_pll_qpll1_reset(struct gt_pll *pll);
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def_gt_pll_masked_reg_read16(gthe3, qpll1_lock, GTHE3_COM_QPLL1_LOCK_ADDR, GTHE3_COM_QPLL1_LOCK_MASK, GTHE3_COM_QPLL1_LOCK_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_pd, GTHE3_COM_QPLL1_PD_ADDR, GTHE3_COM_QPLL1_PD_MASK, GTHE3_COM_QPLL1_PD_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_reset, GTHE3_CH_TX_RESET_ADDR, GTHE3_CH_TX_RESET_MASK, GTHE3_CH_TX_RESET_LSB);
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int gthe3_ch_tx_reset(struct gt_ch *ch);
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def_gt_ch_masked_reg_rw16(gthe3, tx_pma_reset, GTHE3_CH_TX_PMA_RESET_ADDR, GTHE3_CH_TX_PMA_RESET_MASK, GTHE3_CH_TX_PMA_RESET_LSB);
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int gthe3_ch_tx_pma_reset(struct gt_ch *ch);
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def_gt_ch_masked_reg_rw16(gthe3, tx_pcs_reset, GTHE3_CH_TX_PCS_RESET_ADDR, GTHE3_CH_TX_PCS_RESET_MASK, GTHE3_CH_TX_PCS_RESET_LSB);
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int gthe3_ch_tx_pcs_reset(struct gt_ch *ch);
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def_gt_ch_masked_reg_read16(gthe3, tx_reset_done, GTHE3_CH_TX_RESET_DONE_ADDR, GTHE3_CH_TX_RESET_DONE_MASK, GTHE3_CH_TX_RESET_DONE_LSB);
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def_gt_ch_masked_reg_read16(gthe3, tx_gt_reset_done, GTHE3_CH_TX_GT_RESET_DONE_ADDR, GTHE3_CH_TX_GT_RESET_DONE_MASK, GTHE3_CH_TX_GT_RESET_DONE_LSB);
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def_gt_ch_masked_reg_read16(gthe3, tx_pma_reset_done, GTHE3_CH_TX_PMA_RESET_DONE_ADDR, GTHE3_CH_TX_PMA_RESET_DONE_MASK, GTHE3_CH_TX_PMA_RESET_DONE_LSB);
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def_gt_ch_masked_reg_read16(gthe3, tx_prgdiv_reset_done, GTHE3_CH_TX_PRGDIV_RESET_DONE_ADDR, GTHE3_CH_TX_PRGDIV_RESET_DONE_MASK, GTHE3_CH_TX_PRGDIV_RESET_DONE_LSB);
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def_gt_ch_masked_reg_read16(gthe3, tx_usrclk_act, GTHE3_CH_TX_USRCLK_ACT_ADDR, GTHE3_CH_TX_USRCLK_ACT_MASK, GTHE3_CH_TX_USRCLK_ACT_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_pd, GTHE3_CH_TX_PD_ADDR, GTHE3_CH_TX_PD_MASK, GTHE3_CH_TX_PD_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_qpll_sel, GTHE3_CH_TX_QPLL_SEL_ADDR, GTHE3_CH_TX_QPLL_SEL_MASK, GTHE3_CH_TX_QPLL_SEL_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_polarity, GTHE3_CH_TX_POLARITY_ADDR, GTHE3_CH_TX_POLARITY_MASK, GTHE3_CH_TX_POLARITY_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_elecidle, GTHE3_CH_TX_ELECIDLE_ADDR, GTHE3_CH_TX_ELECIDLE_MASK, GTHE3_CH_TX_ELECIDLE_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_inhibit, GTHE3_CH_TX_INHIBIT_ADDR, GTHE3_CH_TX_INHIBIT_MASK, GTHE3_CH_TX_INHIBIT_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_diffctrl, GTHE3_CH_TX_DIFFCTRL_ADDR, GTHE3_CH_TX_DIFFCTRL_MASK, GTHE3_CH_TX_DIFFCTRL_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_maincursor, GTHE3_CH_TX_MAINCURSOR_ADDR, GTHE3_CH_TX_MAINCURSOR_MASK, GTHE3_CH_TX_MAINCURSOR_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_precursor, GTHE3_CH_TX_PRECURSOR_ADDR, GTHE3_CH_TX_PRECURSOR_MASK, GTHE3_CH_TX_PRECURSOR_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_postcursor, GTHE3_CH_TX_POSTCURSOR_ADDR, GTHE3_CH_TX_POSTCURSOR_MASK, GTHE3_CH_TX_POSTCURSOR_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_prbs_sel, GTHE3_CH_TX_PRBS_SEL_ADDR, GTHE3_CH_TX_PRBS_SEL_MASK, GTHE3_CH_TX_PRBS_SEL_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, tx_prbs_forcerr, GTHE3_CH_TX_PRBS_FORCERR_ADDR, GTHE3_CH_TX_PRBS_FORCERR_MASK, GTHE3_CH_TX_PRBS_FORCERR_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_reset, GTHE3_CH_RX_RESET_ADDR, GTHE3_CH_RX_RESET_MASK, GTHE3_CH_RX_RESET_LSB);
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int gthe3_ch_rx_reset(struct gt_ch *ch);
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def_gt_ch_masked_reg_rw16(gthe3, rx_pma_reset, GTHE3_CH_RX_PMA_RESET_ADDR, GTHE3_CH_RX_PMA_RESET_MASK, GTHE3_CH_RX_PMA_RESET_LSB);
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int gthe3_ch_rx_pma_reset(struct gt_ch *ch);
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def_gt_ch_masked_reg_rw16(gthe3, rx_pcs_reset, GTHE3_CH_RX_PCS_RESET_ADDR, GTHE3_CH_RX_PCS_RESET_MASK, GTHE3_CH_RX_PCS_RESET_LSB);
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int gthe3_ch_rx_pcs_reset(struct gt_ch *ch);
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def_gt_ch_masked_reg_rw16(gthe3, rx_dfe_lpm_reset, GTHE3_CH_RX_DFE_LPM_RESET_ADDR, GTHE3_CH_RX_DFE_LPM_RESET_MASK, GTHE3_CH_RX_DFE_LPM_RESET_LSB);
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int gthe3_ch_rx_dfe_lpm_reset(struct gt_ch *ch);
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def_gt_ch_masked_reg_rw16(gthe3, eyescan_reset, GTHE3_CH_EYESCAN_RESET_ADDR, GTHE3_CH_EYESCAN_RESET_MASK, GTHE3_CH_EYESCAN_RESET_LSB);
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int gthe3_ch_eyescan_reset(struct gt_ch *ch);
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def_gt_ch_masked_reg_read16(gthe3, rx_reset_done, GTHE3_CH_RX_RESET_DONE_ADDR, GTHE3_CH_RX_RESET_DONE_MASK, GTHE3_CH_RX_RESET_DONE_LSB);
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def_gt_ch_masked_reg_read16(gthe3, rx_gt_reset_done, GTHE3_CH_RX_GT_RESET_DONE_ADDR, GTHE3_CH_RX_GT_RESET_DONE_MASK, GTHE3_CH_RX_GT_RESET_DONE_LSB);
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def_gt_ch_masked_reg_read16(gthe3, rx_pma_reset_done, GTHE3_CH_RX_PMA_RESET_DONE_ADDR, GTHE3_CH_RX_PMA_RESET_DONE_MASK, GTHE3_CH_RX_PMA_RESET_DONE_LSB);
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def_gt_ch_masked_reg_read16(gthe3, rx_prgdiv_reset_done, GTHE3_CH_RX_PRGDIV_RESET_DONE_ADDR, GTHE3_CH_RX_PRGDIV_RESET_DONE_MASK, GTHE3_CH_RX_PRGDIV_RESET_DONE_LSB);
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def_gt_ch_masked_reg_read16(gthe3, rx_usrclk_act, GTHE3_CH_RX_USRCLK_ACT_ADDR, GTHE3_CH_RX_USRCLK_ACT_MASK, GTHE3_CH_RX_USRCLK_ACT_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_pd, GTHE3_CH_RX_PD_ADDR, GTHE3_CH_RX_PD_MASK, GTHE3_CH_RX_PD_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_qpll_sel, GTHE3_CH_RX_QPLL_SEL_ADDR, GTHE3_CH_RX_QPLL_SEL_MASK, GTHE3_CH_RX_QPLL_SEL_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, loopback, GTHE3_CH_LOOPBACK_ADDR, GTHE3_CH_LOOPBACK_MASK, GTHE3_CH_LOOPBACK_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_polarity, GTHE3_CH_RX_POLARITY_ADDR, GTHE3_CH_RX_POLARITY_MASK, GTHE3_CH_RX_POLARITY_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_cdr_hold, GTHE3_CH_RX_CDR_HOLD_ADDR, GTHE3_CH_RX_CDR_HOLD_MASK, GTHE3_CH_RX_CDR_HOLD_LSB);
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def_gt_ch_masked_reg_read16(gthe3, rx_cdr_lock, GTHE3_CH_RX_CDR_LOCK_ADDR, GTHE3_CH_RX_CDR_LOCK_MASK, GTHE3_CH_RX_CDR_LOCK_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_lpm_en, GTHE3_CH_RX_LPM_EN_ADDR, GTHE3_CH_RX_LPM_EN_MASK, GTHE3_CH_RX_LPM_EN_LSB);
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def_gt_ch_masked_reg_read16(gthe3, rx_dmonitor, GTHE3_CH_RX_DMONITOR_ADDR, GTHE3_CH_RX_DMONITOR_MASK, GTHE3_CH_RX_DMONITOR_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_prbs_sel, GTHE3_CH_RX_PRBS_SEL_ADDR, GTHE3_CH_RX_PRBS_SEL_MASK, GTHE3_CH_RX_PRBS_SEL_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_prbs_cnt_reset, GTHE3_CH_RX_PRBS_CNT_RESET_ADDR, GTHE3_CH_RX_PRBS_CNT_RESET_MASK, GTHE3_CH_RX_PRBS_CNT_RESET_LSB);
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def_gt_ch_masked_reg_read16(gthe3, rx_prbs_locked, GTHE3_CH_RX_PRBS_LOCKED_ADDR, GTHE3_CH_RX_PRBS_LOCKED_MASK, GTHE3_CH_RX_PRBS_LOCKED_LSB);
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def_gt_ch_masked_reg_read16(gthe3, rx_prbs_error, GTHE3_CH_RX_PRBS_ERROR_ADDR, GTHE3_CH_RX_PRBS_ERROR_MASK, GTHE3_CH_RX_PRBS_ERROR_LSB);
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// common
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_cfg0, GTHE3_COM_QPLL0_CFG0_ADDR, GTHE3_COM_QPLL0_CFG0_MASK, GTHE3_COM_QPLL0_CFG0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, common_cfg0, GTHE3_COM_COMMON_CFG0_ADDR, GTHE3_COM_COMMON_CFG0_MASK, GTHE3_COM_COMMON_CFG0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, rsvd_attr0, GTHE3_COM_RSVD_ATTR0_ADDR, GTHE3_COM_RSVD_ATTR0_MASK, GTHE3_COM_RSVD_ATTR0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_cfg1, GTHE3_COM_QPLL0_CFG1_ADDR, GTHE3_COM_QPLL0_CFG1_MASK, GTHE3_COM_QPLL0_CFG1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_cfg2, GTHE3_COM_QPLL0_CFG2_ADDR, GTHE3_COM_QPLL0_CFG2_MASK, GTHE3_COM_QPLL0_CFG2_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_lock_cfg, GTHE3_COM_QPLL0_LOCK_CFG_ADDR, GTHE3_COM_QPLL0_LOCK_CFG_MASK, GTHE3_COM_QPLL0_LOCK_CFG_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_init_cfg0, GTHE3_COM_QPLL0_INIT_CFG0_ADDR, GTHE3_COM_QPLL0_INIT_CFG0_MASK, GTHE3_COM_QPLL0_INIT_CFG0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_init_cfg1, GTHE3_COM_QPLL0_INIT_CFG1_ADDR, GTHE3_COM_QPLL0_INIT_CFG1_MASK, GTHE3_COM_QPLL0_INIT_CFG1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_fbdiv, GTHE3_COM_QPLL0_FBDIV_ADDR, GTHE3_COM_QPLL0_FBDIV_MASK, GTHE3_COM_QPLL0_FBDIV_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_cfg3, GTHE3_COM_QPLL0_CFG3_ADDR, GTHE3_COM_QPLL0_CFG3_MASK, GTHE3_COM_QPLL0_CFG3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_cp, GTHE3_COM_QPLL0_CP_ADDR, GTHE3_COM_QPLL0_CP_MASK, GTHE3_COM_QPLL0_CP_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_refclk_div, GTHE3_COM_QPLL0_REFCLK_DIV_ADDR, GTHE3_COM_QPLL0_REFCLK_DIV_MASK, GTHE3_COM_QPLL0_REFCLK_DIV_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_lpf, GTHE3_COM_QPLL0_LPF_ADDR, GTHE3_COM_QPLL0_LPF_MASK, GTHE3_COM_QPLL0_LPF_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_cfg1_g3, GTHE3_COM_QPLL0_CFG1_G3_ADDR, GTHE3_COM_QPLL0_CFG1_G3_MASK, GTHE3_COM_QPLL0_CFG1_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_cfg2_g3, GTHE3_COM_QPLL0_CFG2_G3_ADDR, GTHE3_COM_QPLL0_CFG2_G3_MASK, GTHE3_COM_QPLL0_CFG2_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_lpf_g3, GTHE3_COM_QPLL0_LPF_G3_ADDR, GTHE3_COM_QPLL0_LPF_G3_MASK, GTHE3_COM_QPLL0_LPF_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_lock_cfg_g3, GTHE3_COM_QPLL0_LOCK_CFG_G3_ADDR, GTHE3_COM_QPLL0_LOCK_CFG_G3_MASK, GTHE3_COM_QPLL0_LOCK_CFG_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, rsvd_attr1, GTHE3_COM_RSVD_ATTR1_ADDR, GTHE3_COM_RSVD_ATTR1_MASK, GTHE3_COM_RSVD_ATTR1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_fbdiv_g3, GTHE3_COM_QPLL0_FBDIV_G3_ADDR, GTHE3_COM_QPLL0_FBDIV_G3_MASK, GTHE3_COM_QPLL0_FBDIV_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, rxrecclkout0_sel, GTHE3_COM_RXRECCLKOUT0_SEL_ADDR, GTHE3_COM_RXRECCLKOUT0_SEL_MASK, GTHE3_COM_RXRECCLKOUT0_SEL_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_sdm_cfg0, GTHE3_COM_QPLL0_SDM_CFG0_ADDR, GTHE3_COM_QPLL0_SDM_CFG0_MASK, GTHE3_COM_QPLL0_SDM_CFG0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_sdm_cfg1, GTHE3_COM_QPLL0_SDM_CFG1_ADDR, GTHE3_COM_QPLL0_SDM_CFG1_MASK, GTHE3_COM_QPLL0_SDM_CFG1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm0initseed0_0, GTHE3_COM_SDM0INITSEED0_0_ADDR, GTHE3_COM_SDM0INITSEED0_0_MASK, GTHE3_COM_SDM0INITSEED0_0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm0initseed0_1, GTHE3_COM_SDM0INITSEED0_1_ADDR, GTHE3_COM_SDM0INITSEED0_1_MASK, GTHE3_COM_SDM0INITSEED0_1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_sdm_cfg2, GTHE3_COM_QPLL0_SDM_CFG2_ADDR, GTHE3_COM_QPLL0_SDM_CFG2_MASK, GTHE3_COM_QPLL0_SDM_CFG2_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_cp_g3, GTHE3_COM_QPLL0_CP_G3_ADDR, GTHE3_COM_QPLL0_CP_G3_MASK, GTHE3_COM_QPLL0_CP_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm0data1_0, GTHE3_COM_SDM0DATA1_0_ADDR, GTHE3_COM_SDM0DATA1_0_MASK, GTHE3_COM_SDM0DATA1_0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm0_width_pin_sel, GTHE3_COM_SDM0_WIDTH_PIN_SEL_ADDR, GTHE3_COM_SDM0_WIDTH_PIN_SEL_MASK, GTHE3_COM_SDM0_WIDTH_PIN_SEL_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm0_data_pin_sel, GTHE3_COM_SDM0_DATA_PIN_SEL_ADDR, GTHE3_COM_SDM0_DATA_PIN_SEL_MASK, GTHE3_COM_SDM0_DATA_PIN_SEL_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm0data1_1, GTHE3_COM_SDM0DATA1_1_ADDR, GTHE3_COM_SDM0DATA1_1_MASK, GTHE3_COM_SDM0DATA1_1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll0_cfg4, GTHE3_COM_QPLL0_CFG4_ADDR, GTHE3_COM_QPLL0_CFG4_MASK, GTHE3_COM_QPLL0_CFG4_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, bias_cfg0, GTHE3_COM_BIAS_CFG0_ADDR, GTHE3_COM_BIAS_CFG0_MASK, GTHE3_COM_BIAS_CFG0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, bias_cfg1, GTHE3_COM_BIAS_CFG1_ADDR, GTHE3_COM_BIAS_CFG1_MASK, GTHE3_COM_BIAS_CFG1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, bias_cfg2, GTHE3_COM_BIAS_CFG2_ADDR, GTHE3_COM_BIAS_CFG2_MASK, GTHE3_COM_BIAS_CFG2_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, bias_cfg3, GTHE3_COM_BIAS_CFG3_ADDR, GTHE3_COM_BIAS_CFG3_MASK, GTHE3_COM_BIAS_CFG3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, bias_cfg_rsvd, GTHE3_COM_BIAS_CFG_RSVD_ADDR, GTHE3_COM_BIAS_CFG_RSVD_MASK, GTHE3_COM_BIAS_CFG_RSVD_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, bias_cfg4, GTHE3_COM_BIAS_CFG4_ADDR, GTHE3_COM_BIAS_CFG4_MASK, GTHE3_COM_BIAS_CFG4_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_cfg0, GTHE3_COM_QPLL1_CFG0_ADDR, GTHE3_COM_QPLL1_CFG0_MASK, GTHE3_COM_QPLL1_CFG0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, common_cfg1, GTHE3_COM_COMMON_CFG1_ADDR, GTHE3_COM_COMMON_CFG1_MASK, GTHE3_COM_COMMON_CFG1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, por_cfg, GTHE3_COM_POR_CFG_ADDR, GTHE3_COM_POR_CFG_MASK, GTHE3_COM_POR_CFG_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_cfg1, GTHE3_COM_QPLL1_CFG1_ADDR, GTHE3_COM_QPLL1_CFG1_MASK, GTHE3_COM_QPLL1_CFG1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_cfg2, GTHE3_COM_QPLL1_CFG2_ADDR, GTHE3_COM_QPLL1_CFG2_MASK, GTHE3_COM_QPLL1_CFG2_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_lock_cfg, GTHE3_COM_QPLL1_LOCK_CFG_ADDR, GTHE3_COM_QPLL1_LOCK_CFG_MASK, GTHE3_COM_QPLL1_LOCK_CFG_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_init_cfg0, GTHE3_COM_QPLL1_INIT_CFG0_ADDR, GTHE3_COM_QPLL1_INIT_CFG0_MASK, GTHE3_COM_QPLL1_INIT_CFG0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_init_cfg1, GTHE3_COM_QPLL1_INIT_CFG1_ADDR, GTHE3_COM_QPLL1_INIT_CFG1_MASK, GTHE3_COM_QPLL1_INIT_CFG1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_fbdiv, GTHE3_COM_QPLL1_FBDIV_ADDR, GTHE3_COM_QPLL1_FBDIV_MASK, GTHE3_COM_QPLL1_FBDIV_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_cfg3, GTHE3_COM_QPLL1_CFG3_ADDR, GTHE3_COM_QPLL1_CFG3_MASK, GTHE3_COM_QPLL1_CFG3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_cp, GTHE3_COM_QPLL1_CP_ADDR, GTHE3_COM_QPLL1_CP_MASK, GTHE3_COM_QPLL1_CP_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sarc_sel, GTHE3_COM_SARC_SEL_ADDR, GTHE3_COM_SARC_SEL_MASK, GTHE3_COM_SARC_SEL_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sarc_en, GTHE3_COM_SARC_EN_ADDR, GTHE3_COM_SARC_EN_MASK, GTHE3_COM_SARC_EN_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_refclk_div, GTHE3_COM_QPLL1_REFCLK_DIV_ADDR, GTHE3_COM_QPLL1_REFCLK_DIV_MASK, GTHE3_COM_QPLL1_REFCLK_DIV_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_lpf, GTHE3_COM_QPLL1_LPF_ADDR, GTHE3_COM_QPLL1_LPF_MASK, GTHE3_COM_QPLL1_LPF_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_cfg1_g3, GTHE3_COM_QPLL1_CFG1_G3_ADDR, GTHE3_COM_QPLL1_CFG1_G3_MASK, GTHE3_COM_QPLL1_CFG1_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_cfg2_g3, GTHE3_COM_QPLL1_CFG2_G3_ADDR, GTHE3_COM_QPLL1_CFG2_G3_MASK, GTHE3_COM_QPLL1_CFG2_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_lpf_g3, GTHE3_COM_QPLL1_LPF_G3_ADDR, GTHE3_COM_QPLL1_LPF_G3_MASK, GTHE3_COM_QPLL1_LPF_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_lock_cfg_g3, GTHE3_COM_QPLL1_LOCK_CFG_G3_ADDR, GTHE3_COM_QPLL1_LOCK_CFG_G3_MASK, GTHE3_COM_QPLL1_LOCK_CFG_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, rsvd_attr2, GTHE3_COM_RSVD_ATTR2_ADDR, GTHE3_COM_RSVD_ATTR2_MASK, GTHE3_COM_RSVD_ATTR2_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_fbdiv_g3, GTHE3_COM_QPLL1_FBDIV_G3_ADDR, GTHE3_COM_QPLL1_FBDIV_G3_MASK, GTHE3_COM_QPLL1_FBDIV_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, rxrecclkout1_sel, GTHE3_COM_RXRECCLKOUT1_SEL_ADDR, GTHE3_COM_RXRECCLKOUT1_SEL_MASK, GTHE3_COM_RXRECCLKOUT1_SEL_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_sdm_cfg0, GTHE3_COM_QPLL1_SDM_CFG0_ADDR, GTHE3_COM_QPLL1_SDM_CFG0_MASK, GTHE3_COM_QPLL1_SDM_CFG0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_sdm_cfg1, GTHE3_COM_QPLL1_SDM_CFG1_ADDR, GTHE3_COM_QPLL1_SDM_CFG1_MASK, GTHE3_COM_QPLL1_SDM_CFG1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm1initseed0_0, GTHE3_COM_SDM1INITSEED0_0_ADDR, GTHE3_COM_SDM1INITSEED0_0_MASK, GTHE3_COM_SDM1INITSEED0_0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm1initseed0_1, GTHE3_COM_SDM1INITSEED0_1_ADDR, GTHE3_COM_SDM1INITSEED0_1_MASK, GTHE3_COM_SDM1INITSEED0_1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_sdm_cfg2, GTHE3_COM_QPLL1_SDM_CFG2_ADDR, GTHE3_COM_QPLL1_SDM_CFG2_MASK, GTHE3_COM_QPLL1_SDM_CFG2_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_cp_g3, GTHE3_COM_QPLL1_CP_G3_ADDR, GTHE3_COM_QPLL1_CP_G3_MASK, GTHE3_COM_QPLL1_CP_G3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm1data1_0, GTHE3_COM_SDM1DATA1_0_ADDR, GTHE3_COM_SDM1DATA1_0_MASK, GTHE3_COM_SDM1DATA1_0_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm1_width_pin_sel, GTHE3_COM_SDM1_WIDTH_PIN_SEL_ADDR, GTHE3_COM_SDM1_WIDTH_PIN_SEL_MASK, GTHE3_COM_SDM1_WIDTH_PIN_SEL_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm1_data_pin_sel, GTHE3_COM_SDM1_DATA_PIN_SEL_ADDR, GTHE3_COM_SDM1_DATA_PIN_SEL_MASK, GTHE3_COM_SDM1_DATA_PIN_SEL_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, sdm1data1_1, GTHE3_COM_SDM1DATA1_1_ADDR, GTHE3_COM_SDM1DATA1_1_MASK, GTHE3_COM_SDM1DATA1_1_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, rsvd_attr3, GTHE3_COM_RSVD_ATTR3_ADDR, GTHE3_COM_RSVD_ATTR3_MASK, GTHE3_COM_RSVD_ATTR3_LSB);
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def_gt_pll_masked_reg_rw16(gthe3, qpll1_cfg4, GTHE3_COM_QPLL1_CFG4_ADDR, GTHE3_COM_QPLL1_CFG4_MASK, GTHE3_COM_QPLL1_CFG4_LSB);
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// RX
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def_gt_ch_masked_reg_rw16(gthe3, rx_data_width_raw, GTHE3_CH_RX_DATA_WIDTH_ADDR, GTHE3_CH_RX_DATA_WIDTH_MASK, GTHE3_CH_RX_DATA_WIDTH_LSB);
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int gthe3_ch_get_rx_data_width(struct gt_ch *ch, uint32_t *val);
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def_gt_ch_masked_reg_rw16(gthe3, rx_int_data_width_raw, GTHE3_CH_RX_INT_DATAWIDTH_ADDR, GTHE3_CH_RX_INT_DATAWIDTH_MASK, GTHE3_CH_RX_INT_DATAWIDTH_LSB);
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int gthe3_ch_get_rx_int_data_width(struct gt_ch *ch, uint32_t *val);
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def_gt_ch_masked_reg_rw16(gthe3, es_prescale, GTHE3_CH_ES_PRESCALE_ADDR, GTHE3_CH_ES_PRESCALE_MASK, GTHE3_CH_ES_PRESCALE_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, es_eye_scan_en, GTHE3_CH_ES_EYE_SCAN_EN_ADDR, GTHE3_CH_ES_EYE_SCAN_EN_MASK, GTHE3_CH_ES_EYE_SCAN_EN_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, es_errdet_en, GTHE3_CH_ES_ERRDET_EN_ADDR, GTHE3_CH_ES_ERRDET_EN_MASK, GTHE3_CH_ES_ERRDET_EN_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, es_control, GTHE3_CH_ES_CONTROL_ADDR, GTHE3_CH_ES_CONTROL_MASK, GTHE3_CH_ES_CONTROL_LSB);
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int gthe3_ch_set_es_qual_mask(struct gt_ch *ch, uint8_t *mask);
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int gthe3_ch_set_es_qual_mask_clear(struct gt_ch *ch);
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int gthe3_ch_set_es_sdata_mask(struct gt_ch *ch, uint8_t *mask);
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int gthe3_ch_set_es_sdata_mask_width(struct gt_ch *ch, int width);
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def_gt_ch_masked_reg_rw16(gthe3, es_horz_offset, GTHE3_CH_ES_HORZ_OFFSET_ADDR, GTHE3_CH_ES_HORZ_OFFSET_MASK, GTHE3_CH_ES_HORZ_OFFSET_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_eyescan_vs_range, GTHE3_CH_RX_EYESCAN_VS_RANGE_ADDR, GTHE3_CH_RX_EYESCAN_VS_RANGE_MASK, GTHE3_CH_RX_EYESCAN_VS_RANGE_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_eyescan_vs_code, GTHE3_CH_RX_EYESCAN_VS_CODE_ADDR, GTHE3_CH_RX_EYESCAN_VS_CODE_MASK, GTHE3_CH_RX_EYESCAN_VS_CODE_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_eyescan_vs_ut_sign, GTHE3_CH_RX_EYESCAN_VS_UT_SIGN_ADDR, GTHE3_CH_RX_EYESCAN_VS_UT_SIGN_MASK, GTHE3_CH_RX_EYESCAN_VS_UT_SIGN_LSB);
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def_gt_ch_masked_reg_rw16(gthe3, rx_eyescan_vs_neg_dir, GTHE3_CH_RX_EYESCAN_VS_NEG_DIR_ADDR, GTHE3_CH_RX_EYESCAN_VS_NEG_DIR_MASK, GTHE3_CH_RX_EYESCAN_VS_NEG_DIR_LSB);
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def_gt_ch_masked_reg_read16(gthe3, es_error_count, GTHE3_CH_ES_ERROR_COUNT_ADDR, GTHE3_CH_ES_ERROR_COUNT_MASK, GTHE3_CH_ES_ERROR_COUNT_LSB);
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def_gt_ch_masked_reg_read16(gthe3, es_sample_count, GTHE3_CH_ES_SAMPLE_COUNT_ADDR, GTHE3_CH_ES_SAMPLE_COUNT_MASK, GTHE3_CH_ES_SAMPLE_COUNT_LSB);
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def_gt_ch_masked_reg_read16(gthe3, es_control_status, GTHE3_CH_ES_CONTROL_STATUS_ADDR, GTHE3_CH_ES_CONTROL_STATUS_MASK, GTHE3_CH_ES_CONTROL_STATUS_LSB);
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int gthe3_ch_get_rx_prbs_error_count(struct gt_ch *ch, uint32_t *val);
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// TX
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def_gt_ch_masked_reg_rw16(gthe3, tx_data_width_raw, GTHE3_CH_TX_DATA_WIDTH_ADDR, GTHE3_CH_TX_DATA_WIDTH_MASK, GTHE3_CH_TX_DATA_WIDTH_LSB);
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int gthe3_ch_get_tx_data_width(struct gt_ch *ch, uint32_t *val);
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def_gt_ch_masked_reg_rw16(gthe3, tx_int_data_width_raw, GTHE3_CH_TX_INT_DATAWIDTH_ADDR, GTHE3_CH_TX_INT_DATAWIDTH_MASK, GTHE3_CH_TX_INT_DATAWIDTH_LSB);
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int gthe3_ch_get_tx_int_data_width(struct gt_ch *ch, uint32_t *val);
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extern const struct gt_quad_ops gthe3_gt_quad_ops;
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#endif /* XCVR_GTHE3_H */
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