2018-06-13 19:30:07 -07:00
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# FPGA settings
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FPGA_PART = xcvu9p-flga2104-2L-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_reset.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/mdio_master.v
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SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_1g.v
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SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
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SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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2018-10-24 01:03:44 -07:00
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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2018-06-13 19:30:07 -07:00
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
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SYN_FILES += lib/eth/rtl/udp_complete_64.v
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SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
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SYN_FILES += lib/eth/rtl/udp_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_complete_64.v
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SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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2018-11-08 09:17:29 -08:00
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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2018-06-13 19:30:07 -07:00
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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2018-11-08 09:17:29 -08:00
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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2018-06-13 19:30:07 -07:00
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_adapter.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
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2018-10-30 21:32:32 -07:00
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SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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2018-06-13 19:30:07 -07:00
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += clock.xdc
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# IP
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XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci
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XCI_FILES += ip/ten_gig_eth_pcs_pma_0.xci
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [lindex [get_hw_devices] 0]" >> program.tcl
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echo "program_hw_devices [lindex [get_hw_devices] 0]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -mode batch -source program.tcl
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