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27 lines
714 B
Markdown
27 lines
714 B
Markdown
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# Verilog Ethernet Nexys Video Example Design
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## Introduction
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This example design targets the Digilent Nexys Video FPGA board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests.
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FPGA: XC7A200TSBG484-1
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PHY: Realtek RTL8211E
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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## How to test
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Run make program to program the Nexys Video board with the Digilent command
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line tools. Then run netcat -u 192.168.1.128 1234 to open a UDP connection to
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port 1234. Any text entered into netcat will be echoed back after pressing
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enter.
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