2014-11-08 21:07:47 -08:00
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/*
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2018-02-26 12:25:20 -08:00
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Copyright (c) 2014-2018 Alex Forencich
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2014-11-08 21:07:47 -08:00
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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2016-09-12 13:38:34 -07:00
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`timescale 1ns / 1ps
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2014-11-08 21:07:47 -08:00
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2016-09-12 13:38:34 -07:00
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/*
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2017-11-20 20:11:44 -08:00
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* Testbench for axis_frame_fifo
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2016-09-12 13:38:34 -07:00
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*/
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2014-11-08 21:07:47 -08:00
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module test_axis_frame_fifo_64;
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2016-09-12 13:38:34 -07:00
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// Parameters
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parameter ADDR_WIDTH = 6;
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parameter DATA_WIDTH = 64;
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parameter KEEP_ENABLE = (DATA_WIDTH>8);
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parameter KEEP_WIDTH = (DATA_WIDTH/8);
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parameter ID_ENABLE = 1;
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parameter ID_WIDTH = 8;
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parameter DEST_ENABLE = 1;
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parameter DEST_WIDTH = 8;
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parameter USER_ENABLE = 1;
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parameter USER_WIDTH = 1;
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parameter USER_BAD_FRAME_VALUE = 1'b1;
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parameter USER_BAD_FRAME_MASK = 1'b1;
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parameter DROP_BAD_FRAME = 1;
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parameter DROP_WHEN_FULL = 0;
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2014-11-08 21:07:47 -08:00
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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2016-09-12 13:38:34 -07:00
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reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
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reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
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reg input_axis_tvalid = 0;
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reg input_axis_tlast = 0;
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reg [ID_WIDTH-1:0] input_axis_tid = 0;
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reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
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reg [USER_WIDTH-1:0] input_axis_tuser = 0;
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2014-11-08 21:07:47 -08:00
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reg output_axis_tready = 0;
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// Outputs
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wire input_axis_tready;
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wire [DATA_WIDTH-1:0] output_axis_tdata;
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wire [KEEP_WIDTH-1:0] output_axis_tkeep;
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wire output_axis_tvalid;
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wire output_axis_tlast;
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2017-11-20 20:11:44 -08:00
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wire [ID_WIDTH-1:0] output_axis_tid;
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wire [DEST_WIDTH-1:0] output_axis_tdest;
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wire [USER_WIDTH-1:0] output_axis_tuser;
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2015-05-12 17:52:41 -07:00
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wire overflow;
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wire bad_frame;
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wire good_frame;
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2014-11-08 21:07:47 -08:00
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initial begin
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// myhdl integration
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2016-09-12 13:38:34 -07:00
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$from_myhdl(
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clk,
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rst,
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current_test,
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input_axis_tdata,
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input_axis_tkeep,
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input_axis_tvalid,
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input_axis_tlast,
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input_axis_tid,
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input_axis_tdest,
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input_axis_tuser,
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output_axis_tready
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);
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$to_myhdl(
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input_axis_tready,
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output_axis_tdata,
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output_axis_tkeep,
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output_axis_tvalid,
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output_axis_tlast,
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output_axis_tid,
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output_axis_tdest,
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output_axis_tuser,
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overflow,
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bad_frame,
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good_frame
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);
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2014-11-08 21:07:47 -08:00
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// dump file
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$dumpfile("test_axis_frame_fifo_64.lxt");
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$dumpvars(0, test_axis_frame_fifo_64);
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end
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2017-11-20 20:11:44 -08:00
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axis_frame_fifo #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_ENABLE(KEEP_ENABLE),
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.KEEP_WIDTH(KEEP_WIDTH),
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.ID_ENABLE(ID_ENABLE),
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.ID_WIDTH(ID_WIDTH),
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.DEST_ENABLE(DEST_ENABLE),
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.DEST_WIDTH(DEST_WIDTH),
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.USER_ENABLE(USER_ENABLE),
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.USER_WIDTH(USER_WIDTH),
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.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
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.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
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.DROP_BAD_FRAME(DROP_BAD_FRAME),
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.DROP_WHEN_FULL(DROP_WHEN_FULL)
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2014-11-08 21:07:47 -08:00
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)
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UUT (
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.clk(clk),
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.rst(rst),
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// AXI input
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.input_axis_tdata(input_axis_tdata),
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.input_axis_tkeep(input_axis_tkeep),
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.input_axis_tvalid(input_axis_tvalid),
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.input_axis_tready(input_axis_tready),
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.input_axis_tlast(input_axis_tlast),
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.input_axis_tid(input_axis_tid),
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.input_axis_tdest(input_axis_tdest),
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2014-11-08 21:07:47 -08:00
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.input_axis_tuser(input_axis_tuser),
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// AXI output
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.output_axis_tdata(output_axis_tdata),
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.output_axis_tkeep(output_axis_tkeep),
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.output_axis_tvalid(output_axis_tvalid),
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.output_axis_tready(output_axis_tready),
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2015-05-12 17:52:41 -07:00
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.output_axis_tlast(output_axis_tlast),
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.output_axis_tid(output_axis_tid),
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.output_axis_tdest(output_axis_tdest),
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.output_axis_tuser(output_axis_tuser),
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// Status
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.overflow(overflow),
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.bad_frame(bad_frame),
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.good_frame(good_frame)
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2014-11-08 21:07:47 -08:00
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);
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endmodule
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