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27 lines
714 B
Markdown
27 lines
714 B
Markdown
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# Verilog PCIe Alveo U200 Example Design
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## Introduction
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This example design targets the Xilinx Alveo U200 FPGA board.
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The design implements the PCIe AXI lite master module, the PCIe AXI master
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module, and the PCIe AXI DMA module. A very simple Linux driver is included
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to test the FPGA design.
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FPGA: xcu200-fsgd2104-2-e
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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Run make to build the driver. Ensure the headers for the running kernel are
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installed, otherwise the driver cannot be compiled.
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## How to test
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Run make program to program the Alveo U200 board with Vivado. Then load the
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driver with insmod example.ko. Check dmesg for the output.
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