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corundum/tb/test_axis_async_frame_fifo.py

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#!/usr/bin/env python
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"""
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
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import axis_ep
module = 'axis_async_frame_fifo'
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testbench = 'test_%s' % module
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srcs = []
srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
ADDR_WIDTH = 9
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
DROP_BAD_FRAME = 1
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DROP_WHEN_FULL = 0
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# Inputs
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async_rst = Signal(bool(0))
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input_clk = Signal(bool(0))
output_clk = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
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input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
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input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
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output_axis_tready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
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output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
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output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_status_overflow = Signal(bool(0))
input_status_bad_frame = Signal(bool(0))
input_status_good_frame = Signal(bool(0))
output_status_overflow = Signal(bool(0))
output_status_bad_frame = Signal(bool(0))
output_status_good_frame = Signal(bool(0))
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# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(
input_clk,
async_rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
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tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
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tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
output_clk,
async_rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
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tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
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pause=sink_pause,
name='sink'
)
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# DUT
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if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
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input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
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input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
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output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
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input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame,
input_status_good_frame=input_status_good_frame,
output_status_overflow=output_status_overflow,
output_status_bad_frame=output_status_bad_frame,
output_status_good_frame=output_status_good_frame
)
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@always(delay(4))
def input_clkgen():
input_clk.next = not input_clk
@always(delay(5))
def output_clkgen():
output_clk.next = not output_clk
input_status_overflow_asserted = Signal(bool(0))
input_status_bad_frame_asserted = Signal(bool(0))
input_status_good_frame_asserted = Signal(bool(0))
output_status_overflow_asserted = Signal(bool(0))
output_status_bad_frame_asserted = Signal(bool(0))
output_status_good_frame_asserted = Signal(bool(0))
@always(input_clk.posedge)
def monitor_1():
if (input_status_overflow):
input_status_overflow_asserted.next = 1
if (input_status_bad_frame):
input_status_bad_frame_asserted.next = 1
if (input_status_good_frame):
input_status_good_frame_asserted.next = 1
@always(output_clk.posedge)
def monitor_2():
if (output_status_overflow):
output_status_overflow_asserted.next = 1
if (output_status_bad_frame):
output_status_bad_frame_asserted.next = 1
if (output_status_good_frame):
output_status_good_frame_asserted.next = 1
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@instance
def check():
yield delay(100)
yield input_clk.posedge
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async_rst.next = 1
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yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
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async_rst.next = 0
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yield input_clk.posedge
yield delay(100)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
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source.send(test_frame)
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yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
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yield delay(100)
yield input_clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
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source.send(test_frame)
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yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
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yield input_clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1
)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
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source.send(test_frame)
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yield input_clk.posedge
yield delay(64)
yield input_clk.posedge
source_pause.next = True
yield delay(32)
yield input_clk.posedge
source_pause.next = False
yield delay(64)
yield output_clk.posedge
sink_pause.next = True
yield delay(32)
yield output_clk.posedge
sink_pause.next = False
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
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yield delay(100)
yield input_clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
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source.send(test_frame1)
source.send(test_frame2)
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yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame1
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rx_frame = sink.recv()
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assert rx_frame == test_frame2
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
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yield delay(100)
yield input_clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
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source.send(test_frame1)
source.send(test_frame2)
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yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
source_pause.next = False
yield input_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
if output_axis_tvalid:
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame1
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rx_frame = sink.recv()
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assert rx_frame == test_frame2
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
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yield delay(100)
yield input_clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=6
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
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source.send(test_frame1)
source.send(test_frame2)
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yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
sink_pause.next = False
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame1
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rx_frame = sink.recv()
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assert rx_frame == test_frame2
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
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yield delay(100)
yield input_clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
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source.send(test_frame)
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yield input_clk.posedge
yield delay(1000)
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assert sink.empty()
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assert not input_status_overflow_asserted
assert input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
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yield delay(100)
yield input_clk.posedge
print("test 8: single packet overflow")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256))*2,
id=8,
dest=1
)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
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source.send(test_frame)
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yield input_clk.posedge
yield delay(10000)
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assert sink.empty()
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assert input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
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yield delay(100)
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yield input_clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=9,
dest=1
)
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sink_pause.next = 1
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source.send(test_frame)
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yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame
yield delay(100)
yield input_clk.posedge
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print("test 10: initial sink pause, assert reset")
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current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=10,
dest=1
)
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sink_pause.next = 1
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source.send(test_frame)
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yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
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async_rst.next = 1
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yield input_clk.posedge
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async_rst.next = 0
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sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
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assert sink.empty()
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yield delay(100)
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raise StopSimulation
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return dut, monitor_1, monitor_2, source_logic, sink_logic, input_clkgen, output_clkgen, check
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def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()