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28 lines
1003 B
Markdown
28 lines
1003 B
Markdown
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# Verilog Ethernet HXT100G Crosspoint Switch Design
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## Introduction
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This design targets the HiTech Global HXT100G FPGA board.
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The design forms a 16x16 crosspoint switch for 10G Ethernet. It is capable of
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connecting any output port to any input port based on configuration frames
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received over a dedicated configuration interface.
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FPGA: XC6VHX565T-2FFG1923
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PHY: 10G BASE-R PHY IP core and internal GTH transceiver
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## How to build
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Run make to build. Ensure that the Xilinx ISE toolchain components are
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in PATH.
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## How to use
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SFP left ports 0-7 are connected to crosspoint input/output ports 0-7, SFP
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right ports 0-7 are connected to crosspoint input/output ports 8-15. SFP port
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left 11 is the control port. Send an Ethernet frame with ethtype 0x8099 to
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this port to reconfigure the switch, the first 16 payload bytes corresponding
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to the 16 switch output ports, each byte selecting which input port will be
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connected. It is possible to connect multiple output ports to the same input
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port.
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