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143 lines
4.3 KiB
Coq
143 lines
4.3 KiB
Coq
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/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1 ns / 1 ps
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module test_axis_demux_4;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [7:0] input_axis_tdata = 0;
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reg input_axis_tvalid = 0;
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reg input_axis_tlast = 0;
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reg input_axis_tuser = 0;
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reg output_0_axis_tready = 0;
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reg output_1_axis_tready = 0;
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reg output_2_axis_tready = 0;
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reg output_3_axis_tready = 0;
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reg [1:0] select = 0;
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// Outputs
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wire input_axis_tready;
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wire [7:0] output_0_axis_tdata;
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wire output_0_axis_tvalid;
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wire output_0_axis_tlast;
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wire output_0_axis_tuser;
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wire [7:0] output_1_axis_tdata;
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wire output_1_axis_tvalid;
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wire output_1_axis_tlast;
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wire output_1_axis_tuser;
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wire [7:0] output_2_axis_tdata;
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wire output_2_axis_tvalid;
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wire output_2_axis_tlast;
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wire output_2_axis_tuser;
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wire [7:0] output_3_axis_tdata;
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wire output_3_axis_tvalid;
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wire output_3_axis_tlast;
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wire output_3_axis_tuser;
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initial begin
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// myhdl integration
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$from_myhdl(clk,
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rst,
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current_test,
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input_axis_tdata,
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input_axis_tvalid,
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input_axis_tlast,
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input_axis_tuser,
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output_0_axis_tready,
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output_1_axis_tready,
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output_2_axis_tready,
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output_3_axis_tready,
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select);
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$to_myhdl(input_axis_tready,
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output_0_axis_tdata,
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output_0_axis_tvalid,
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output_0_axis_tlast,
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output_0_axis_tuser,
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output_1_axis_tdata,
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output_1_axis_tvalid,
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output_1_axis_tlast,
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output_1_axis_tuser,
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output_2_axis_tdata,
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output_2_axis_tvalid,
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output_2_axis_tlast,
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output_2_axis_tuser,
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output_3_axis_tdata,
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output_3_axis_tvalid,
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output_3_axis_tlast,
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output_3_axis_tuser);
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// dump file
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$dumpfile("test_axis_demux_4.lxt");
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$dumpvars(0, test_axis_demux_4);
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end
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axis_demux_4 #(
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.DATA_WIDTH(8)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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// AXI input
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.input_axis_tdata(input_axis_tdata),
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.input_axis_tvalid(input_axis_tvalid),
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.input_axis_tready(input_axis_tready),
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.input_axis_tlast(input_axis_tlast),
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.input_axis_tuser(input_axis_tuser),
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// AXI outputs
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.output_0_axis_tdata(output_0_axis_tdata),
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.output_0_axis_tvalid(output_0_axis_tvalid),
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.output_0_axis_tready(output_0_axis_tready),
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.output_0_axis_tlast(output_0_axis_tlast),
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.output_0_axis_tuser(output_0_axis_tuser),
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.output_1_axis_tdata(output_1_axis_tdata),
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.output_1_axis_tvalid(output_1_axis_tvalid),
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.output_1_axis_tready(output_1_axis_tready),
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.output_1_axis_tlast(output_1_axis_tlast),
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.output_1_axis_tuser(output_1_axis_tuser),
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.output_2_axis_tdata(output_2_axis_tdata),
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.output_2_axis_tvalid(output_2_axis_tvalid),
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.output_2_axis_tready(output_2_axis_tready),
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.output_2_axis_tlast(output_2_axis_tlast),
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.output_2_axis_tuser(output_2_axis_tuser),
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.output_3_axis_tdata(output_3_axis_tdata),
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.output_3_axis_tvalid(output_3_axis_tvalid),
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.output_3_axis_tready(output_3_axis_tready),
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.output_3_axis_tlast(output_3_axis_tlast),
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.output_3_axis_tuser(output_3_axis_tuser),
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// Control
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.select(select)
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);
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endmodule
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