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31 lines
845 B
Markdown
31 lines
845 B
Markdown
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# Verilog Ethernet Stratix 10 DX Example Design
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## Introduction
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This example design targets the Intel Stratix 10 DX FPGA development board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests.
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* FPGA: 1SD280PT2F55E1VG
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* PHY: Transceiver in 10G BASE-R native mode
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## How to build
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Run make to build. Ensure that the Intel Quartus Prime Pro toolchain
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components are in PATH.
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## How to test
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Run make program to program the board with the Intel software. Then run
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netcat -u 192.168.1.128 1234
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to open a UDP connection to port 1234. Any text entered into netcat will be
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echoed back after pressing enter.
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It is also possible to use hping to test the design by running
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hping 192.168.1.128 -2 -p 1234 -d 1024
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