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29 lines
773 B
Markdown
29 lines
773 B
Markdown
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# Verilog Ethernet ML605 SGMII Example Design
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## Introduction
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This example design targets the Xilinx ML605 FPGA board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests.
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Configure the PHY for SGMII by placing J66 and J67 across pins 2 and 3 and
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opening J68.
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FPGA: XC6SlX45-2CSG324
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PHY: Marvell M88E1111
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## How to build
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Run make to build. Ensure that the Xilinx ISE toolchain components are
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in PATH.
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## How to test
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Run make program to program the ML605 board with the Xilinx Impact software.
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Then run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234.
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Any text entered into netcat will be echoed back after pressing enter.
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