mirror of
https://github.com/corundum/corundum.git
synced 2025-02-06 08:38:23 +08:00
20 lines
709 B
Markdown
20 lines
709 B
Markdown
|
# Verilog PCIe Alveo U200 Example Design
|
||
|
|
|
||
|
|
## Introduction
|
||
|
|
|
||
|
|
This example design targets the Xilinx Alveo U200 FPGA board.
|
||
|
|
|
||
|
|
The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design.
|
||
|
|
|
||
|
|
* FPGA: xcu200-fsgd2104-2-e
|
||
|
|
|
||
|
|
## How to build
|
||
|
|
|
||
|
|
Run `make` to build. Ensure that the Xilinx Vivado components are in PATH.
|
||
|
|
|
||
|
|
Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
|
||
|
|
|
||
|
|
## How to test
|
||
|
|
|
||
|
|
Run `make program` to program the Alveo U200 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output.
|