2020-10-02 16:53:41 -07:00
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/*
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Copyright 2020, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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#include "fpga_id.h"
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struct fpga_id {
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int id;
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int mask;
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char part[16];
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};
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const struct fpga_id fpga_id_list[] =
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{
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// Xilinx
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// Artix 7
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{FPGA_ID_XC7A15T, FPGA_ID_MASK_NOVER, "XC7A15T"},
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{FPGA_ID_XC7A35T, FPGA_ID_MASK_NOVER, "XC7A35T"},
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{FPGA_ID_XC7A50T, FPGA_ID_MASK_NOVER, "XC7A50T"},
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{FPGA_ID_XC7A75T, FPGA_ID_MASK_NOVER, "XC7A75T"},
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{FPGA_ID_XC7A100T, FPGA_ID_MASK_NOVER, "XC7A100T"},
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{FPGA_ID_XC7A200T, FPGA_ID_MASK_NOVER, "XC7A200T"},
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// Kintex 7
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{FPGA_ID_XC7K70T, FPGA_ID_MASK_NOVER, "XC7K70T"},
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{FPGA_ID_XC7K160T, FPGA_ID_MASK_NOVER, "XC7K160T"},
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{FPGA_ID_XC7K325T, FPGA_ID_MASK_NOVER, "XC7K325T"},
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{FPGA_ID_XC7K355T, FPGA_ID_MASK_NOVER, "XC7K355T"},
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{FPGA_ID_XC7K410T, FPGA_ID_MASK_NOVER, "XC7K410T"},
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{FPGA_ID_XC7K420T, FPGA_ID_MASK_NOVER, "XC7K420T"},
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{FPGA_ID_XC7K480T, FPGA_ID_MASK_NOVER, "XC7K480T"},
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// Virtex 7
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{FPGA_ID_XC7V585T, FPGA_ID_MASK_NOVER, "XC7V585T"},
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{FPGA_ID_XC7V2000T, FPGA_ID_MASK_NOVER, "XC7V2000T"},
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{FPGA_ID_XC7VX330T, FPGA_ID_MASK_NOVER, "XC7VX330T"},
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{FPGA_ID_XC7VX415T, FPGA_ID_MASK_NOVER, "XC7VX415T"},
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{FPGA_ID_XC7VX485T, FPGA_ID_MASK_NOVER, "XC7VX485T"},
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{FPGA_ID_XC7VX550T, FPGA_ID_MASK_NOVER, "XC7VX550T"},
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{FPGA_ID_XC7VX690T, FPGA_ID_MASK_NOVER, "XC7VX690T"},
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{FPGA_ID_XC7VX980T, FPGA_ID_MASK_NOVER, "XC7VX980T"},
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{FPGA_ID_XC7VX1140T, FPGA_ID_MASK_NOVER, "XC7VX1140T"},
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{FPGA_ID_XC7VH580T, FPGA_ID_MASK_NOVER, "XC7VH580T"},
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{FPGA_ID_XC7VH870T, FPGA_ID_MASK_NOVER, "XC7VH870T"},
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// Kintex Ultrascale
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{FPGA_ID_XCKU025, FPGA_ID_MASK_NOVER, "XCKU025"},
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{FPGA_ID_XCKU035, FPGA_ID_MASK_NOVER, "XCKU035"},
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{FPGA_ID_XCKU040, FPGA_ID_MASK_NOVER, "XCKU040"},
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{FPGA_ID_XCKU060, FPGA_ID_MASK_NOVER, "XCKU060"},
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{FPGA_ID_XCKU085, FPGA_ID_MASK_NOVER, "XCKU085"},
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{FPGA_ID_XCKU095, FPGA_ID_MASK_NOVER, "XCKU095"},
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{FPGA_ID_XCKU115, FPGA_ID_MASK_NOVER, "XCKU115"},
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// Virtex Ultrascale
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{FPGA_ID_XCVU065, FPGA_ID_MASK_NOVER, "XCVU065"},
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{FPGA_ID_XCVU080, FPGA_ID_MASK_NOVER, "XCVU080"},
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{FPGA_ID_XCVU095, FPGA_ID_MASK_NOVER, "XCVU095"},
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{FPGA_ID_XCVU125, FPGA_ID_MASK_NOVER, "XCVU125"},
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{FPGA_ID_XCVU160, FPGA_ID_MASK_NOVER, "XCVU160"},
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{FPGA_ID_XCVU190, FPGA_ID_MASK_NOVER, "XCVU190"},
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{FPGA_ID_XCVU440, FPGA_ID_MASK_NOVER, "XCVU440"},
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// Kintex Ultrascale+
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{FPGA_ID_XCKU3P, FPGA_ID_MASK_NOVER, "XCKU3P"},
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{FPGA_ID_XCKU5P, FPGA_ID_MASK_NOVER, "XCKU5P"},
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{FPGA_ID_XCKU9P, FPGA_ID_MASK_NOVER, "XCKU9P"},
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{FPGA_ID_XCKU11P, FPGA_ID_MASK_NOVER, "XCKU11P"},
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{FPGA_ID_XCKU13P, FPGA_ID_MASK_NOVER, "XCKU13P"},
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{FPGA_ID_XCKU15P, FPGA_ID_MASK_NOVER, "XCKU15P"},
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// Virtex Ultrascale+
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{FPGA_ID_XCVU3P, FPGA_ID_MASK_NOVER, "XCVU3P"},
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{FPGA_ID_XCVU5P, FPGA_ID_MASK_NOVER, "XCVU5P"},
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{FPGA_ID_XCVU7P, FPGA_ID_MASK_NOVER, "XCVU7P"},
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{FPGA_ID_XCVU9P, FPGA_ID_MASK_NOVER, "XCVU9P"},
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{FPGA_ID_XCVU11P, FPGA_ID_MASK_NOVER, "XCVU11P"},
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{FPGA_ID_XCVU13P, FPGA_ID_MASK_NOVER, "XCVU13P"},
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// Zynq Ultrascale+
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{FPGA_ID_XCZU2, FPGA_ID_MASK_NOVER, "XCZU2"},
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{FPGA_ID_XCZU3, FPGA_ID_MASK_NOVER, "XCZU3"},
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{FPGA_ID_XCZU4, FPGA_ID_MASK_NOVER, "XCZU4"},
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{FPGA_ID_XCZU5, FPGA_ID_MASK_NOVER, "XCZU5"},
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{FPGA_ID_XCZU6, FPGA_ID_MASK_NOVER, "XCZU6"},
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{FPGA_ID_XCZU7, FPGA_ID_MASK_NOVER, "XCZU7"},
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{FPGA_ID_XCZU9, FPGA_ID_MASK_NOVER, "XCZU9"},
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{FPGA_ID_XCZU11, FPGA_ID_MASK_NOVER, "XCZU11"},
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{FPGA_ID_XCZU15, FPGA_ID_MASK_NOVER, "XCZU15"},
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{FPGA_ID_XCZU17, FPGA_ID_MASK_NOVER, "XCZU17"},
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{FPGA_ID_XCZU19, FPGA_ID_MASK_NOVER, "XCZU19"},
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{FPGA_ID_XCZU21, FPGA_ID_MASK_NOVER, "XCZU21"},
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{FPGA_ID_XCZU25, FPGA_ID_MASK_NOVER, "XCZU25"},
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{FPGA_ID_XCZU27, FPGA_ID_MASK_NOVER, "XCZU27"},
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{FPGA_ID_XCZU28, FPGA_ID_MASK_NOVER, "XCZU28"},
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{FPGA_ID_XCZU29, FPGA_ID_MASK_NOVER, "XCZU29"},
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// Alveo
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{FPGA_ID_XCU50, FPGA_ID_MASK_NOVER, "XCU50"},
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{FPGA_ID_XCU200, FPGA_ID_MASK_NOVER, "XCU200"},
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{FPGA_ID_XCU250, FPGA_ID_MASK_NOVER, "XCU250"},
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{FPGA_ID_XCU280, FPGA_ID_MASK_NOVER, "XCU280"},
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// Intel
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// Stratix 10
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{FPGA_ID_1SG10MH_U1, FPGA_ID_MASK_FULL, "1SG10MH_U1"},
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{FPGA_ID_1SG10MH_U2, FPGA_ID_MASK_FULL, "1SG10MH_U2"},
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{FPGA_ID_1SG040H, FPGA_ID_MASK_FULL, "1SG040H"},
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{FPGA_ID_1SG040H_NL, FPGA_ID_MASK_FULL, "1SG040H(NL)"},
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{FPGA_ID_1SG065H, FPGA_ID_MASK_FULL, "1SG065H"},
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{FPGA_ID_1SG065H_NL, FPGA_ID_MASK_FULL, "1SG065H(NL)"},
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{FPGA_ID_1SG085H, FPGA_ID_MASK_FULL, "1SG085H"},
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{FPGA_ID_1SG110H, FPGA_ID_MASK_FULL, "1SG110H"},
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{FPGA_ID_1SG110H_NL, FPGA_ID_MASK_FULL, "1SG110H(NL)"},
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{FPGA_ID_1SG165H, FPGA_ID_MASK_FULL, "1SG165H"},
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{FPGA_ID_1SG166H, FPGA_ID_MASK_FULL, "1SG166H"},
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{FPGA_ID_1SG166H_NL, FPGA_ID_MASK_FULL, "1SG166H(NL)"},
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{FPGA_ID_1SG210H, FPGA_ID_MASK_FULL, "1SG210H"},
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{FPGA_ID_1SG210H_ES1, FPGA_ID_MASK_FULL, "1SG210H(ES1)"},
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{FPGA_ID_1SG211H, FPGA_ID_MASK_FULL, "1SG211H"},
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{FPGA_ID_1SG250L, FPGA_ID_MASK_FULL, "1SG250L"},
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{FPGA_ID_1SG250H, FPGA_ID_MASK_FULL, "1SG250H"},
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{FPGA_ID_1SG280L, FPGA_ID_MASK_FULL, "1SG280L"},
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{FPGA_ID_1SG280L_NL, FPGA_ID_MASK_FULL, "1SG280L(NL)"},
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{FPGA_ID_1SG280L_ES1, FPGA_ID_MASK_FULL, "1SG280L(ES1)"},
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{FPGA_ID_1SG280L_ES2, FPGA_ID_MASK_FULL, "1SG280L(ES2)"},
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{FPGA_ID_1SG280L_ES3, FPGA_ID_MASK_FULL, "1SG280L(ES3)"},
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{FPGA_ID_1SG280H, FPGA_ID_MASK_FULL, "1SG280H"},
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{FPGA_ID_1SG280H_NL, FPGA_ID_MASK_FULL, "1SG280H(NL)"},
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{FPGA_ID_1SG280H_ES1, FPGA_ID_MASK_FULL, "1SG280H(ES1)"},
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{FPGA_ID_1SG280H_ES2, FPGA_ID_MASK_FULL, "1SG280H(ES2)"},
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{FPGA_ID_1SG280H_ES3, FPGA_ID_MASK_FULL, "1SG280H(ES3)"},
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{FPGA_ID_1SX040H, FPGA_ID_MASK_FULL, "1SX040H"},
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{FPGA_ID_1SX065H, FPGA_ID_MASK_FULL, "1SX065H"},
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{FPGA_ID_1SX085H, FPGA_ID_MASK_FULL, "1SX085H"},
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{FPGA_ID_1SX110H, FPGA_ID_MASK_FULL, "1SX110H"},
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{FPGA_ID_1SX165H, FPGA_ID_MASK_FULL, "1SX165H"},
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{FPGA_ID_1SX210H, FPGA_ID_MASK_FULL, "1SX210H"},
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{FPGA_ID_1SX250L, FPGA_ID_MASK_FULL, "1SX250L"},
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{FPGA_ID_1SX250H, FPGA_ID_MASK_FULL, "1SX250H"},
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{FPGA_ID_1SX280L, FPGA_ID_MASK_FULL, "1SX280L"},
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{FPGA_ID_1SX280L_ES1, FPGA_ID_MASK_FULL, "1SX280L(ES1)"},
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{FPGA_ID_1SX280L_ES2, FPGA_ID_MASK_FULL, "1SX280L(ES2)"},
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{FPGA_ID_1SX280H, FPGA_ID_MASK_FULL, "1SX280H"},
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{FPGA_ID_1SX280H_ES1, FPGA_ID_MASK_FULL, "1SX280H(ES1)"},
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{FPGA_ID_1SX280H_ES2, FPGA_ID_MASK_FULL, "1SX280H(ES2)"},
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{FPGA_ID_1ST040E, FPGA_ID_MASK_FULL, "1ST040E"},
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{FPGA_ID_1ST040E_NL, FPGA_ID_MASK_FULL, "1ST040E(NL)"},
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{FPGA_ID_1ST085E, FPGA_ID_MASK_FULL, "1ST085E"},
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{FPGA_ID_1ST110E, FPGA_ID_MASK_FULL, "1ST110E"},
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{FPGA_ID_1ST110E_NL, FPGA_ID_MASK_FULL, "1ST110E(NL)"},
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{FPGA_ID_1ST165E, FPGA_ID_MASK_FULL, "1ST165E"},
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{FPGA_ID_1ST210E, FPGA_ID_MASK_FULL, "1ST210E"},
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{FPGA_ID_1ST210E_ES1, FPGA_ID_MASK_FULL, "1ST210E(ES1)"},
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{FPGA_ID_1ST250E, FPGA_ID_MASK_FULL, "1ST250E"},
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{FPGA_ID_1ST280E, FPGA_ID_MASK_FULL, "1ST280E"},
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{FPGA_ID_1ST280E_ES1, FPGA_ID_MASK_FULL, "1ST280E(ES1)"},
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{FPGA_ID_1SM16BE, FPGA_ID_MASK_FULL, "1SM16BE"},
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{FPGA_ID_1SM16BE_ES1, FPGA_ID_MASK_FULL, "1SM16BE(ES1)"},
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{FPGA_ID_1SM16BH, FPGA_ID_MASK_FULL, "1SM16BH"},
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{FPGA_ID_1SM16BH_ES1, FPGA_ID_MASK_FULL, "1SM16BH(ES1)"},
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{FPGA_ID_1SM16CH, FPGA_ID_MASK_FULL, "1SM16CH"},
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{FPGA_ID_1SM16CH_ES1, FPGA_ID_MASK_FULL, "1SM16CH(ES1)"},
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{FPGA_ID_1SM21BE, FPGA_ID_MASK_FULL, "1SM21BE"},
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{FPGA_ID_1SM21BE_ES1, FPGA_ID_MASK_FULL, "1SM21BE(ES1)"},
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{FPGA_ID_1SM21BH, FPGA_ID_MASK_FULL, "1SM21BH"},
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{FPGA_ID_1SM21BH_ES1, FPGA_ID_MASK_FULL, "1SM21BH(ES1)"},
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{FPGA_ID_1SM21CH, FPGA_ID_MASK_FULL, "1SM21CH"},
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{FPGA_ID_1SM21CH_ES1, FPGA_ID_MASK_FULL, "1SM21CH(ES1)"},
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{FPGA_ID_1SD110P, FPGA_ID_MASK_FULL, "1SD110P"},
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{FPGA_ID_1SD110P_NL, FPGA_ID_MASK_FULL, "1SD110P(NL)"},
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{FPGA_ID_1SD21BP, FPGA_ID_MASK_FULL, "1SD21BP"},
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{FPGA_ID_1SD280P, FPGA_ID_MASK_FULL, "1SD280P"},
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// end of list
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{0, 0, ""}
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};
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const char *get_fpga_part(int id)
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{
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const struct fpga_id *ptr = fpga_id_list;
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while (ptr->id && ((ptr->id ^ id) & ptr->mask) != 0)
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{
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ptr++;
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}
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return ptr->part;
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}
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