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27 lines
820 B
Markdown
27 lines
820 B
Markdown
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# Verilog Ethernet Alveo U250 Example Design
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## Introduction
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This example design targets the Xilinx Alveo U250 FPGA board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests. The design also enables the gigabit Ethernet interface for
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testing with a QSFP loopback adapter.
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FPGA: xcu250-figd2104-2-e
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PHY: 10G BASE-R PHY IP core and internal GTY transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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## How to test
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Run make program to program the Alveo U250 board with Vivado. Then run
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netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
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entered into netcat will be echoed back after pressing enter.
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