FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity
corundum/docs/source/rb/if_ctrl.rst

168 lines
7.2 KiB
ReStructuredText
Raw Normal View History

Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
.. _rb_if_ctrl:
================================
Interface control register block
================================
Add RX queue mapping module Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-04-23 00:12:22 -07:00
The interface control register block has a header with type 0x0000C001, version 0x00000400, and contains several interface-level control registers.
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
.. table::
======== ============= ====== ====== ====== ====== =============
Address Field 31..24 23..16 15..8 7..0 Reset value
======== ============= ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C001
-------- ------------- -------------- -------------- -------------
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
2022-03-28 17:23:27 -07:00
RBB+0x04 Version Major Minor Patch Meta RO 0x00000300
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------
RBB+0x0C Features Interface feature bits RO -
-------- ------------- ------------------------------ -------------
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
2022-03-28 17:23:27 -07:00
RBB+0x10 Port count Port count RO -
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
-------- ------------- ------------------------------ -------------
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
2022-03-28 17:23:27 -07:00
RBB+0x14 Sched count Scheduler block count RO -
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
-------- ------------- ------------------------------ -------------
docs: Fix table Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-04-07 22:42:47 -07:00
RBB+0x18 \- \- RO -
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
-------- ------------- ------------------------------ -------------
docs: Fix table Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-04-07 22:42:47 -07:00
RBB+0x1C \- \- RO -
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
-------- ------------- ------------------------------ -------------
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
2022-03-28 17:23:27 -07:00
RBB+0x20 Max TX MTU Max TX MTU RO -
-------- ------------- ------------------------------ -------------
RBB+0x24 Max RX MTU Max RX MTU RO -
-------- ------------- ------------------------------ -------------
RBB+0x28 TX MTU TX MTU RW -
-------- ------------- ------------------------------ -------------
RBB+0x2C RX MTU RX MTU RW -
Generate pause frames on TX Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-09-10 23:22:50 -07:00
-------- ------------- ------------------------------ -------------
RBB+0x30 TX FIFO depth TX FIFO depth RO -
-------- ------------- ------------------------------ -------------
RBB+0x34 RX FIFO depth RX FIFO depth RO -
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
======== ============= ============================== =============
See :ref:`rb_overview` for definitions of the standard register block header fields.
.. object:: Features
The features field contains all of the interface-level feature bits, indicating the state of various optional features that can be enabled via Verilog parameters during synthesis.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x0C Interface feature bits RO -
======== ============================== =============
Currently implemented feature bits:
.. table::
=== =======================
Bit Feature
=== =======================
0 RSS
4 PTP timestamping
8 TX checksum offloading
9 RX checksum offloading
10 RX flow hash offloading
Add flow control Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-09-09 19:01:36 -07:00
11 LFC (IEEE 802.3 annex 31B)
12 PFC (IEEE 802.3 annex 31D)
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
=== =======================
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
2022-03-28 17:23:27 -07:00
.. object:: Port count
The port count field contains the number of ports associated with the interface, as configured via Verilog parameters during synthesis.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x10 Port count RO -
======== ============================== =============
.. object:: Scheduler block count
The scheduler block count field contains the number of scheduler blocks associated with the interface, as configured via Verilog parameters during synthesis.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x14 Scheduler block count RO -
======== ============================== =============
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
.. object:: Max TX MTU
The max TX MTU field contains the maximum frame size on the transmit path, as configured via Verilog parameters during synthesis.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
2022-03-28 17:23:27 -07:00
RBB+0x20 Max TX MTU RO -
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
======== ============================== =============
.. object:: Max RX MTU
The max RX MTU field contains the maximum frame size on the receive path, as configured via Verilog parameters during synthesis.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
2022-03-28 17:23:27 -07:00
RBB+0x24 Max RX MTU RO -
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
======== ============================== =============
.. object:: TX MTU
The TX MTU field controls the maximum frame size on the transmit path.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
2022-03-28 17:23:27 -07:00
RBB+0x28 TX MTU RW -
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
======== ============================== =============
.. object:: RX MTU
The RX MTU field controls the maximum frame size on the receive path.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
2022-03-28 17:23:27 -07:00
RBB+0x2C RX MTU RW -
Initial commit of sphinx documentation
2022-03-13 23:32:01 -07:00
======== ============================== =============
Generate pause frames on TX Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-09-10 23:22:50 -07:00
.. object:: TX FIFO depth
The TX FIFO depth field contains the size of the transmit FIFO in bytes, as configured via Verilog parameters during synthesis.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x30 TX FIFO depth RO -
======== ============================== =============
.. object:: RX FIFO depth
The RX FIFO depth field contains the size of the receive FIFO in bytes, as configured via Verilog parameters during synthesis.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x34 RX FIFO depth RO -
======== ============================== =============
Reference in New Issue Copy Permalink