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corundum/utils/fpga_id.c

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Add FPGA ID code for userspace tools
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/*
Copyright 2020, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
#include "fpga_id.h"
struct fpga_id {
int id;
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int mask;
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char part[16];
};
const struct fpga_id fpga_id_list[] =
{
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// Xilinx
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// Spartan 7
{FPGA_ID_XC7S6, FPGA_ID_MASK_NOVER, "XC7S6"},
{FPGA_ID_XC7S15, FPGA_ID_MASK_NOVER, "XC7S15"},
{FPGA_ID_XC7S25, FPGA_ID_MASK_NOVER, "XC7S25"},
{FPGA_ID_XC7S50, FPGA_ID_MASK_NOVER, "XC7S50"},
{FPGA_ID_XC7S75, FPGA_ID_MASK_NOVER, "XC7S75"},
{FPGA_ID_XC7S100, FPGA_ID_MASK_NOVER, "XC7S100"},
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// Artix 7
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{FPGA_ID_XC7A15T, FPGA_ID_MASK_NOVER, "XC7A15T"},
{FPGA_ID_XC7A35T, FPGA_ID_MASK_NOVER, "XC7A35T"},
{FPGA_ID_XC7A50T, FPGA_ID_MASK_NOVER, "XC7A50T"},
{FPGA_ID_XC7A75T, FPGA_ID_MASK_NOVER, "XC7A75T"},
{FPGA_ID_XC7A100T, FPGA_ID_MASK_NOVER, "XC7A100T"},
{FPGA_ID_XC7A200T, FPGA_ID_MASK_NOVER, "XC7A200T"},
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// Kintex 7
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{FPGA_ID_XC7K70T, FPGA_ID_MASK_NOVER, "XC7K70T"},
{FPGA_ID_XC7K160T, FPGA_ID_MASK_NOVER, "XC7K160T"},
{FPGA_ID_XC7K325T, FPGA_ID_MASK_NOVER, "XC7K325T"},
{FPGA_ID_XC7K355T, FPGA_ID_MASK_NOVER, "XC7K355T"},
{FPGA_ID_XC7K410T, FPGA_ID_MASK_NOVER, "XC7K410T"},
{FPGA_ID_XC7K420T, FPGA_ID_MASK_NOVER, "XC7K420T"},
{FPGA_ID_XC7K480T, FPGA_ID_MASK_NOVER, "XC7K480T"},
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// Virtex 7
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{FPGA_ID_XC7V585T, FPGA_ID_MASK_NOVER, "XC7V585T"},
{FPGA_ID_XC7V2000T, FPGA_ID_MASK_NOVER, "XC7V2000T"},
{FPGA_ID_XC7VX330T, FPGA_ID_MASK_NOVER, "XC7VX330T"},
{FPGA_ID_XC7VX415T, FPGA_ID_MASK_NOVER, "XC7VX415T"},
{FPGA_ID_XC7VX485T, FPGA_ID_MASK_NOVER, "XC7VX485T"},
{FPGA_ID_XC7VX550T, FPGA_ID_MASK_NOVER, "XC7VX550T"},
{FPGA_ID_XC7VX690T, FPGA_ID_MASK_NOVER, "XC7VX690T"},
{FPGA_ID_XC7VX980T, FPGA_ID_MASK_NOVER, "XC7VX980T"},
{FPGA_ID_XC7VX1140T, FPGA_ID_MASK_NOVER, "XC7VX1140T"},
{FPGA_ID_XC7VH580T, FPGA_ID_MASK_NOVER, "XC7VH580T"},
{FPGA_ID_XC7VH870T, FPGA_ID_MASK_NOVER, "XC7VH870T"},
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// Zynq 7000
{FPGA_ID_XC7Z007, FPGA_ID_MASK_NOVER, "XC7Z007"},
{FPGA_ID_XC7Z010, FPGA_ID_MASK_NOVER, "XC7Z010"},
{FPGA_ID_XC7Z012, FPGA_ID_MASK_NOVER, "XC7Z012"},
{FPGA_ID_XC7Z014, FPGA_ID_MASK_NOVER, "XC7Z014"},
{FPGA_ID_XC7Z015, FPGA_ID_MASK_NOVER, "XC7Z015"},
{FPGA_ID_XC7Z020, FPGA_ID_MASK_NOVER, "XC7Z020"},
{FPGA_ID_XC7Z030, FPGA_ID_MASK_NOVER, "XC7Z030"},
{FPGA_ID_XC7Z035, FPGA_ID_MASK_NOVER, "XC7Z035"},
{FPGA_ID_XC7Z045, FPGA_ID_MASK_NOVER, "XC7Z045"},
{FPGA_ID_XC7Z100, FPGA_ID_MASK_NOVER, "XC7Z100"},
// Kintex UltraScale
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{FPGA_ID_XCKU025, FPGA_ID_MASK_NOVER, "XCKU025"},
{FPGA_ID_XCKU035, FPGA_ID_MASK_NOVER, "XCKU035"},
{FPGA_ID_XCKU040, FPGA_ID_MASK_NOVER, "XCKU040"},
{FPGA_ID_XCKU060, FPGA_ID_MASK_NOVER, "XCKU060"},
{FPGA_ID_XCKU085, FPGA_ID_MASK_NOVER, "XCKU085"},
{FPGA_ID_XCKU095, FPGA_ID_MASK_NOVER, "XCKU095"},
{FPGA_ID_XCKU115, FPGA_ID_MASK_NOVER, "XCKU115"},
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// Virtex UltraScale
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{FPGA_ID_XCVU065, FPGA_ID_MASK_NOVER, "XCVU065"},
{FPGA_ID_XCVU080, FPGA_ID_MASK_NOVER, "XCVU080"},
{FPGA_ID_XCVU095, FPGA_ID_MASK_NOVER, "XCVU095"},
{FPGA_ID_XCVU125, FPGA_ID_MASK_NOVER, "XCVU125"},
{FPGA_ID_XCVU160, FPGA_ID_MASK_NOVER, "XCVU160"},
{FPGA_ID_XCVU190, FPGA_ID_MASK_NOVER, "XCVU190"},
{FPGA_ID_XCVU440, FPGA_ID_MASK_NOVER, "XCVU440"},
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// Artix UltraScale+
{FPGA_ID_XCAU10P, FPGA_ID_MASK_NOVER, "XCAU10P"},
{FPGA_ID_XCAU15P, FPGA_ID_MASK_NOVER, "XCAU15P"},
{FPGA_ID_XCAU20P, FPGA_ID_MASK_NOVER, "XCAU20P"},
{FPGA_ID_XCAU25P, FPGA_ID_MASK_NOVER, "XCAU25P"},
// Kintex UltraScale+
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{FPGA_ID_XCKU3P, FPGA_ID_MASK_NOVER, "XCKU3P"},
{FPGA_ID_XCKU5P, FPGA_ID_MASK_NOVER, "XCKU5P"},
{FPGA_ID_XCKU9P, FPGA_ID_MASK_NOVER, "XCKU9P"},
{FPGA_ID_XCKU11P, FPGA_ID_MASK_NOVER, "XCKU11P"},
{FPGA_ID_XCKU13P, FPGA_ID_MASK_NOVER, "XCKU13P"},
{FPGA_ID_XCKU15P, FPGA_ID_MASK_NOVER, "XCKU15P"},
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// Virtex UltraScale+
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{FPGA_ID_XCVU3P, FPGA_ID_MASK_NOVER, "XCVU3P"},
{FPGA_ID_XCVU5P, FPGA_ID_MASK_NOVER, "XCVU5P"},
{FPGA_ID_XCVU7P, FPGA_ID_MASK_NOVER, "XCVU7P"},
{FPGA_ID_XCVU9P, FPGA_ID_MASK_NOVER, "XCVU9P"},
{FPGA_ID_XCVU11P, FPGA_ID_MASK_NOVER, "XCVU11P"},
{FPGA_ID_XCVU13P, FPGA_ID_MASK_NOVER, "XCVU13P"},
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{FPGA_ID_XCVU19P, FPGA_ID_MASK_NOVER, "XCVU19P"},
{FPGA_ID_XCVU23P, FPGA_ID_MASK_NOVER, "XCVU23P"},
{FPGA_ID_XCVU27P, FPGA_ID_MASK_NOVER, "XCVU27P"},
{FPGA_ID_XCVU29P, FPGA_ID_MASK_NOVER, "XCVU29P"},
{FPGA_ID_XCVU31P, FPGA_ID_MASK_NOVER, "XCVU31P"},
{FPGA_ID_XCVU33P, FPGA_ID_MASK_NOVER, "XCVU33P"},
{FPGA_ID_XCVU35P, FPGA_ID_MASK_NOVER, "XCVU35P"},
{FPGA_ID_XCVU37P, FPGA_ID_MASK_NOVER, "XCVU37P"},
{FPGA_ID_XCVU45P, FPGA_ID_MASK_NOVER, "XCVU45P"},
{FPGA_ID_XCVU47P, FPGA_ID_MASK_NOVER, "XCVU47P"},
{FPGA_ID_XCVU57P, FPGA_ID_MASK_NOVER, "XCVU57P"},
// Zynq UltraScale+
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{FPGA_ID_XCZU2, FPGA_ID_MASK_NOVER, "XCZU2"},
{FPGA_ID_XCZU3, FPGA_ID_MASK_NOVER, "XCZU3"},
{FPGA_ID_XCZU4, FPGA_ID_MASK_NOVER, "XCZU4"},
{FPGA_ID_XCZU5, FPGA_ID_MASK_NOVER, "XCZU5"},
{FPGA_ID_XCZU6, FPGA_ID_MASK_NOVER, "XCZU6"},
{FPGA_ID_XCZU7, FPGA_ID_MASK_NOVER, "XCZU7"},
{FPGA_ID_XCZU9, FPGA_ID_MASK_NOVER, "XCZU9"},
{FPGA_ID_XCZU11, FPGA_ID_MASK_NOVER, "XCZU11"},
{FPGA_ID_XCZU15, FPGA_ID_MASK_NOVER, "XCZU15"},
{FPGA_ID_XCZU17, FPGA_ID_MASK_NOVER, "XCZU17"},
{FPGA_ID_XCZU19, FPGA_ID_MASK_NOVER, "XCZU19"},
{FPGA_ID_XCZU21, FPGA_ID_MASK_NOVER, "XCZU21"},
{FPGA_ID_XCZU25, FPGA_ID_MASK_NOVER, "XCZU25"},
{FPGA_ID_XCZU27, FPGA_ID_MASK_NOVER, "XCZU27"},
{FPGA_ID_XCZU28, FPGA_ID_MASK_NOVER, "XCZU28"},
{FPGA_ID_XCZU29, FPGA_ID_MASK_NOVER, "XCZU29"},
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{FPGA_ID_XCZU39, FPGA_ID_MASK_NOVER, "XCZU39"},
{FPGA_ID_XCZU43, FPGA_ID_MASK_NOVER, "XCZU43"},
{FPGA_ID_XCZU46, FPGA_ID_MASK_NOVER, "XCZU46"},
{FPGA_ID_XCZU47, FPGA_ID_MASK_NOVER, "XCZU47"},
{FPGA_ID_XCZU48, FPGA_ID_MASK_NOVER, "XCZU48"},
{FPGA_ID_XCZU49, FPGA_ID_MASK_NOVER, "XCZU49"},
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// Alveo
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{FPGA_ID_XCU50, FPGA_ID_MASK_NOVER, "XCU50"},
{FPGA_ID_XCU200, FPGA_ID_MASK_NOVER, "XCU200"},
{FPGA_ID_XCU250, FPGA_ID_MASK_NOVER, "XCU250"},
{FPGA_ID_XCU280, FPGA_ID_MASK_NOVER, "XCU280"},
// Intel
// Stratix 10
{FPGA_ID_1SG10MH_U1, FPGA_ID_MASK_FULL, "1SG10MH_U1"},
{FPGA_ID_1SG10MH_U2, FPGA_ID_MASK_FULL, "1SG10MH_U2"},
{FPGA_ID_1SG040H, FPGA_ID_MASK_FULL, "1SG040H"},
{FPGA_ID_1SG040H_NL, FPGA_ID_MASK_FULL, "1SG040H(NL)"},
{FPGA_ID_1SG065H, FPGA_ID_MASK_FULL, "1SG065H"},
{FPGA_ID_1SG065H_NL, FPGA_ID_MASK_FULL, "1SG065H(NL)"},
{FPGA_ID_1SG085H, FPGA_ID_MASK_FULL, "1SG085H"},
{FPGA_ID_1SG110H, FPGA_ID_MASK_FULL, "1SG110H"},
{FPGA_ID_1SG110H_NL, FPGA_ID_MASK_FULL, "1SG110H(NL)"},
{FPGA_ID_1SG165H, FPGA_ID_MASK_FULL, "1SG165H"},
{FPGA_ID_1SG166H, FPGA_ID_MASK_FULL, "1SG166H"},
{FPGA_ID_1SG166H_NL, FPGA_ID_MASK_FULL, "1SG166H(NL)"},
{FPGA_ID_1SG210H, FPGA_ID_MASK_FULL, "1SG210H"},
{FPGA_ID_1SG210H_ES1, FPGA_ID_MASK_FULL, "1SG210H(ES1)"},
{FPGA_ID_1SG211H, FPGA_ID_MASK_FULL, "1SG211H"},
{FPGA_ID_1SG250L, FPGA_ID_MASK_FULL, "1SG250L"},
{FPGA_ID_1SG250H, FPGA_ID_MASK_FULL, "1SG250H"},
{FPGA_ID_1SG280L, FPGA_ID_MASK_FULL, "1SG280L"},
{FPGA_ID_1SG280L_NL, FPGA_ID_MASK_FULL, "1SG280L(NL)"},
{FPGA_ID_1SG280L_ES1, FPGA_ID_MASK_FULL, "1SG280L(ES1)"},
{FPGA_ID_1SG280L_ES2, FPGA_ID_MASK_FULL, "1SG280L(ES2)"},
{FPGA_ID_1SG280L_ES3, FPGA_ID_MASK_FULL, "1SG280L(ES3)"},
{FPGA_ID_1SG280H, FPGA_ID_MASK_FULL, "1SG280H"},
{FPGA_ID_1SG280H_NL, FPGA_ID_MASK_FULL, "1SG280H(NL)"},
{FPGA_ID_1SG280H_ES1, FPGA_ID_MASK_FULL, "1SG280H(ES1)"},
{FPGA_ID_1SG280H_ES2, FPGA_ID_MASK_FULL, "1SG280H(ES2)"},
{FPGA_ID_1SG280H_ES3, FPGA_ID_MASK_FULL, "1SG280H(ES3)"},
{FPGA_ID_1SX040H, FPGA_ID_MASK_FULL, "1SX040H"},
{FPGA_ID_1SX065H, FPGA_ID_MASK_FULL, "1SX065H"},
{FPGA_ID_1SX085H, FPGA_ID_MASK_FULL, "1SX085H"},
{FPGA_ID_1SX110H, FPGA_ID_MASK_FULL, "1SX110H"},
{FPGA_ID_1SX165H, FPGA_ID_MASK_FULL, "1SX165H"},
{FPGA_ID_1SX210H, FPGA_ID_MASK_FULL, "1SX210H"},
{FPGA_ID_1SX250L, FPGA_ID_MASK_FULL, "1SX250L"},
{FPGA_ID_1SX250H, FPGA_ID_MASK_FULL, "1SX250H"},
{FPGA_ID_1SX280L, FPGA_ID_MASK_FULL, "1SX280L"},
{FPGA_ID_1SX280L_ES1, FPGA_ID_MASK_FULL, "1SX280L(ES1)"},
{FPGA_ID_1SX280L_ES2, FPGA_ID_MASK_FULL, "1SX280L(ES2)"},
{FPGA_ID_1SX280H, FPGA_ID_MASK_FULL, "1SX280H"},
{FPGA_ID_1SX280H_ES1, FPGA_ID_MASK_FULL, "1SX280H(ES1)"},
{FPGA_ID_1SX280H_ES2, FPGA_ID_MASK_FULL, "1SX280H(ES2)"},
{FPGA_ID_1ST040E, FPGA_ID_MASK_FULL, "1ST040E"},
{FPGA_ID_1ST040E_NL, FPGA_ID_MASK_FULL, "1ST040E(NL)"},
{FPGA_ID_1ST085E, FPGA_ID_MASK_FULL, "1ST085E"},
{FPGA_ID_1ST110E, FPGA_ID_MASK_FULL, "1ST110E"},
{FPGA_ID_1ST110E_NL, FPGA_ID_MASK_FULL, "1ST110E(NL)"},
{FPGA_ID_1ST165E, FPGA_ID_MASK_FULL, "1ST165E"},
{FPGA_ID_1ST210E, FPGA_ID_MASK_FULL, "1ST210E"},
{FPGA_ID_1ST210E_ES1, FPGA_ID_MASK_FULL, "1ST210E(ES1)"},
{FPGA_ID_1ST250E, FPGA_ID_MASK_FULL, "1ST250E"},
{FPGA_ID_1ST280E, FPGA_ID_MASK_FULL, "1ST280E"},
{FPGA_ID_1ST280E_ES1, FPGA_ID_MASK_FULL, "1ST280E(ES1)"},
{FPGA_ID_1SM16BE, FPGA_ID_MASK_FULL, "1SM16BE"},
{FPGA_ID_1SM16BE_ES1, FPGA_ID_MASK_FULL, "1SM16BE(ES1)"},
{FPGA_ID_1SM16BH, FPGA_ID_MASK_FULL, "1SM16BH"},
{FPGA_ID_1SM16BH_ES1, FPGA_ID_MASK_FULL, "1SM16BH(ES1)"},
{FPGA_ID_1SM16CH, FPGA_ID_MASK_FULL, "1SM16CH"},
{FPGA_ID_1SM16CH_ES1, FPGA_ID_MASK_FULL, "1SM16CH(ES1)"},
{FPGA_ID_1SM21BE, FPGA_ID_MASK_FULL, "1SM21BE"},
{FPGA_ID_1SM21BE_ES1, FPGA_ID_MASK_FULL, "1SM21BE(ES1)"},
{FPGA_ID_1SM21BH, FPGA_ID_MASK_FULL, "1SM21BH"},
{FPGA_ID_1SM21BH_ES1, FPGA_ID_MASK_FULL, "1SM21BH(ES1)"},
{FPGA_ID_1SM21CH, FPGA_ID_MASK_FULL, "1SM21CH"},
{FPGA_ID_1SM21CH_ES1, FPGA_ID_MASK_FULL, "1SM21CH(ES1)"},
{FPGA_ID_1SD110P, FPGA_ID_MASK_FULL, "1SD110P"},
{FPGA_ID_1SD110P_NL, FPGA_ID_MASK_FULL, "1SD110P(NL)"},
{FPGA_ID_1SD21BP, FPGA_ID_MASK_FULL, "1SD21BP"},
{FPGA_ID_1SD280P, FPGA_ID_MASK_FULL, "1SD280P"},
// end of list
{0, 0, ""}
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};
const char *get_fpga_part(int id)
{
const struct fpga_id *ptr = fpga_id_list;
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while (ptr->id && ((ptr->id ^ id) & ptr->mask) != 0)
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{
ptr++;
}
return ptr->part;
}
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