diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/config.tcl similarity index 99% rename from fpga/mqnic/DE10_Agilex/fpga_100g/fpga/config.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/config.tcl index 423b949f7..b0b0ad58d 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/config.tcl @@ -53,6 +53,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/config.tcl similarity index 99% rename from fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/config.tcl index 0415200d2..db39aa575 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/config.tcl @@ -53,6 +53,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/config.tcl similarity index 99% rename from fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/config.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/config.tcl index ed3552aa7..ca0ac8079 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/config.tcl @@ -53,6 +53,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/config.tcl similarity index 99% rename from fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/config.tcl index aec0e8560..afb249fa7 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/config.tcl @@ -53,6 +53,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/config.tcl similarity index 99% rename from fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/config.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/config.tcl index 0b12f88dd..36a295d9d 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/config.tcl @@ -53,6 +53,10 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "0" +dict set params MAC_RSFEC "0" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" @@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" dict set params AXIS_ETH_TX_TS_PIPELINE "0" dict set params AXIS_ETH_RX_PIPELINE "0" dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" -dict set params MAC_RSFEC "0" # Statistics counter subsystem dict set params STAT_ENABLE "1" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/config.tcl similarity index 99% rename from fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/config.tcl index 8c38a9a44..9a125783b 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/config.tcl @@ -53,6 +53,10 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "0" +dict set params MAC_RSFEC "0" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" @@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" dict set params AXIS_ETH_TX_TS_PIPELINE "0" dict set params AXIS_ETH_RX_PIPELINE "0" dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" -dict set params MAC_RSFEC "0" # Statistics counter subsystem dict set params STAT_ENABLE "1" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl similarity index 99% rename from fpga/mqnic/DE10_Agilex/fpga_25g/fpga/config.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl index 04dfdc662..ea43421dc 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl @@ -53,6 +53,10 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "0" +dict set params MAC_RSFEC "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" @@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" dict set params AXIS_ETH_TX_TS_PIPELINE "0" dict set params AXIS_ETH_RX_PIPELINE "0" dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" -dict set params MAC_RSFEC "1" # Statistics counter subsystem dict set params STAT_ENABLE "1" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl similarity index 99% rename from fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl index 3755351e6..85b388257 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl @@ -53,6 +53,10 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "0" +dict set params MAC_RSFEC "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" @@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" dict set params AXIS_ETH_TX_TS_PIPELINE "0" dict set params AXIS_ETH_RX_PIPELINE "0" dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" -dict set params MAC_RSFEC "1" # Statistics counter subsystem dict set params STAT_ENABLE "1" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/ip/10g/mac_02.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/ip/10g/mac_02.tcl similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_25g/ip/10g/mac_02.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/ip/10g/mac_02.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/ip/10g/mac_13.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/ip/10g/mac_13.tcl similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_25g/ip/10g/mac_13.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/ip/10g/mac_13.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/ip/25g/mac_rsfec_02.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/ip/25g/mac_rsfec_02.tcl similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_25g/ip/25g/mac_rsfec_02.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/ip/25g/mac_rsfec_02.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/ip/25g/mac_rsfec_13.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/ip/25g/mac_rsfec_13.tcl similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_25g/ip/25g/mac_rsfec_13.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/ip/25g/mac_rsfec_13.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/ip/iopll_etile_ptp.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/ip/iopll_etile_ptp.tcl similarity index 100% rename from fpga/mqnic/DE10_Agilex/fpga_25g/ip/iopll_etile_ptp.tcl rename to fpga/mqnic/DE10_Agilex/fpga_100g/ip/iopll_etile_ptp.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/eth_mac_dual_quad_wrapper.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/eth_mac_dual_quad_wrapper.v similarity index 54% rename from fpga/mqnic/DE10_Agilex/fpga_25g/rtl/eth_mac_dual_quad_wrapper.v rename to fpga/mqnic/DE10_Agilex/fpga_100g/rtl/eth_mac_dual_quad_wrapper.v index ce159801a..9c2901584 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/eth_mac_dual_quad_wrapper.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/eth_mac_dual_quad_wrapper.v @@ -33,6 +33,7 @@ THE SOFTWARE. */ module eth_mac_dual_quad_wrapper # ( + parameter N_CH = 8, parameter PTP_TS_WIDTH = 96, parameter PTP_TAG_WIDTH = 8, parameter DATA_WIDTH = 64, @@ -42,331 +43,56 @@ module eth_mac_dual_quad_wrapper # parameter MAC_RSFEC = 0 ) ( - input wire ctrl_clk, - input wire ctrl_rst, - - output wire [7:0] tx_serial_data_p, - output wire [7:0] tx_serial_data_n, - input wire [7:0] rx_serial_data_p, - input wire [7:0] rx_serial_data_n, - input wire ref_clk, - input wire ptp_sample_clk, - - output wire mac_1_tx_clk, - output wire mac_1_tx_rst, - - output wire mac_1_tx_ptp_clk, - output wire mac_1_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_1_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_1_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_1_tx_ptp_ts_tag, - output wire mac_1_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_1_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_1_tx_axis_tkeep, - input wire mac_1_tx_axis_tvalid, - output wire mac_1_tx_axis_tready, - input wire mac_1_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_1_tx_axis_tuser, - - output wire mac_1_tx_status, - input wire mac_1_tx_lfc_req, - input wire [7:0] mac_1_tx_pfc_req, - - output wire mac_1_rx_clk, - output wire mac_1_rx_rst, - - output wire mac_1_rx_ptp_clk, - output wire mac_1_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_1_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_1_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_1_rx_axis_tkeep, - output wire mac_1_rx_axis_tvalid, - output wire mac_1_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_1_rx_axis_tuser, - - output wire mac_1_rx_status, - output wire mac_1_rx_lfc_req, - output wire [7:0] mac_1_rx_pfc_req, - - output wire mac_2_tx_clk, - output wire mac_2_tx_rst, - - output wire mac_2_tx_ptp_clk, - output wire mac_2_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_2_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_2_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_2_tx_ptp_ts_tag, - output wire mac_2_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_2_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_2_tx_axis_tkeep, - input wire mac_2_tx_axis_tvalid, - output wire mac_2_tx_axis_tready, - input wire mac_2_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_2_tx_axis_tuser, - - output wire mac_2_tx_status, - input wire mac_2_tx_lfc_req, - input wire [7:0] mac_2_tx_pfc_req, - - output wire mac_2_rx_clk, - output wire mac_2_rx_rst, - - output wire mac_2_rx_ptp_clk, - output wire mac_2_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_2_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_2_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_2_rx_axis_tkeep, - output wire mac_2_rx_axis_tvalid, - output wire mac_2_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_2_rx_axis_tuser, - - output wire mac_2_rx_status, - output wire mac_2_rx_lfc_req, - output wire [7:0] mac_2_rx_pfc_req, - - output wire mac_3_tx_clk, - output wire mac_3_tx_rst, - - output wire mac_3_tx_ptp_clk, - output wire mac_3_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_3_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_3_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_3_tx_ptp_ts_tag, - output wire mac_3_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_3_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_3_tx_axis_tkeep, - input wire mac_3_tx_axis_tvalid, - output wire mac_3_tx_axis_tready, - input wire mac_3_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_3_tx_axis_tuser, - - output wire mac_3_tx_status, - input wire mac_3_tx_lfc_req, - input wire [7:0] mac_3_tx_pfc_req, - - output wire mac_3_rx_clk, - output wire mac_3_rx_rst, - - output wire mac_3_rx_ptp_clk, - output wire mac_3_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_3_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_3_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_3_rx_axis_tkeep, - output wire mac_3_rx_axis_tvalid, - output wire mac_3_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_3_rx_axis_tuser, - - output wire mac_3_rx_status, - output wire mac_3_rx_lfc_req, - output wire [7:0] mac_3_rx_pfc_req, - - output wire mac_4_tx_clk, - output wire mac_4_tx_rst, - - output wire mac_4_tx_ptp_clk, - output wire mac_4_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_4_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_4_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_4_tx_ptp_ts_tag, - output wire mac_4_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_4_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_4_tx_axis_tkeep, - input wire mac_4_tx_axis_tvalid, - output wire mac_4_tx_axis_tready, - input wire mac_4_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_4_tx_axis_tuser, - - output wire mac_4_tx_status, - input wire mac_4_tx_lfc_req, - input wire [7:0] mac_4_tx_pfc_req, - - output wire mac_4_rx_clk, - output wire mac_4_rx_rst, - - output wire mac_4_rx_ptp_clk, - output wire mac_4_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_4_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_4_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_4_rx_axis_tkeep, - output wire mac_4_rx_axis_tvalid, - output wire mac_4_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_4_rx_axis_tuser, - - output wire mac_4_rx_status, - output wire mac_4_rx_lfc_req, - output wire [7:0] mac_4_rx_pfc_req, - - output wire mac_5_tx_clk, - output wire mac_5_tx_rst, - - output wire mac_5_tx_ptp_clk, - output wire mac_5_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_5_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_5_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_5_tx_ptp_ts_tag, - output wire mac_5_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_5_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_5_tx_axis_tkeep, - input wire mac_5_tx_axis_tvalid, - output wire mac_5_tx_axis_tready, - input wire mac_5_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_5_tx_axis_tuser, - - output wire mac_5_tx_status, - input wire mac_5_tx_lfc_req, - input wire [7:0] mac_5_tx_pfc_req, - - output wire mac_5_rx_clk, - output wire mac_5_rx_rst, - - output wire mac_5_rx_ptp_clk, - output wire mac_5_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_5_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_5_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_5_rx_axis_tkeep, - output wire mac_5_rx_axis_tvalid, - output wire mac_5_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_5_rx_axis_tuser, - - output wire mac_5_rx_status, - output wire mac_5_rx_lfc_req, - output wire [7:0] mac_5_rx_pfc_req, - - output wire mac_6_tx_clk, - output wire mac_6_tx_rst, - - output wire mac_6_tx_ptp_clk, - output wire mac_6_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_6_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_6_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_6_tx_ptp_ts_tag, - output wire mac_6_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_6_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_6_tx_axis_tkeep, - input wire mac_6_tx_axis_tvalid, - output wire mac_6_tx_axis_tready, - input wire mac_6_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_6_tx_axis_tuser, - - output wire mac_6_tx_status, - input wire mac_6_tx_lfc_req, - input wire [7:0] mac_6_tx_pfc_req, - - output wire mac_6_rx_clk, - output wire mac_6_rx_rst, - - output wire mac_6_rx_ptp_clk, - output wire mac_6_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_6_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_6_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_6_rx_axis_tkeep, - output wire mac_6_rx_axis_tvalid, - output wire mac_6_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_6_rx_axis_tuser, - - output wire mac_6_rx_status, - output wire mac_6_rx_lfc_req, - output wire [7:0] mac_6_rx_pfc_req, - - output wire mac_7_tx_clk, - output wire mac_7_tx_rst, - - output wire mac_7_tx_ptp_clk, - output wire mac_7_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_7_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_7_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_7_tx_ptp_ts_tag, - output wire mac_7_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_7_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_7_tx_axis_tkeep, - input wire mac_7_tx_axis_tvalid, - output wire mac_7_tx_axis_tready, - input wire mac_7_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_7_tx_axis_tuser, - - output wire mac_7_tx_status, - input wire mac_7_tx_lfc_req, - input wire [7:0] mac_7_tx_pfc_req, - - output wire mac_7_rx_clk, - output wire mac_7_rx_rst, - - output wire mac_7_rx_ptp_clk, - output wire mac_7_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_7_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_7_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_7_rx_axis_tkeep, - output wire mac_7_rx_axis_tvalid, - output wire mac_7_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_7_rx_axis_tuser, - - output wire mac_7_rx_status, - output wire mac_7_rx_lfc_req, - output wire [7:0] mac_7_rx_pfc_req, - - output wire mac_8_tx_clk, - output wire mac_8_tx_rst, - - output wire mac_8_tx_ptp_clk, - output wire mac_8_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_8_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_8_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_8_tx_ptp_ts_tag, - output wire mac_8_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_8_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_8_tx_axis_tkeep, - input wire mac_8_tx_axis_tvalid, - output wire mac_8_tx_axis_tready, - input wire mac_8_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_8_tx_axis_tuser, - - output wire mac_8_tx_status, - input wire mac_8_tx_lfc_req, - input wire [7:0] mac_8_tx_pfc_req, - - output wire mac_8_rx_clk, - output wire mac_8_rx_rst, - - output wire mac_8_rx_ptp_clk, - output wire mac_8_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_8_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_8_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_8_rx_axis_tkeep, - output wire mac_8_rx_axis_tvalid, - output wire mac_8_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_8_rx_axis_tuser, - - output wire mac_8_rx_status, - output wire mac_8_rx_lfc_req, - output wire [7:0] mac_8_rx_pfc_req + input wire ctrl_clk, + input wire ctrl_rst, + + output wire [7:0] tx_serial_data_p, + output wire [7:0] tx_serial_data_n, + input wire [7:0] rx_serial_data_p, + input wire [7:0] rx_serial_data_n, + input wire ref_clk, + input wire ptp_sample_clk, + + output wire [N_CH-1:0] mac_tx_clk, + output wire [N_CH-1:0] mac_tx_rst, + + output wire [N_CH-1:0] mac_tx_ptp_clk, + output wire [N_CH-1:0] mac_tx_ptp_rst, + input wire [N_CH*PTP_TS_WIDTH-1:0] mac_tx_ptp_time, + + output wire [N_CH*PTP_TS_WIDTH-1:0] mac_tx_ptp_ts, + output wire [N_CH*PTP_TAG_WIDTH-1:0] mac_tx_ptp_ts_tag, + output wire [N_CH-1:0] mac_tx_ptp_ts_valid, + + input wire [N_CH*DATA_WIDTH-1:0] mac_tx_axis_tdata, + input wire [N_CH*KEEP_WIDTH-1:0] mac_tx_axis_tkeep, + input wire [N_CH-1:0] mac_tx_axis_tvalid, + output wire [N_CH-1:0] mac_tx_axis_tready, + input wire [N_CH-1:0] mac_tx_axis_tlast, + input wire [N_CH*TX_USER_WIDTH-1:0] mac_tx_axis_tuser, + + output wire [N_CH*1-1:0] mac_tx_status, + input wire [N_CH*1-1:0] mac_tx_lfc_req, + input wire [N_CH*8-1:0] mac_tx_pfc_req, + + output wire [N_CH-1:0] mac_rx_clk, + output wire [N_CH-1:0] mac_rx_rst, + + output wire [N_CH-1:0] mac_rx_ptp_clk, + output wire [N_CH-1:0] mac_rx_ptp_rst, + input wire [N_CH*PTP_TS_WIDTH-1:0] mac_rx_ptp_time, + + output wire [N_CH*DATA_WIDTH-1:0] mac_rx_axis_tdata, + output wire [N_CH*KEEP_WIDTH-1:0] mac_rx_axis_tkeep, + output wire [N_CH-1:0] mac_rx_axis_tvalid, + output wire [N_CH-1:0] mac_rx_axis_tlast, + output wire [N_CH*RX_USER_WIDTH-1:0] mac_rx_axis_tuser, + + output wire [N_CH*1-1:0] mac_rx_status, + output wire [N_CH*1-1:0] mac_rx_lfc_req, + output wire [N_CH*8-1:0] mac_rx_pfc_req ); -parameter N_CH = 8; - wire [11:0] mac_pll_clk_d64; wire [11:0] mac_pll_clk_d66; wire [11:0] mac_rec_clk_d64; @@ -374,16 +100,6 @@ wire [11:0] mac_rec_clk_d66; wire [N_CH-1:0] mac_tx_pll_locked; -wire [N_CH-1:0] mac_rx_clk; -wire [N_CH-1:0] mac_rx_rst; -wire [N_CH-1:0] mac_tx_clk; -wire [N_CH-1:0] mac_tx_rst; - -wire [N_CH-1:0] mac_rx_ptp_clk; -wire [N_CH-1:0] mac_rx_ptp_rst; -wire [N_CH-1:0] mac_tx_ptp_clk; -wire [N_CH-1:0] mac_tx_ptp_rst; - wire [N_CH*19-1:0] xcvr_reconfig_address; wire [N_CH-1:0] xcvr_reconfig_read; wire [N_CH-1:0] xcvr_reconfig_write; @@ -857,19 +573,6 @@ end endgenerate -wire [N_CH*DATA_WIDTH-1:0] mac_rx_axis_tdata; -wire [N_CH*KEEP_WIDTH-1:0] mac_rx_axis_tkeep; -wire [N_CH-1:0] mac_rx_axis_tvalid; -wire [N_CH-1:0] mac_rx_axis_tlast; -wire [N_CH*RX_USER_WIDTH-1:0] mac_rx_axis_tuser; - -wire [N_CH*DATA_WIDTH-1:0] mac_tx_axis_tdata; -wire [N_CH*KEEP_WIDTH-1:0] mac_tx_axis_tkeep; -wire [N_CH-1:0] mac_tx_axis_tvalid; -wire [N_CH-1:0] mac_tx_axis_tready; -wire [N_CH-1:0] mac_tx_axis_tlast; -wire [N_CH*TX_USER_WIDTH-1:0] mac_tx_axis_tuser; - assign mac_tx_clk[3:0] = {4{mac_pll_clk_d64[4]}}; assign mac_rx_clk[3:0] = mac_tx_clk[3:0]; @@ -882,317 +585,20 @@ assign mac_rx_clk[7:4] = mac_tx_clk[7:4]; assign mac_tx_ptp_clk[7:4] = mac_pll_clk_d66[9:6]; assign mac_rx_ptp_clk[7:4] = mac_rec_clk_d66[9:6]; -assign mac_1_tx_clk = mac_tx_clk[0]; -assign mac_1_tx_rst = mac_tx_rst[0]; +assign mac_ptp_tx_tod = mac_tx_ptp_time; +assign mac_ptp_rx_tod = mac_rx_ptp_time; -assign mac_1_tx_ptp_clk = mac_tx_ptp_clk[0]; -assign mac_1_tx_ptp_rst = mac_tx_ptp_rst[0]; -assign mac_ptp_tx_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_tx_ptp_time; +assign mac_tx_ptp_ts = mac_ptp_ets; +assign mac_tx_ptp_ts_tag = mac_ptp_ets_fp; +assign mac_tx_ptp_ts_valid = mac_ptp_ets_valid; -assign mac_1_tx_ptp_ts = mac_ptp_ets[0*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_1_tx_ptp_ts_tag = mac_ptp_ets_fp[0*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_1_tx_ptp_ts_valid = mac_ptp_ets_valid[0]; +assign mac_tx_status = mac_tx_lanes_stable; +assign mac_tx_pause = mac_tx_lfc_req; +assign mac_tx_pfc = mac_tx_pfc_req; -assign mac_tx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH] = mac_1_tx_axis_tdata; -assign mac_tx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH] = mac_1_tx_axis_tkeep; -assign mac_tx_axis_tvalid[0] = mac_1_tx_axis_tvalid; -assign mac_1_tx_axis_tready = mac_tx_axis_tready[0]; -assign mac_tx_axis_tlast[0] = mac_1_tx_axis_tlast; -assign mac_tx_axis_tuser[0*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_1_tx_axis_tuser; - -assign mac_1_tx_status = mac_tx_lanes_stable[0*1 +: 1]; -assign mac_tx_pause[0*1 +: 1] = mac_1_tx_lfc_req; -assign mac_tx_pfc[0*8 +: 8] = mac_1_tx_pfc_req; - -assign mac_1_rx_clk = mac_rx_clk[0]; -assign mac_1_rx_rst = mac_rx_rst[0]; - -assign mac_1_rx_ptp_clk = mac_rx_ptp_clk[0]; -assign mac_1_rx_ptp_rst = mac_rx_ptp_rst[0]; -assign mac_ptp_rx_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_rx_ptp_time; - -assign mac_1_rx_axis_tdata = mac_rx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH]; -assign mac_1_rx_axis_tkeep = mac_rx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_1_rx_axis_tvalid = mac_rx_axis_tvalid[0]; -assign mac_1_rx_axis_tlast = mac_rx_axis_tlast[0]; -assign mac_1_rx_axis_tuser = mac_rx_axis_tuser[0*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_1_rx_status = mac_rx_pcs_ready[0*1 +: 1]; -assign mac_1_rx_lfc_req = mac_rx_pause[0*1 +: 1]; -assign mac_1_rx_pfc_req = mac_rx_pfc[0*8 +: 8]; - -assign mac_2_tx_clk = mac_tx_clk[1]; -assign mac_2_tx_rst = mac_tx_rst[1]; - -assign mac_2_tx_ptp_clk = mac_tx_ptp_clk[1]; -assign mac_2_tx_ptp_rst = mac_tx_ptp_rst[1]; -assign mac_ptp_tx_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_tx_ptp_time; - -assign mac_2_tx_ptp_ts = mac_ptp_ets[1*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_2_tx_ptp_ts_tag = mac_ptp_ets_fp[1*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_2_tx_ptp_ts_valid = mac_ptp_ets_valid[1]; - -assign mac_tx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH] = mac_2_tx_axis_tdata; -assign mac_tx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH] = mac_2_tx_axis_tkeep; -assign mac_tx_axis_tvalid[1] = mac_2_tx_axis_tvalid; -assign mac_2_tx_axis_tready = mac_tx_axis_tready[1]; -assign mac_tx_axis_tlast[1] = mac_2_tx_axis_tlast; -assign mac_tx_axis_tuser[1*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_2_tx_axis_tuser; - -assign mac_2_tx_status = mac_tx_lanes_stable[1*1 +: 1]; -assign mac_tx_pause[1*1 +: 1] = mac_2_tx_lfc_req; -assign mac_tx_pfc[1*8 +: 8] = mac_2_tx_pfc_req; - -assign mac_2_rx_clk = mac_rx_clk[1]; -assign mac_2_rx_rst = mac_rx_rst[1]; - -assign mac_2_rx_ptp_clk = mac_rx_ptp_clk[1]; -assign mac_2_rx_ptp_rst = mac_rx_ptp_rst[1]; -assign mac_ptp_rx_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_rx_ptp_time; - -assign mac_2_rx_axis_tdata = mac_rx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH]; -assign mac_2_rx_axis_tkeep = mac_rx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_2_rx_axis_tvalid = mac_rx_axis_tvalid[1]; -assign mac_2_rx_axis_tlast = mac_rx_axis_tlast[1]; -assign mac_2_rx_axis_tuser = mac_rx_axis_tuser[1*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_2_rx_status = mac_rx_pcs_ready[1*1 +: 1]; -assign mac_2_rx_lfc_req = mac_rx_pause[1*1 +: 1]; -assign mac_2_rx_pfc_req = mac_rx_pfc[1*8 +: 8]; - -assign mac_3_tx_clk = mac_tx_clk[2]; -assign mac_3_tx_rst = mac_tx_rst[2]; - -assign mac_3_tx_ptp_clk = mac_tx_ptp_clk[2]; -assign mac_3_tx_ptp_rst = mac_tx_ptp_rst[2]; -assign mac_ptp_tx_tod[2*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_3_tx_ptp_time; - -assign mac_3_tx_ptp_ts = mac_ptp_ets[2*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_3_tx_ptp_ts_tag = mac_ptp_ets_fp[2*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_3_tx_ptp_ts_valid = mac_ptp_ets_valid[2]; - -assign mac_tx_axis_tdata[2*DATA_WIDTH +: DATA_WIDTH] = mac_3_tx_axis_tdata; -assign mac_tx_axis_tkeep[2*KEEP_WIDTH +: KEEP_WIDTH] = mac_3_tx_axis_tkeep; -assign mac_tx_axis_tvalid[2] = mac_3_tx_axis_tvalid; -assign mac_3_tx_axis_tready = mac_tx_axis_tready[2]; -assign mac_tx_axis_tlast[2] = mac_3_tx_axis_tlast; -assign mac_tx_axis_tuser[2*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_3_tx_axis_tuser; - -assign mac_3_tx_status = mac_tx_lanes_stable[2*1 +: 1]; -assign mac_tx_pause[2*1 +: 1] = mac_3_tx_lfc_req; -assign mac_tx_pfc[2*8 +: 8] = mac_3_tx_pfc_req; - -assign mac_3_rx_clk = mac_rx_clk[2]; -assign mac_3_rx_rst = mac_rx_rst[2]; - -assign mac_3_rx_ptp_clk = mac_rx_ptp_clk[2]; -assign mac_3_rx_ptp_rst = mac_rx_ptp_rst[2]; -assign mac_ptp_rx_tod[2*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_3_rx_ptp_time; - -assign mac_3_rx_axis_tdata = mac_rx_axis_tdata[2*DATA_WIDTH +: DATA_WIDTH]; -assign mac_3_rx_axis_tkeep = mac_rx_axis_tkeep[2*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_3_rx_axis_tvalid = mac_rx_axis_tvalid[2]; -assign mac_3_rx_axis_tlast = mac_rx_axis_tlast[2]; -assign mac_3_rx_axis_tuser = mac_rx_axis_tuser[2*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_3_rx_status = mac_rx_pcs_ready[2*1 +: 1]; -assign mac_3_rx_lfc_req = mac_rx_pause[2*1 +: 1]; -assign mac_3_rx_pfc_req = mac_rx_pfc[2*8 +: 8]; - -assign mac_4_tx_clk = mac_tx_clk[3]; -assign mac_4_tx_rst = mac_tx_rst[3]; - -assign mac_4_tx_ptp_clk = mac_tx_ptp_clk[3]; -assign mac_4_tx_ptp_rst = mac_tx_ptp_rst[3]; -assign mac_ptp_tx_tod[3*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_4_tx_ptp_time; - -assign mac_4_tx_ptp_ts = mac_ptp_ets[3*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_4_tx_ptp_ts_tag = mac_ptp_ets_fp[3*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_4_tx_ptp_ts_valid = mac_ptp_ets_valid[3]; - -assign mac_tx_axis_tdata[3*DATA_WIDTH +: DATA_WIDTH] = mac_4_tx_axis_tdata; -assign mac_tx_axis_tkeep[3*KEEP_WIDTH +: KEEP_WIDTH] = mac_4_tx_axis_tkeep; -assign mac_tx_axis_tvalid[3] = mac_4_tx_axis_tvalid; -assign mac_4_tx_axis_tready = mac_tx_axis_tready[3]; -assign mac_tx_axis_tlast[3] = mac_4_tx_axis_tlast; -assign mac_tx_axis_tuser[3*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_4_tx_axis_tuser; - -assign mac_4_tx_status = mac_tx_lanes_stable[3*1 +: 1]; -assign mac_tx_pause[3*1 +: 1] = mac_4_tx_lfc_req; -assign mac_tx_pfc[3*8 +: 8] = mac_4_tx_pfc_req; - -assign mac_4_rx_clk = mac_rx_clk[3]; -assign mac_4_rx_rst = mac_rx_rst[3]; - -assign mac_4_rx_ptp_clk = mac_rx_ptp_clk[3]; -assign mac_4_rx_ptp_rst = mac_rx_ptp_rst[3]; -assign mac_ptp_rx_tod[3*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_4_rx_ptp_time; - -assign mac_4_rx_axis_tdata = mac_rx_axis_tdata[3*DATA_WIDTH +: DATA_WIDTH]; -assign mac_4_rx_axis_tkeep = mac_rx_axis_tkeep[3*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_4_rx_axis_tvalid = mac_rx_axis_tvalid[3]; -assign mac_4_rx_axis_tlast = mac_rx_axis_tlast[3]; -assign mac_4_rx_axis_tuser = mac_rx_axis_tuser[3*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_4_rx_status = mac_rx_pcs_ready[3*1 +: 1]; -assign mac_4_rx_lfc_req = mac_rx_pause[3*1 +: 1]; -assign mac_4_rx_pfc_req = mac_rx_pfc[3*8 +: 8]; - -assign mac_5_tx_clk = mac_tx_clk[4]; -assign mac_5_tx_rst = mac_tx_rst[4]; - -assign mac_5_tx_ptp_clk = mac_tx_ptp_clk[4]; -assign mac_5_tx_ptp_rst = mac_tx_ptp_rst[4]; -assign mac_ptp_tx_tod[4*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_5_tx_ptp_time; - -assign mac_5_tx_ptp_ts = mac_ptp_ets[4*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_5_tx_ptp_ts_tag = mac_ptp_ets_fp[4*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_5_tx_ptp_ts_valid = mac_ptp_ets_valid[4]; - -assign mac_tx_axis_tdata[4*DATA_WIDTH +: DATA_WIDTH] = mac_5_tx_axis_tdata; -assign mac_tx_axis_tkeep[4*KEEP_WIDTH +: KEEP_WIDTH] = mac_5_tx_axis_tkeep; -assign mac_tx_axis_tvalid[4] = mac_5_tx_axis_tvalid; -assign mac_5_tx_axis_tready = mac_tx_axis_tready[4]; -assign mac_tx_axis_tlast[4] = mac_5_tx_axis_tlast; -assign mac_tx_axis_tuser[4*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_5_tx_axis_tuser; - -assign mac_5_tx_status = mac_tx_lanes_stable[4*1 +: 1]; -assign mac_tx_pause[4*1 +: 1] = mac_5_tx_lfc_req; -assign mac_tx_pfc[4*8 +: 8] = mac_5_tx_pfc_req; - -assign mac_5_rx_clk = mac_rx_clk[4]; -assign mac_5_rx_rst = mac_rx_rst[4]; - -assign mac_5_rx_ptp_clk = mac_rx_ptp_clk[4]; -assign mac_5_rx_ptp_rst = mac_rx_ptp_rst[4]; -assign mac_ptp_rx_tod[4*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_5_rx_ptp_time; - -assign mac_5_rx_axis_tdata = mac_rx_axis_tdata[4*DATA_WIDTH +: DATA_WIDTH]; -assign mac_5_rx_axis_tkeep = mac_rx_axis_tkeep[4*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_5_rx_axis_tvalid = mac_rx_axis_tvalid[4]; -assign mac_5_rx_axis_tlast = mac_rx_axis_tlast[4]; -assign mac_5_rx_axis_tuser = mac_rx_axis_tuser[4*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_5_rx_status = mac_rx_pcs_ready[4*1 +: 1]; -assign mac_5_rx_lfc_req = mac_rx_pause[4*1 +: 1]; -assign mac_5_rx_pfc_req = mac_rx_pfc[4*8 +: 8]; - -assign mac_6_tx_clk = mac_tx_clk[5]; -assign mac_6_tx_rst = mac_tx_rst[5]; - -assign mac_6_tx_ptp_clk = mac_tx_ptp_clk[5]; -assign mac_6_tx_ptp_rst = mac_tx_ptp_rst[5]; -assign mac_ptp_tx_tod[5*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_6_tx_ptp_time; - -assign mac_6_tx_ptp_ts = mac_ptp_ets[5*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_6_tx_ptp_ts_tag = mac_ptp_ets_fp[5*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_6_tx_ptp_ts_valid = mac_ptp_ets_valid[5]; - -assign mac_tx_axis_tdata[5*DATA_WIDTH +: DATA_WIDTH] = mac_6_tx_axis_tdata; -assign mac_tx_axis_tkeep[5*KEEP_WIDTH +: KEEP_WIDTH] = mac_6_tx_axis_tkeep; -assign mac_tx_axis_tvalid[5] = mac_6_tx_axis_tvalid; -assign mac_6_tx_axis_tready = mac_tx_axis_tready[5]; -assign mac_tx_axis_tlast[5] = mac_6_tx_axis_tlast; -assign mac_tx_axis_tuser[5*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_6_tx_axis_tuser; - -assign mac_6_tx_status = mac_tx_lanes_stable[5*1 +: 1]; -assign mac_tx_pause[5*1 +: 1] = mac_6_tx_lfc_req; -assign mac_tx_pfc[5*8 +: 8] = mac_6_tx_pfc_req; - -assign mac_6_rx_clk = mac_rx_clk[5]; -assign mac_6_rx_rst = mac_rx_rst[5]; - -assign mac_6_rx_ptp_clk = mac_rx_ptp_clk[5]; -assign mac_6_rx_ptp_rst = mac_rx_ptp_rst[5]; -assign mac_ptp_rx_tod[5*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_6_rx_ptp_time; - -assign mac_6_rx_axis_tdata = mac_rx_axis_tdata[5*DATA_WIDTH +: DATA_WIDTH]; -assign mac_6_rx_axis_tkeep = mac_rx_axis_tkeep[5*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_6_rx_axis_tvalid = mac_rx_axis_tvalid[5]; -assign mac_6_rx_axis_tlast = mac_rx_axis_tlast[5]; -assign mac_6_rx_axis_tuser = mac_rx_axis_tuser[5*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_6_rx_status = mac_rx_pcs_ready[5*1 +: 1]; -assign mac_6_rx_lfc_req = mac_rx_pause[5*1 +: 1]; -assign mac_6_rx_pfc_req = mac_rx_pfc[5*8 +: 8]; - -assign mac_7_tx_clk = mac_tx_clk[6]; -assign mac_7_tx_rst = mac_tx_rst[6]; - -assign mac_7_tx_ptp_clk = mac_tx_ptp_clk[6]; -assign mac_7_tx_ptp_rst = mac_tx_ptp_rst[6]; -assign mac_ptp_tx_tod[6*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_7_tx_ptp_time; - -assign mac_7_tx_ptp_ts = mac_ptp_ets[6*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_7_tx_ptp_ts_tag = mac_ptp_ets_fp[6*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_7_tx_ptp_ts_valid = mac_ptp_ets_valid[6]; - -assign mac_tx_axis_tdata[6*DATA_WIDTH +: DATA_WIDTH] = mac_7_tx_axis_tdata; -assign mac_tx_axis_tkeep[6*KEEP_WIDTH +: KEEP_WIDTH] = mac_7_tx_axis_tkeep; -assign mac_tx_axis_tvalid[6] = mac_7_tx_axis_tvalid; -assign mac_7_tx_axis_tready = mac_tx_axis_tready[6]; -assign mac_tx_axis_tlast[6] = mac_7_tx_axis_tlast; -assign mac_tx_axis_tuser[6*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_7_tx_axis_tuser; - -assign mac_7_tx_status = mac_tx_lanes_stable[6*1 +: 1]; -assign mac_tx_pause[6*1 +: 1] = mac_7_tx_lfc_req; -assign mac_tx_pfc[6*8 +: 8] = mac_7_tx_pfc_req; - -assign mac_7_rx_clk = mac_rx_clk[6]; -assign mac_7_rx_rst = mac_rx_rst[6]; - -assign mac_7_rx_ptp_clk = mac_rx_ptp_clk[6]; -assign mac_7_rx_ptp_rst = mac_rx_ptp_rst[6]; -assign mac_ptp_rx_tod[6*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_7_rx_ptp_time; - -assign mac_7_rx_axis_tdata = mac_rx_axis_tdata[6*DATA_WIDTH +: DATA_WIDTH]; -assign mac_7_rx_axis_tkeep = mac_rx_axis_tkeep[6*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_7_rx_axis_tvalid = mac_rx_axis_tvalid[6]; -assign mac_7_rx_axis_tlast = mac_rx_axis_tlast[6]; -assign mac_7_rx_axis_tuser = mac_rx_axis_tuser[6*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_7_rx_status = mac_rx_pcs_ready[6*1 +: 1]; -assign mac_7_rx_lfc_req = mac_rx_pause[6*1 +: 1]; -assign mac_7_rx_pfc_req = mac_rx_pfc[6*8 +: 8]; - -assign mac_8_tx_clk = mac_tx_clk[7]; -assign mac_8_tx_rst = mac_tx_rst[7]; - -assign mac_8_tx_ptp_clk = mac_tx_ptp_clk[7]; -assign mac_8_tx_ptp_rst = mac_tx_ptp_rst[7]; -assign mac_ptp_tx_tod[7*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_8_tx_ptp_time; - -assign mac_8_tx_ptp_ts = mac_ptp_ets[7*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_8_tx_ptp_ts_tag = mac_ptp_ets_fp[7*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_8_tx_ptp_ts_valid = mac_ptp_ets_valid[7]; - -assign mac_tx_axis_tdata[7*DATA_WIDTH +: DATA_WIDTH] = mac_8_tx_axis_tdata; -assign mac_tx_axis_tkeep[7*KEEP_WIDTH +: KEEP_WIDTH] = mac_8_tx_axis_tkeep; -assign mac_tx_axis_tvalid[7] = mac_8_tx_axis_tvalid; -assign mac_8_tx_axis_tready = mac_tx_axis_tready[7]; -assign mac_tx_axis_tlast[7] = mac_8_tx_axis_tlast; -assign mac_tx_axis_tuser[7*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_8_tx_axis_tuser; - -assign mac_8_tx_status = mac_tx_lanes_stable[7*1 +: 1]; -assign mac_tx_pause[7*1 +: 1] = mac_8_tx_lfc_req; -assign mac_tx_pfc[7*8 +: 8] = mac_8_tx_pfc_req; - -assign mac_8_rx_clk = mac_rx_clk[7]; -assign mac_8_rx_rst = mac_rx_rst[7]; - -assign mac_8_rx_ptp_clk = mac_rx_ptp_clk[7]; -assign mac_8_rx_ptp_rst = mac_rx_ptp_rst[7]; -assign mac_ptp_rx_tod[7*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_8_rx_ptp_time; - -assign mac_8_rx_axis_tdata = mac_rx_axis_tdata[7*DATA_WIDTH +: DATA_WIDTH]; -assign mac_8_rx_axis_tkeep = mac_rx_axis_tkeep[7*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_8_rx_axis_tvalid = mac_rx_axis_tvalid[7]; -assign mac_8_rx_axis_tlast = mac_rx_axis_tlast[7]; -assign mac_8_rx_axis_tuser = mac_rx_axis_tuser[7*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_8_rx_status = mac_rx_pcs_ready[7*1 +: 1]; -assign mac_8_rx_lfc_req = mac_rx_pause[7*1 +: 1]; -assign mac_8_rx_pfc_req = mac_rx_pfc[7*8 +: 8]; +assign mac_rx_status = mac_rx_pcs_ready; +assign mac_rx_lfc_req = mac_rx_pause; +assign mac_rx_pfc_req = mac_rx_pfc; generate diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v index e434d59d8..86ffff5fa 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v @@ -24,6 +24,10 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter MAC_100G = 1, + parameter MAC_RSFEC = 1, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -448,7 +452,7 @@ pcie pcie_hip_inst ( // QSFP-DD interfaces localparam QSFPDD_CNT = 2; -localparam CH_CNT = QSFPDD_CNT*2; +localparam CH_CNT = MAC_100G ? QSFPDD_CNT*2 : QSFPDD_CNT*8; wire [CH_CNT-1:0] qsfpdd_mac_tx_clk; wire [CH_CNT-1:0] qsfpdd_mac_tx_rst; @@ -460,7 +464,10 @@ wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready; wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast; wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser; +wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_clk; +wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_rst; wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time; + wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts; wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag; wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid; @@ -478,117 +485,269 @@ wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid; wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast; wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser; +wire [CH_CNT-1:0] qsfpdd_mac_rx_ptp_clk; +wire [CH_CNT-1:0] qsfpdd_mac_rx_ptp_rst; wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time; wire [CH_CNT-1:0] qsfpdd_mac_rx_status; wire [CH_CNT-1:0] qsfpdd_mac_rx_lfc_req; wire [CH_CNT*8-1:0] qsfpdd_mac_rx_pfc_req; -// QSFP-DD A -assign qsfpdd_mac_rx_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2]; -assign qsfpdd_mac_rx_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2]; +generate -eth_mac_dual_wrapper #( - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) -) -qsfpdda_mac_inst ( - .ctrl_clk(clk_100mhz), - .ctrl_rst(rst_100mhz), +if (MAC_100G) begin - .tx_serial_data_p({qsfpdda_tx_p[7], qsfpdda_tx_p[5], qsfpdda_tx_p[6], qsfpdda_tx_p[4], qsfpdda_tx_p[3], qsfpdda_tx_p[1], qsfpdda_tx_p[2], qsfpdda_tx_p[0]}), - // .tx_serial_data_n({qsfpdda_tx_n[7], qsfpdda_tx_n[5], qsfpdda_tx_n[6], qsfpdda_tx_n[4], qsfpdda_tx_n[3], qsfpdda_tx_n[1], qsfpdda_tx_n[2], qsfpdda_tx_n[0]}), - .rx_serial_data_p({qsfpdda_rx_p[7], qsfpdda_rx_p[5], qsfpdda_rx_p[6], qsfpdda_rx_p[4], qsfpdda_rx_p[3], qsfpdda_rx_p[1], qsfpdda_rx_p[2], qsfpdda_rx_p[0]}), - // .rx_serial_data_n({qsfpdda_rx_n[7], qsfpdda_rx_n[5], qsfpdda_rx_n[6], qsfpdda_rx_n[4], qsfpdda_rx_n[3], qsfpdda_rx_n[1], qsfpdda_rx_n[2], qsfpdda_rx_n[0]}), - .ref_clk(qsfpddb_refclk_p), + // QSFP-DD A + assign qsfpdd_mac_tx_ptp_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2]; + assign qsfpdd_mac_tx_ptp_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2]; + assign qsfpdd_mac_rx_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2]; + assign qsfpdd_mac_rx_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2]; + assign qsfpdd_mac_rx_ptp_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2]; + assign qsfpdd_mac_rx_ptp_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2]; - .mac_clk(qsfpdd_mac_tx_clk[0*2 +: 2*1]), - .mac_rst(qsfpdd_mac_tx_rst[0*2 +: 2*1]), + eth_mac_dual_wrapper #( + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) + ) + qsfpdda_mac_inst ( + .ctrl_clk(clk_100mhz), + .ctrl_rst(rst_100mhz), - .mac_ptp_time(qsfpdd_mac_tx_ptp_time[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]), + .tx_serial_data_p({qsfpdda_tx_p[7], qsfpdda_tx_p[5], qsfpdda_tx_p[6], qsfpdda_tx_p[4], qsfpdda_tx_p[3], qsfpdda_tx_p[1], qsfpdda_tx_p[2], qsfpdda_tx_p[0]}), + // .tx_serial_data_n({qsfpdda_tx_n[7], qsfpdda_tx_n[5], qsfpdda_tx_n[6], qsfpdda_tx_n[4], qsfpdda_tx_n[3], qsfpdda_tx_n[1], qsfpdda_tx_n[2], qsfpdda_tx_n[0]}), + .rx_serial_data_p({qsfpdda_rx_p[7], qsfpdda_rx_p[5], qsfpdda_rx_p[6], qsfpdda_rx_p[4], qsfpdda_rx_p[3], qsfpdda_rx_p[1], qsfpdda_rx_p[2], qsfpdda_rx_p[0]}), + // .rx_serial_data_n({qsfpdda_rx_n[7], qsfpdda_rx_n[5], qsfpdda_rx_n[6], qsfpdda_rx_n[4], qsfpdda_rx_n[3], qsfpdda_rx_n[1], qsfpdda_rx_n[2], qsfpdda_rx_n[0]}), + .ref_clk(qsfpddb_refclk_p), - .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]), - .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[0*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]), - .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[0*2 +: 2*1]), + .mac_clk(qsfpdd_mac_tx_clk[0*2 +: 2*1]), + .mac_rst(qsfpdd_mac_tx_rst[0*2 +: 2*1]), - .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]), - .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]), - .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[0*2 +: 2*1]), - .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[0*2 +: 2*1]), - .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[0*2 +: 2*1]), - .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[0*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]), + .mac_ptp_time(qsfpdd_mac_tx_ptp_time[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]), - .mac_tx_status(qsfpdd_mac_tx_status[0*2 +: 2*1]), - .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[0*2 +: 2*1]), - .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[0*2*8 +: 2*8]), + .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]), + .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[0*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]), + .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[0*2 +: 2*1]), - .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]), - .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]), - .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[0*2 +: 2*1]), - .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[0*2 +: 2*1]), - .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[0*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]), + .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]), + .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]), + .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[0*2 +: 2*1]), + .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[0*2 +: 2*1]), + .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[0*2 +: 2*1]), + .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[0*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]), - .mac_rx_status(qsfpdd_mac_rx_status[0*2 +: 2*1]), - .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[0*2 +: 2*1]), - .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[0*2*8 +: 2*8]) -); + .mac_tx_status(qsfpdd_mac_tx_status[0*2 +: 2*1]), + .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[0*2 +: 2*1]), + .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[0*2*8 +: 2*8]), -// QSFP-DD B -assign qsfpdd_mac_rx_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2]; -assign qsfpdd_mac_rx_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2]; + .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]), + .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]), + .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[0*2 +: 2*1]), + .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[0*2 +: 2*1]), + .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[0*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]), -eth_mac_dual_wrapper #( - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) -) -qsfpddb_mac_inst ( - .ctrl_clk(clk_100mhz), - .ctrl_rst(rst_100mhz), + .mac_rx_status(qsfpdd_mac_rx_status[0*2 +: 2*1]), + .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[0*2 +: 2*1]), + .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[0*2*8 +: 2*8]) + ); - .tx_serial_data_p({qsfpddb_tx_p[7], qsfpddb_tx_p[5], qsfpddb_tx_p[6], qsfpddb_tx_p[4], qsfpddb_tx_p[3], qsfpddb_tx_p[1], qsfpddb_tx_p[2], qsfpddb_tx_p[0]}), - // .tx_serial_data_n({qsfpddb_tx_n[7], qsfpddb_tx_n[5], qsfpddb_tx_n[6], qsfpddb_tx_n[4], qsfpddb_tx_n[3], qsfpddb_tx_n[1], qsfpddb_tx_n[2], qsfpddb_tx_n[0]}), - .rx_serial_data_p({qsfpddb_rx_p[7], qsfpddb_rx_p[5], qsfpddb_rx_p[6], qsfpddb_rx_p[4], qsfpddb_rx_p[3], qsfpddb_rx_p[1], qsfpddb_rx_p[2], qsfpddb_rx_p[0]}), - // .rx_serial_data_n({qsfpddb_rx_n[7], qsfpddb_rx_n[5], qsfpddb_rx_n[6], qsfpddb_rx_n[4], qsfpddb_rx_n[3], qsfpddb_rx_n[1], qsfpddb_rx_n[2], qsfpddb_rx_n[0]}), - .ref_clk(qsfpddb_refclk_p), + // QSFP-DD B + assign qsfpdd_mac_tx_ptp_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2]; + assign qsfpdd_mac_tx_ptp_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2]; + assign qsfpdd_mac_rx_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2]; + assign qsfpdd_mac_rx_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2]; + assign qsfpdd_mac_rx_ptp_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2]; + assign qsfpdd_mac_rx_ptp_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2]; - .mac_clk(qsfpdd_mac_tx_clk[1*2 +: 2*1]), - .mac_rst(qsfpdd_mac_tx_rst[1*2 +: 2*1]), + eth_mac_dual_wrapper #( + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) + ) + qsfpddb_mac_inst ( + .ctrl_clk(clk_100mhz), + .ctrl_rst(rst_100mhz), - .mac_ptp_time(qsfpdd_mac_tx_ptp_time[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]), + .tx_serial_data_p({qsfpddb_tx_p[7], qsfpddb_tx_p[5], qsfpddb_tx_p[6], qsfpddb_tx_p[4], qsfpddb_tx_p[3], qsfpddb_tx_p[1], qsfpddb_tx_p[2], qsfpddb_tx_p[0]}), + // .tx_serial_data_n({qsfpddb_tx_n[7], qsfpddb_tx_n[5], qsfpddb_tx_n[6], qsfpddb_tx_n[4], qsfpddb_tx_n[3], qsfpddb_tx_n[1], qsfpddb_tx_n[2], qsfpddb_tx_n[0]}), + .rx_serial_data_p({qsfpddb_rx_p[7], qsfpddb_rx_p[5], qsfpddb_rx_p[6], qsfpddb_rx_p[4], qsfpddb_rx_p[3], qsfpddb_rx_p[1], qsfpddb_rx_p[2], qsfpddb_rx_p[0]}), + // .rx_serial_data_n({qsfpddb_rx_n[7], qsfpddb_rx_n[5], qsfpddb_rx_n[6], qsfpddb_rx_n[4], qsfpddb_rx_n[3], qsfpddb_rx_n[1], qsfpddb_rx_n[2], qsfpddb_rx_n[0]}), + .ref_clk(qsfpddb_refclk_p), - .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]), - .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[1*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]), - .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[1*2 +: 2*1]), + .mac_clk(qsfpdd_mac_tx_clk[1*2 +: 2*1]), + .mac_rst(qsfpdd_mac_tx_rst[1*2 +: 2*1]), - .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]), - .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]), - .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[1*2 +: 2*1]), - .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[1*2 +: 2*1]), - .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[1*2 +: 2*1]), - .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[1*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]), + .mac_ptp_time(qsfpdd_mac_tx_ptp_time[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]), - .mac_tx_status(qsfpdd_mac_tx_status[1*2 +: 2*1]), - .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[1*2 +: 2*1]), - .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[1*2*8 +: 2*8]), + .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]), + .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[1*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]), + .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[1*2 +: 2*1]), - .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]), - .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]), - .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[1*2 +: 2*1]), - .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[1*2 +: 2*1]), - .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[1*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]), + .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]), + .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]), + .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[1*2 +: 2*1]), + .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[1*2 +: 2*1]), + .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[1*2 +: 2*1]), + .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[1*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]), - .mac_rx_status(qsfpdd_mac_rx_status[1*2 +: 2*1]), - .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[1*2 +: 2*1]), - .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[1*2*8 +: 2*8]) -); + .mac_tx_status(qsfpdd_mac_tx_status[1*2 +: 2*1]), + .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[1*2 +: 2*1]), + .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[1*2*8 +: 2*8]), + + .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]), + .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]), + .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[1*2 +: 2*1]), + .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[1*2 +: 2*1]), + .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[1*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]), + + .mac_rx_status(qsfpdd_mac_rx_status[1*2 +: 2*1]), + .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[1*2 +: 2*1]), + .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[1*2*8 +: 2*8]) + ); + +end else begin + + wire etile_iopll_locked; + wire etile_ptp_sample_clk; + + iopll_etile_ptp iopll_etile_ptp_inst ( + .rst (rst_100mhz), + .refclk (clk_100mhz), + .locked (etile_iopll_locked), + .outclk_0 (etile_ptp_sample_clk) + ); + + // QSFP-DD A + eth_mac_dual_quad_wrapper #( + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .MAC_RSFEC(MAC_RSFEC) + ) + qsfpdda_mac_inst ( + .ctrl_clk(clk_100mhz), + .ctrl_rst(rst_100mhz), + + .tx_serial_data_p({qsfpdda_tx_p[7], qsfpdda_tx_p[5], qsfpdda_tx_p[6], qsfpdda_tx_p[4], qsfpdda_tx_p[3], qsfpdda_tx_p[1], qsfpdda_tx_p[2], qsfpdda_tx_p[0]}), + // .tx_serial_data_n({qsfpdda_tx_n[7], qsfpdda_tx_n[5], qsfpdda_tx_n[6], qsfpdda_tx_n[4], qsfpdda_tx_n[3], qsfpdda_tx_n[1], qsfpdda_tx_n[2], qsfpdda_tx_n[0]}), + .rx_serial_data_p({qsfpdda_rx_p[7], qsfpdda_rx_p[5], qsfpdda_rx_p[6], qsfpdda_rx_p[4], qsfpdda_rx_p[3], qsfpdda_rx_p[1], qsfpdda_rx_p[2], qsfpdda_rx_p[0]}), + // .rx_serial_data_n({qsfpdda_rx_n[7], qsfpdda_rx_n[5], qsfpdda_rx_n[6], qsfpdda_rx_n[4], qsfpdda_rx_n[3], qsfpdda_rx_n[1], qsfpdda_rx_n[2], qsfpdda_rx_n[0]}), + .ref_clk(qsfpddb_refclk_p), + .ptp_sample_clk(etile_ptp_sample_clk), + + .mac_tx_clk(qsfpdd_mac_tx_clk[0*8 +: 8*1]), + .mac_tx_rst(qsfpdd_mac_tx_rst[0*8 +: 8*1]), + + .mac_tx_ptp_clk(qsfpdd_mac_tx_ptp_clk[0*8 +: 8*1]), + .mac_tx_ptp_rst(qsfpdd_mac_tx_ptp_rst[0*8 +: 8*1]), + .mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time[0*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]), + + .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[0*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]), + .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[0*8*TX_TAG_WIDTH +: 8*TX_TAG_WIDTH]), + .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[0*8 +: 8*1]), + + .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[0*8*AXIS_ETH_DATA_WIDTH +: 8*AXIS_ETH_DATA_WIDTH]), + .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[0*8*AXIS_ETH_KEEP_WIDTH +: 8*AXIS_ETH_KEEP_WIDTH]), + .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[0*8 +: 8*1]), + .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[0*8 +: 8*1]), + .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[0*8 +: 8*1]), + .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[0*8*AXIS_ETH_TX_USER_WIDTH +: 8*AXIS_ETH_TX_USER_WIDTH]), + + .mac_tx_status(qsfpdd_mac_tx_status[0*8 +: 8*1]), + .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[0*8 +: 8*1]), + .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[0*8*8 +: 8*8]), + + .mac_rx_clk(qsfpdd_mac_rx_clk[0*8 +: 8*1]), + .mac_rx_rst(qsfpdd_mac_rx_rst[0*8 +: 8*1]), + + .mac_rx_ptp_clk(qsfpdd_mac_rx_ptp_clk[0*8 +: 8*1]), + .mac_rx_ptp_rst(qsfpdd_mac_rx_ptp_rst[0*8 +: 8*1]), + .mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time[0*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]), + + .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[0*8*AXIS_ETH_DATA_WIDTH +: 8*AXIS_ETH_DATA_WIDTH]), + .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[0*8*AXIS_ETH_KEEP_WIDTH +: 8*AXIS_ETH_KEEP_WIDTH]), + .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[0*8 +: 8*1]), + .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[0*8 +: 8*1]), + .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[0*8*AXIS_ETH_RX_USER_WIDTH +: 8*AXIS_ETH_RX_USER_WIDTH]), + + .mac_rx_status(qsfpdd_mac_rx_status[0*8 +: 8*1]), + .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[0*8 +: 8*1]), + .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[0*8*8 +: 8*8]) + ); + + // QSFP-DD B + eth_mac_dual_quad_wrapper #( + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .MAC_RSFEC(MAC_RSFEC) + ) + qsfpddb_mac_inst ( + .ctrl_clk(clk_100mhz), + .ctrl_rst(rst_100mhz), + + .tx_serial_data_p({qsfpddb_tx_p[7], qsfpddb_tx_p[5], qsfpddb_tx_p[6], qsfpddb_tx_p[4], qsfpddb_tx_p[3], qsfpddb_tx_p[1], qsfpddb_tx_p[2], qsfpddb_tx_p[0]}), + // .tx_serial_data_n({qsfpddb_tx_n[7], qsfpddb_tx_n[5], qsfpddb_tx_n[6], qsfpddb_tx_n[4], qsfpddb_tx_n[3], qsfpddb_tx_n[1], qsfpddb_tx_n[2], qsfpddb_tx_n[0]}), + .rx_serial_data_p({qsfpddb_rx_p[7], qsfpddb_rx_p[5], qsfpddb_rx_p[6], qsfpddb_rx_p[4], qsfpddb_rx_p[3], qsfpddb_rx_p[1], qsfpddb_rx_p[2], qsfpddb_rx_p[0]}), + // .rx_serial_data_n({qsfpddb_rx_n[7], qsfpddb_rx_n[5], qsfpddb_rx_n[6], qsfpddb_rx_n[4], qsfpddb_rx_n[3], qsfpddb_rx_n[1], qsfpddb_rx_n[2], qsfpddb_rx_n[0]}), + .ref_clk(qsfpddb_refclk_p), + .ptp_sample_clk(etile_ptp_sample_clk), + + .mac_tx_clk(qsfpdd_mac_tx_clk[1*8 +: 8*1]), + .mac_tx_rst(qsfpdd_mac_tx_rst[1*8 +: 8*1]), + + .mac_tx_ptp_clk(qsfpdd_mac_tx_ptp_clk[1*8 +: 8*1]), + .mac_tx_ptp_rst(qsfpdd_mac_tx_ptp_rst[1*8 +: 8*1]), + .mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time[1*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]), + + .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[1*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]), + .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[1*8*TX_TAG_WIDTH +: 8*TX_TAG_WIDTH]), + .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[1*8 +: 8*1]), + + .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[1*8*AXIS_ETH_DATA_WIDTH +: 8*AXIS_ETH_DATA_WIDTH]), + .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[1*8*AXIS_ETH_KEEP_WIDTH +: 8*AXIS_ETH_KEEP_WIDTH]), + .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[1*8 +: 8*1]), + .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[1*8 +: 8*1]), + .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[1*8 +: 8*1]), + .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[1*8*AXIS_ETH_TX_USER_WIDTH +: 8*AXIS_ETH_TX_USER_WIDTH]), + + .mac_tx_status(qsfpdd_mac_tx_status[1*8 +: 8*1]), + .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[1*8 +: 8*1]), + .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[1*8*8 +: 8*8]), + + .mac_rx_clk(qsfpdd_mac_rx_clk[1*8 +: 8*1]), + .mac_rx_rst(qsfpdd_mac_rx_rst[1*8 +: 8*1]), + + .mac_rx_ptp_clk(qsfpdd_mac_rx_ptp_clk[1*8 +: 8*1]), + .mac_rx_ptp_rst(qsfpdd_mac_rx_ptp_rst[1*8 +: 8*1]), + .mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time[1*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]), + + .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[1*8*AXIS_ETH_DATA_WIDTH +: 8*AXIS_ETH_DATA_WIDTH]), + .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[1*8*AXIS_ETH_KEEP_WIDTH +: 8*AXIS_ETH_KEEP_WIDTH]), + .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[1*8 +: 8*1]), + .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[1*8 +: 8*1]), + .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[1*8*AXIS_ETH_RX_USER_WIDTH +: 8*AXIS_ETH_RX_USER_WIDTH]), + + .mac_rx_status(qsfpdd_mac_rx_status[1*8 +: 8*1]), + .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[1*8 +: 8*1]), + .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[1*8*8 +: 8*8]) + ); + +end + +endgenerate wire ptp_clk; wire ptp_rst; @@ -613,6 +772,7 @@ fpga_core #( // Board configuration .QSFPDD_CNT(QSFPDD_CNT), .CH_CNT(CH_CNT), + .PORT_GROUP_SIZE(MAC_100G ? 2 : 8), // Structural configuration .IF_COUNT(IF_COUNT), @@ -630,6 +790,8 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_SEPARATE_TX_CLOCK(MAC_100G ? 0 : 1), + .PTP_SEPARATE_RX_CLOCK(MAC_100G ? 0 : 1), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -805,7 +967,10 @@ core_inst ( .qsfpdd_mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast), .qsfpdd_mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser), + .qsfpdd_mac_tx_ptp_clk(qsfpdd_mac_tx_ptp_clk), + .qsfpdd_mac_tx_ptp_rst(qsfpdd_mac_tx_ptp_rst), .qsfpdd_mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time), + .qsfpdd_mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts), .qsfpdd_mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag), .qsfpdd_mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid), @@ -823,6 +988,8 @@ core_inst ( .qsfpdd_mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast), .qsfpdd_mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser), + .qsfpdd_mac_rx_ptp_clk(qsfpdd_mac_rx_ptp_clk), + .qsfpdd_mac_rx_ptp_rst(qsfpdd_mac_rx_ptp_rst), .qsfpdd_mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time), .qsfpdd_mac_rx_status(qsfpdd_mac_rx_status), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v index 656fb79d3..b751d4736 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v @@ -27,6 +27,7 @@ module fpga_core # // Board configuration parameter QSFPDD_CNT = 2, parameter CH_CNT = QSFPDD_CNT*2, + parameter PORT_GROUP_SIZE = 2, // Structural configuration parameter IF_COUNT = 2, @@ -44,6 +45,8 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_SEPARATE_TX_CLOCK = 0, + parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -152,59 +155,59 @@ module fpga_core # * Clock: 250 MHz * Synchronous reset */ - input wire clk_250mhz, - input wire rst_250mhz, + input wire clk_250mhz, + input wire rst_250mhz, /* * PTP clock */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, /* * GPIO */ - input wire [1:0] button, - input wire [1:0] sw, - output wire [3:0] led, - output wire [3:0] led_bracket, + input wire [1:0] button, + input wire [1:0] sw, + output wire [3:0] led, + output wire [3:0] led_bracket, /* * P-Tile interface */ - input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data, - input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty, - input wire [SEG_COUNT-1:0] rx_st_sop, - input wire [SEG_COUNT-1:0] rx_st_eop, - input wire [SEG_COUNT-1:0] rx_st_valid, - output wire rx_st_ready, - input wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr, - input wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx, - input wire [SEG_COUNT-1:0] rx_st_vf_active, - input wire [SEG_COUNT*3-1:0] rx_st_func_num, - input wire [SEG_COUNT*11-1:0] rx_st_vf_num, - input wire [SEG_COUNT*3-1:0] rx_st_bar_range, - input wire [SEG_COUNT-1:0] rx_st_tlp_abort, + input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data, + input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty, + input wire [SEG_COUNT-1:0] rx_st_sop, + input wire [SEG_COUNT-1:0] rx_st_eop, + input wire [SEG_COUNT-1:0] rx_st_valid, + output wire rx_st_ready, + input wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr, + input wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx, + input wire [SEG_COUNT-1:0] rx_st_vf_active, + input wire [SEG_COUNT*3-1:0] rx_st_func_num, + input wire [SEG_COUNT*11-1:0] rx_st_vf_num, + input wire [SEG_COUNT*3-1:0] rx_st_bar_range, + input wire [SEG_COUNT-1:0] rx_st_tlp_abort, - output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data, - output wire [SEG_COUNT-1:0] tx_st_sop, - output wire [SEG_COUNT-1:0] tx_st_eop, - output wire [SEG_COUNT-1:0] tx_st_valid, - input wire tx_st_ready, - output wire [SEG_COUNT-1:0] tx_st_err, - output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr, - output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx, + output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data, + output wire [SEG_COUNT-1:0] tx_st_sop, + output wire [SEG_COUNT-1:0] tx_st_eop, + output wire [SEG_COUNT-1:0] tx_st_valid, + input wire tx_st_ready, + output wire [SEG_COUNT-1:0] tx_st_err, + output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr, + output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx, - output wire [11:0] rx_buffer_limit, - output wire [1:0] rx_buffer_limit_tdm_idx, + output wire [11:0] rx_buffer_limit, + output wire [1:0] rx_buffer_limit_tdm_idx, - input wire [15:0] tx_cdts_limit, - input wire [2:0] tx_cdts_limit_tdm_idx, + input wire [15:0] tx_cdts_limit, + input wire [2:0] tx_cdts_limit_tdm_idx, - input wire [15:0] tl_cfg_ctl, - input wire [4:0] tl_cfg_add, - input wire [2:0] tl_cfg_func, + input wire [15:0] tl_cfg_ctl, + input wire [4:0] tl_cfg_add, + input wire [2:0] tl_cfg_func, /* * Ethernet: QSFP-DD @@ -219,7 +222,10 @@ module fpga_core # output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast, output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser, + input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_clk, + input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_rst, output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time, + input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts, input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag, input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid, @@ -237,6 +243,8 @@ module fpga_core # input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast, input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser, + input wire [CH_CNT-1:0] qsfpdd_mac_rx_ptp_clk, + input wire [CH_CNT-1:0] qsfpdd_mac_rx_ptp_rst, output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time, input wire [CH_CNT-1:0] qsfpdd_mac_rx_status, @@ -547,7 +555,7 @@ wire [PORT_COUNT-1:0] eth_rx_status; mqnic_port_map_mac_axis #( .MAC_COUNT(CH_CNT), .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(2), + .PORT_GROUP_SIZE(PORT_GROUP_SIZE), .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), @@ -566,8 +574,8 @@ mqnic_port_map_mac_axis_inst ( .mac_tx_clk(qsfpdd_mac_tx_clk), .mac_tx_rst(qsfpdd_mac_tx_rst), - .mac_tx_ptp_clk(qsfpdd_mac_tx_clk), - .mac_tx_ptp_rst(qsfpdd_mac_tx_rst), + .mac_tx_ptp_clk(qsfpdd_mac_tx_ptp_clk), + .mac_tx_ptp_rst(qsfpdd_mac_tx_ptp_rst), .mac_tx_ptp_ts_96(qsfpdd_mac_tx_ptp_time), .mac_tx_ptp_ts_step(), @@ -593,8 +601,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk(qsfpdd_mac_rx_clk), .mac_rx_rst(qsfpdd_mac_rx_rst), - .mac_rx_ptp_clk(qsfpdd_mac_rx_clk), - .mac_rx_ptp_rst(qsfpdd_mac_rx_rst), + .mac_rx_ptp_clk(qsfpdd_mac_rx_ptp_clk), + .mac_rx_ptp_rst(qsfpdd_mac_rx_ptp_rst), .mac_rx_ptp_ts_96(qsfpdd_mac_rx_ptp_time), .mac_rx_ptp_ts_step(), @@ -683,8 +691,8 @@ mqnic_core_pcie_ptile #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(0), + .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.v index fbce8a92e..00bbeed07 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.v @@ -46,6 +46,7 @@ module test_fpga_core # // Board configuration parameter QSFPDD_CNT = 2, parameter CH_CNT = QSFPDD_CNT*2, + parameter PORT_GROUP_SIZE = 2, // Structural configuration parameter IF_COUNT = 2, @@ -63,6 +64,8 @@ module test_fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_SEPARATE_TX_CLOCK = 0, + parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -238,7 +241,10 @@ module test_fpga_core # // output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast, // output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser, + // input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_clk, + // input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_rst, // output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time, + // input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts, // input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag, // input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid, @@ -256,6 +262,8 @@ module test_fpga_core # // input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast, // input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser, + // input wire [CH_CNT-1:0] qsfpdd_mac_rx_ptp_clk, + // input wire [CH_CNT-1:0] qsfpdd_mac_rx_ptp_rst, // output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time, // input wire [CH_CNT-1:0] qsfpdd_mac_rx_status, @@ -299,7 +307,10 @@ wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready; wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast; wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser; +wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_clk; +wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_rst; wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time; + wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts; wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag; wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid; @@ -317,6 +328,8 @@ wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid; wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast; wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser; +wire [CH_CNT-1:0] qsfpdd_mac_rx_ptp_clk; +wire [CH_CNT-1:0] qsfpdd_mac_rx_ptp_rst; wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time; wire [CH_CNT-1:0] qsfpdd_mac_rx_status; @@ -327,39 +340,44 @@ generate for (n = 0; n < QSFPDD_CNT; n = n + 1) begin : ch - wire ch_mac_tx_clk; - wire ch_mac_tx_rst; + wire ch_mac_tx_clk; + wire ch_mac_tx_rst; - wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_tx_axis_tdata; - wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_tx_axis_tkeep; - wire ch_mac_tx_axis_tvalid; - wire ch_mac_tx_axis_tready; - wire ch_mac_tx_axis_tlast; - wire [AXIS_ETH_TX_USER_WIDTH-1:0] ch_mac_tx_axis_tuser; + wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_tx_axis_tdata; + wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_tx_axis_tkeep; + wire ch_mac_tx_axis_tvalid; + wire ch_mac_tx_axis_tready; + wire ch_mac_tx_axis_tlast; + wire [AXIS_ETH_TX_USER_WIDTH-1:0] ch_mac_tx_axis_tuser; - wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_time; - wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_ts; - wire [15:0] ch_mac_tx_ptp_ts_tag; - wire ch_mac_tx_ptp_ts_valid; + wire ch_mac_tx_ptp_clk; + wire ch_mac_tx_ptp_rst; + wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_time; - wire ch_mac_tx_status; - wire ch_mac_tx_lfc_req; - wire [7:0] ch_mac_tx_pfc_req; + wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_ts; + wire [15:0] ch_mac_tx_ptp_ts_tag; + wire ch_mac_tx_ptp_ts_valid; - wire ch_mac_rx_clk; - wire ch_mac_rx_rst; + wire ch_mac_tx_status; + wire ch_mac_tx_lfc_req; + wire [7:0] ch_mac_tx_pfc_req; - wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_rx_axis_tdata; - wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_rx_axis_tkeep; - wire ch_mac_rx_axis_tvalid; - wire ch_mac_rx_axis_tlast; - wire [AXIS_ETH_RX_USER_WIDTH-1:0] ch_mac_rx_axis_tuser; + wire ch_mac_rx_clk; + wire ch_mac_rx_rst; - wire [PTP_TS_WIDTH-1:0] ch_mac_rx_ptp_time; + wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_rx_axis_tdata; + wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_rx_axis_tkeep; + wire ch_mac_rx_axis_tvalid; + wire ch_mac_rx_axis_tlast; + wire [AXIS_ETH_RX_USER_WIDTH-1:0] ch_mac_rx_axis_tuser; - wire ch_mac_rx_status; - wire ch_mac_rx_lfc_req; - wire [7:0] ch_mac_rx_pfc_req; + wire ch_mac_rx_ptp_clk; + wire ch_mac_rx_ptp_rst; + wire [PTP_TS_WIDTH-1:0] ch_mac_rx_ptp_time; + + wire ch_mac_rx_status; + wire ch_mac_rx_lfc_req; + wire [7:0] ch_mac_rx_pfc_req; assign qsfpdd_mac_tx_clk[n +: 1] = ch_mac_tx_clk; assign qsfpdd_mac_tx_rst[n +: 1] = ch_mac_tx_rst; @@ -371,7 +389,10 @@ for (n = 0; n < QSFPDD_CNT; n = n + 1) begin : ch assign ch_mac_tx_axis_tlast = qsfpdd_mac_tx_axis_tlast[n +: 1]; assign ch_mac_tx_axis_tuser = qsfpdd_mac_tx_axis_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]; + assign qsfpdd_mac_tx_ptp_clk[n +: 1] = ch_mac_tx_ptp_clk; + assign qsfpdd_mac_tx_ptp_rst[n +: 1] = ch_mac_tx_ptp_rst; assign ch_mac_tx_ptp_time = qsfpdd_mac_tx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]; + assign qsfpdd_mac_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = ch_mac_tx_ptp_ts; assign qsfpdd_mac_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH] = ch_mac_tx_ptp_ts_tag; assign qsfpdd_mac_tx_ptp_ts_valid[n +: 1] = ch_mac_tx_ptp_ts_valid; @@ -389,6 +410,8 @@ for (n = 0; n < QSFPDD_CNT; n = n + 1) begin : ch assign qsfpdd_mac_rx_axis_tlast[n +: 1] = ch_mac_rx_axis_tlast; assign qsfpdd_mac_rx_axis_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH] = ch_mac_rx_axis_tuser; + assign qsfpdd_mac_rx_ptp_clk[n +: 1] = ch_mac_rx_ptp_clk; + assign qsfpdd_mac_rx_ptp_rst[n +: 1] = ch_mac_rx_ptp_rst; assign ch_mac_rx_ptp_time = qsfpdd_mac_rx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]; assign qsfpdd_mac_rx_status[n +: 1] = ch_mac_rx_status; @@ -413,6 +436,7 @@ fpga_core #( // Board configuration .QSFPDD_CNT(QSFPDD_CNT), .CH_CNT(CH_CNT), + .PORT_GROUP_SIZE(PORT_GROUP_SIZE), // Structural configuration .IF_COUNT(IF_COUNT), @@ -430,6 +454,8 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -605,7 +631,10 @@ uut ( .qsfpdd_mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast), .qsfpdd_mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser), + .qsfpdd_mac_tx_ptp_clk(qsfpdd_mac_tx_ptp_clk), + .qsfpdd_mac_tx_ptp_rst(qsfpdd_mac_tx_ptp_rst), .qsfpdd_mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time), + .qsfpdd_mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts), .qsfpdd_mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag), .qsfpdd_mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid), @@ -623,6 +652,8 @@ uut ( .qsfpdd_mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast), .qsfpdd_mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser), + .qsfpdd_mac_rx_ptp_clk(qsfpdd_mac_rx_ptp_clk), + .qsfpdd_mac_rx_ptp_rst(qsfpdd_mac_rx_ptp_rst), .qsfpdd_mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time), .qsfpdd_mac_rx_status(qsfpdd_mac_rx_status), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/README.md b/fpga/mqnic/DE10_Agilex/fpga_25g/README.md deleted file mode 100644 index 49c66ef2b..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/README.md +++ /dev/null @@ -1,22 +0,0 @@ -# Corundum mqnic for DE10-Agilex - -## Introduction - -This design targets the Terasic DE10-Agilex FPGA development board. - -* FPGA: AGFB014R24B2E2V -* PHY: E-Tile - -## Quick start - -### Build FPGA bitstream - -Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH. - -### Build driver and userspace tools - -On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. - -### Testing - -Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/app b/fpga/mqnic/DE10_Agilex/fpga_25g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/common/quartus_pro.mk b/fpga/mqnic/DE10_Agilex/fpga_25g/common/quartus_pro.mk deleted file mode 100644 index f7e9cea62..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/common/quartus_pro.mk +++ /dev/null @@ -1,188 +0,0 @@ -################################################################### -# -# Makefile for Intel Quartus Prime Pro -# -# Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. Stratix 10 DX) -# FPGA_DEVICE - FPGA device (e.g. 1SD280PT2F55E1VG) -# SYN_FILES - space-separated list of source files -# IP_FILES - space-separated list of IP files -# IP_TCL_FILES - space-separated list of TCL files for qsys-script -# QSF_FILES - space-separated list of settings files -# SDC_FILES - space-separated list of timing constraint files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = "Stratix 10 DX" -# FPGA_DEVICE = 1SD280PT2F55E1VG -# SYN_FILES = rtl/fpga.v -# QSF_FILES = fpga.qsf -# SDC_FILES = fpga.sdc -# include ../common/quartus_pro.mk -# -################################################################### - -# phony targets -.PHONY: clean fpga - -# output files to hang on to -.PRECIOUS: %.sof %.ipregen.rpt %.syn.rpt %.fit.rpt %.asm.rpt %.sta.rpt -.SECONDARY: - -# any project specific settings -CONFIG ?= config.mk --include ../$(CONFIG) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES)) -IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES))) - -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) -IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES))) -IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES))) - -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef QSF_FILES - QSF_FILES_REL = $(foreach p,$(QSF_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - QSF_FILES_REL = ../$(FPGA_TOP).qsf -endif - -SDC_FILES_REL = $(foreach p,$(SDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and database -################################################################### - -all: fpga - -fpga: $(FPGA_TOP).sof - -quartus: $(FPGA_TOP).qpf - quartus $(FPGA_TOP).qpf - -tmpclean:: - -rm -rf defines.v - -rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp - -rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit - -rm -rf create_project.tcl update_config.tcl update_ip_*.tcl - -clean:: tmpclean - -rm -rf *.sof *.pof *.jdi *.jic *.map - -distclean:: clean - -rm -rf rev - -syn: smart.log output_files/$(PROJECT).syn.rpt -fit: smart.log output_files/$(PROJECT).fit.rpt -asm: smart.log output_files/$(PROJECT).asm.rpt -sta: smart.log output_files/$(PROJECT).sta.rpt -smart: smart.log - -################################################################### -# Executable Configuration -################################################################### - -IP_ARGS = --run_default_mode_op -SYN_ARGS = --read_settings_files=on --write_settings_files=off -FIT_ARGS = --read_settings_files=on --write_settings_files=off -ASM_ARGS = --read_settings_files=on --write_settings_files=off -STA_ARGS = - -################################################################### -# Target implementations -################################################################### - -STAMP = echo done > - -define COPY_IP_RULE -$(patsubst %, ip/%, $(notdir $(1))): $(1) - @mkdir -p ip - @cp -pv $(1) ip/ -endef -$(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l)))) - -define TCL_IP_GEN_RULE -$(patsubst %.tcl,%.ip,$(1)): $(1) - cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf} - cd ip && qsys-script --script=$(notdir $(1)) -endef -$(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l)))) - -%.ipregen.rpt: $(FPGA_TOP).qpf $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) - quartus_ipgenerate $(IP_ARGS) $(FPGA_TOP) - -%.syn.rpt: syn.chg %.ipregen.rpt $(SYN_FILES_REL) - quartus_syn $(SYN_ARGS) $(FPGA_TOP) - -%.fit.rpt: fit.chg %.syn.rpt $(SDC_FILES_REL) - quartus_fit $(FIT_ARGS) $(FPGA_TOP) - -%.sta.rpt: sta.chg %.fit.rpt - quartus_sta $(STA_ARGS) $(FPGA_TOP) - -%.asm.rpt: asm.chg %.sta.rpt - quartus_asm $(ASM_ARGS) $(FPGA_TOP) - mkdir -p rev - EXT=sof; COUNT=100; \ - while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ - do let COUNT=COUNT+1; done; \ - cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \ - echo "Output: rev/$*_rev$$COUNT.$$EXT"; - -%.sof: smart.log %.asm.rpt - - -smart.log: $(ASSIGNMENT_FILES) - quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log - -################################################################### -# Project initialization -################################################################### - -create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) - rm -f update_config.tcl - echo "project_new $(FPGA_TOP) -overwrite" > $@ - echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@ - echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@ - for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \ - case $${x##*.} in \ - v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\ - vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\ - qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\ - ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\ - *) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\ - esac; \ - done - for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done - for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) - echo "project_open $(FPGA_TOP)" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done - -$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl - for x in $?; do quartus_sh -t "$$x"; done - touch -c $(ASSIGNMENT_FILES) - -syn.chg: - $(STAMP) syn.chg -fit.chg: - $(STAMP) fit.chg -sta.chg: - $(STAMP) sta.chg -asm.chg: - $(STAMP) asm.chg diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.qsf b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.qsf deleted file mode 100644 index e8ed034fb..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.qsf +++ /dev/null @@ -1,1582 +0,0 @@ -# I/O constraints for the Terasic DE10-Agilex FPGA development board -# part: AGFB014R24B2E2V - -set_global_assignment -name USE_CONF_DONE SDM_IO16 - -set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" -set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 -set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 -set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" -set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER -set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 4F -set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON - -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X16" -set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON -set_global_assignment -name GENERATE_COMPRESSED_SOF ON - -set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON - -set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on - -# Clock and reset -set_location_assignment PIN_CU50 -to clk_100_b2a -set_location_assignment PIN_CU24 -to clk_30m72 -set_location_assignment PIN_G52 -to clk_50_b3a -set_location_assignment PIN_G26 -to clk_50_b3c - -set_location_assignment PIN_DC22 -to clk_from_si5397a_p[0] -set_location_assignment PIN_A24 -to clk_from_si5397a_p[1] -set_location_assignment PIN_CU26 -to clk_to_si5397a_p[0] -set_location_assignment PIN_CU28 -to clk_to_si5397a_p[1] - -set_location_assignment PIN_DC52 -to ufl_clkin - -set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to clk_100_b2a -set_instance_assignment -name IO_STANDARD "1.2 V" -to clk_30m72 -set_instance_assignment -name IO_STANDARD "1.2 V" -to clk_50_b3a -set_instance_assignment -name IO_STANDARD "1.2 V" -to clk_50_b3c - -set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to clk_from_si5397a_p[0] -set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to clk_from_si5397a_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to clk_to_si5397a_p[0] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITHOUT CALIBRATION" -to clk_to_si5397a_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to clk_to_si5397a_p[1] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITHOUT CALIBRATION" -to clk_to_si5397a_p[1] - -set_instance_assignment -name IO_STANDARD "1.2 V" -to ufl_clkin - -# Switches, buttons, LEDs -set_location_assignment PIN_G56 -to cpu_reset_n -set_location_assignment PIN_J54 -to button[0] -set_location_assignment PIN_G54 -to button[1] - -set_location_assignment PIN_H51 -to sw[0] -set_location_assignment PIN_F51 -to sw[1] - -set_location_assignment PIN_CR54 -to led[0] -set_location_assignment PIN_DB57 -to led[1] -set_location_assignment PIN_CY57 -to led[2] -set_location_assignment PIN_CU52 -to led[3] - -set_location_assignment PIN_CT57 -to led_bracket[0] -set_location_assignment PIN_CV55 -to led_bracket[1] -set_location_assignment PIN_CR56 -to led_bracket[2] -set_location_assignment PIN_CU56 -to led_bracket[3] - -set_instance_assignment -name IO_STANDARD "1.2 V" -to cpu_reset_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to button[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to button[1] - -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[1] - -set_instance_assignment -name IO_STANDARD "1.2 V" -to led[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to led[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to led[2] -set_instance_assignment -name IO_STANDARD "1.2 V" -to led[3] - -set_instance_assignment -name IO_STANDARD "1.2 V" -to led_bracket[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to led_bracket[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to led_bracket[2] -set_instance_assignment -name IO_STANDARD "1.2 V" -to led_bracket[3] - -set_location_assignment PIN_CY21 -to gpio_p[0] -set_location_assignment PIN_CT25 -to gpio_p[1] -set_location_assignment PIN_CT17 -to gpio_p[2] -set_location_assignment PIN_DC20 -to gpio_p[3] -set_location_assignment PIN_CV27 -to gpio_clk[0] -set_location_assignment PIN_CR24 -to gpio_clk[1] - -set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio_clk[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio_clk[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio_p[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio_p[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio_p[2] -set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio_p[3] - -set_location_assignment PIN_A20 -to exp_en - -set_instance_assignment -name IO_STANDARD "1.2 V" -to exp_en - -# UART -set_location_assignment PIN_D23 -to ag_uart_tx -set_location_assignment PIN_A22 -to ag_uart_rx -set_location_assignment PIN_B23 -to ag_uart_cts -set_location_assignment PIN_C22 -to ag_uart_rts - -set_instance_assignment -name IO_STANDARD "1.2 V" -to ag_uart_tx -set_instance_assignment -name IO_STANDARD "1.2 V" -to ag_uart_rx -set_instance_assignment -name IO_STANDARD "1.2 V" -to ag_uart_cts -set_instance_assignment -name IO_STANDARD "1.2 V" -to ag_uart_rts - -# MAX10 BMC -set_location_assignment PIN_CU18 -to info_spi_sclk -set_location_assignment PIN_CV29 -to info_spi_miso -set_location_assignment PIN_CV17 -to info_spi_mosi -set_location_assignment PIN_CR18 -to info_spi_cs_n - -set_instance_assignment -name IO_STANDARD "1.2 V" -to info_spi_sclk -set_instance_assignment -name IO_STANDARD "1.2 V" -to info_spi_miso -set_instance_assignment -name IO_STANDARD "1.2 V" -to info_spi_mosi -set_instance_assignment -name IO_STANDARD "1.2 V" -to info_spi_cs_n - -# QSPI -set_location_assignment PIN_CT53 -to qspi_clk -set_location_assignment PIN_CT55 -to qspi_data[0] -set_location_assignment PIN_CV57 -to qspi_data[1] -set_location_assignment PIN_DC56 -to qspi_data[2] -set_location_assignment PIN_DA56 -to qspi_data[3] -set_location_assignment PIN_CV53 -to qspi_ncso - -set_instance_assignment -name IO_STANDARD "1.2 V" -to qspi_clk -set_instance_assignment -name IO_STANDARD "1.2 V" -to qspi_data[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to qspi_data[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to qspi_data[2] -set_instance_assignment -name IO_STANDARD "1.2 V" -to qspi_data[3] -set_instance_assignment -name IO_STANDARD "1.2 V" -to qspi_ncso - -# SI5397A -set_location_assignment PIN_CV47 -to si5397a_i2c_scl -set_location_assignment PIN_CR46 -to si5397a_i2c_sda -set_location_assignment PIN_CT19 -to si5397a_lol_a_n -set_location_assignment PIN_CV21 -to si5397a_lol_b_n -set_location_assignment PIN_DB17 -to si5397a_lol_c_n -set_location_assignment PIN_CT27 -to si5397a_lol_d_n -set_location_assignment PIN_CV19 -to si5397a_los_xaxb_n -set_location_assignment PIN_CT45 -to si5397a_oe_n -set_location_assignment PIN_CU46 -to si5397a_rst_n - -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_i2c_scl -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_i2c_sda -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_lol_a_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_lol_b_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_lol_c_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_lol_d_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_los_xaxb_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_oe_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_rst_n - -# PCIe -set_location_assignment PIN_BP55 -to pcie_tx_p[0] ;# GXPL10A_TX_CH0P -set_location_assignment PIN_BN52 -to pcie_tx_p[1] ;# GXPL10A_TX_CH1P -set_location_assignment PIN_BK55 -to pcie_tx_p[2] ;# GXPL10A_TX_CH2P -set_location_assignment PIN_BJ52 -to pcie_tx_p[3] ;# GXPL10A_TX_CH3P -set_location_assignment PIN_BF55 -to pcie_tx_p[4] ;# GXPL10A_TX_CH4P -set_location_assignment PIN_BE52 -to pcie_tx_p[5] ;# GXPL10A_TX_CH5P -set_location_assignment PIN_BB55 -to pcie_tx_p[6] ;# GXPL10A_TX_CH6P -set_location_assignment PIN_BA52 -to pcie_tx_p[7] ;# GXPL10A_TX_CH7P -set_location_assignment PIN_AV55 -to pcie_tx_p[8] ;# GXPL10A_TX_CH8P -set_location_assignment PIN_AU52 -to pcie_tx_p[9] ;# GXPL10A_TX_CH9P -set_location_assignment PIN_AP55 -to pcie_tx_p[10] ;# GXPL10A_TX_CH10P -set_location_assignment PIN_AN52 -to pcie_tx_p[11] ;# GXPL10A_TX_CH11P -set_location_assignment PIN_AK55 -to pcie_tx_p[12] ;# GXPL10A_TX_CH12P -set_location_assignment PIN_AJ52 -to pcie_tx_p[13] ;# GXPL10A_TX_CH13P -set_location_assignment PIN_AF55 -to pcie_tx_p[14] ;# GXPL10A_TX_CH14P -set_location_assignment PIN_AE52 -to pcie_tx_p[15] ;# GXPL10A_TX_CH15P -set_location_assignment PIN_BR56 -to pcie_tx_n[0] ;# GXPL10A_TX_CH0N -set_location_assignment PIN_BM53 -to pcie_tx_n[1] ;# GXPL10A_TX_CH1N -set_location_assignment PIN_BL56 -to pcie_tx_n[2] ;# GXPL10A_TX_CH2N -set_location_assignment PIN_BH53 -to pcie_tx_n[3] ;# GXPL10A_TX_CH3N -set_location_assignment PIN_BG56 -to pcie_tx_n[4] ;# GXPL10A_TX_CH4N -set_location_assignment PIN_BD53 -to pcie_tx_n[5] ;# GXPL10A_TX_CH5N -set_location_assignment PIN_BC56 -to pcie_tx_n[6] ;# GXPL10A_TX_CH6N -set_location_assignment PIN_AY53 -to pcie_tx_n[7] ;# GXPL10A_TX_CH7N -set_location_assignment PIN_AW56 -to pcie_tx_n[8] ;# GXPL10A_TX_CH8N -set_location_assignment PIN_AT53 -to pcie_tx_n[9] ;# GXPL10A_TX_CH9N -set_location_assignment PIN_AR56 -to pcie_tx_n[10] ;# GXPL10A_TX_CH10N -set_location_assignment PIN_AM53 -to pcie_tx_n[11] ;# GXPL10A_TX_CH11N -set_location_assignment PIN_AL56 -to pcie_tx_n[12] ;# GXPL10A_TX_CH12N -set_location_assignment PIN_AH53 -to pcie_tx_n[13] ;# GXPL10A_TX_CH13N -set_location_assignment PIN_AG56 -to pcie_tx_n[14] ;# GXPL10A_TX_CH14N -set_location_assignment PIN_AD53 -to pcie_tx_n[15] ;# GXPL10A_TX_CH15N -set_location_assignment PIN_BP61 -to pcie_rx_p[0] ;# GXPL10A_RX_CH0P -set_location_assignment PIN_BN58 -to pcie_rx_p[1] ;# GXPL10A_RX_CH1P -set_location_assignment PIN_BK61 -to pcie_rx_p[2] ;# GXPL10A_RX_CH2P -set_location_assignment PIN_BJ58 -to pcie_rx_p[3] ;# GXPL10A_RX_CH3P -set_location_assignment PIN_BF61 -to pcie_rx_p[4] ;# GXPL10A_RX_CH4P -set_location_assignment PIN_BE58 -to pcie_rx_p[5] ;# GXPL10A_RX_CH5P -set_location_assignment PIN_BB61 -to pcie_rx_p[6] ;# GXPL10A_RX_CH6P -set_location_assignment PIN_BA58 -to pcie_rx_p[7] ;# GXPL10A_RX_CH7P -set_location_assignment PIN_AV61 -to pcie_rx_p[8] ;# GXPL10A_RX_CH8P -set_location_assignment PIN_AU58 -to pcie_rx_p[9] ;# GXPL10A_RX_CH9P -set_location_assignment PIN_AP61 -to pcie_rx_p[10] ;# GXPL10A_RX_CH10P -set_location_assignment PIN_AN58 -to pcie_rx_p[11] ;# GXPL10A_RX_CH11P -set_location_assignment PIN_AK61 -to pcie_rx_p[12] ;# GXPL10A_RX_CH12P -set_location_assignment PIN_AJ58 -to pcie_rx_p[13] ;# GXPL10A_RX_CH13P -set_location_assignment PIN_AF61 -to pcie_rx_p[14] ;# GXPL10A_RX_CH14P -set_location_assignment PIN_AE58 -to pcie_rx_p[15] ;# GXPL10A_RX_CH15P -set_location_assignment PIN_BR62 -to pcie_rx_n[0] ;# GXPL10A_RX_CH0N -set_location_assignment PIN_BM59 -to pcie_rx_n[1] ;# GXPL10A_RX_CH1N -set_location_assignment PIN_BL62 -to pcie_rx_n[2] ;# GXPL10A_RX_CH2N -set_location_assignment PIN_BH59 -to pcie_rx_n[3] ;# GXPL10A_RX_CH3N -set_location_assignment PIN_BG62 -to pcie_rx_n[4] ;# GXPL10A_RX_CH4N -set_location_assignment PIN_BD59 -to pcie_rx_n[5] ;# GXPL10A_RX_CH5N -set_location_assignment PIN_BC62 -to pcie_rx_n[6] ;# GXPL10A_RX_CH6N -set_location_assignment PIN_AY59 -to pcie_rx_n[7] ;# GXPL10A_RX_CH7N -set_location_assignment PIN_AW62 -to pcie_rx_n[8] ;# GXPL10A_RX_CH8N -set_location_assignment PIN_AT59 -to pcie_rx_n[9] ;# GXPL10A_RX_CH9N -set_location_assignment PIN_AR62 -to pcie_rx_n[10] ;# GXPL10A_RX_CH10N -set_location_assignment PIN_AM59 -to pcie_rx_n[11] ;# GXPL10A_RX_CH11N -set_location_assignment PIN_AL62 -to pcie_rx_n[12] ;# GXPL10A_RX_CH12N -set_location_assignment PIN_AH59 -to pcie_rx_n[13] ;# GXPL10A_RX_CH13N -set_location_assignment PIN_AG62 -to pcie_rx_n[14] ;# GXPL10A_RX_CH14N -set_location_assignment PIN_AD59 -to pcie_rx_n[15] ;# GXPL10A_RX_CH15N -set_location_assignment PIN_AJ48 -to pcie_refclk_p[0] ;# REFCLK_GXPL10A_CH0P -set_location_assignment PIN_AE48 -to pcie_refclk_p[1] ;# REFCLK_GXPL10A_CH2P -set_location_assignment PIN_BU58 -to pcie_perst_n ;# I_PIN_PERST_N_U10_P - -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[4] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[5] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[6] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[7] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[8] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[9] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[10] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[11] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[12] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[13] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[14] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[15] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[4] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[5] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[6] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[7] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[8] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[9] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[10] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[11] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[12] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[13] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[14] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[15] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[4] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[5] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[6] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[7] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[8] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[9] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[10] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[11] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[12] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[13] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[14] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[15] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[4] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[5] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[6] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[7] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[8] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[9] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[10] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[11] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[12] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[13] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[14] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[15] -set_instance_assignment -name IO_STANDARD "HCSL" -to pcie_refclk_p[0] -set_instance_assignment -name IO_STANDARD "HCSL" -to pcie_refclk_p[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie_perst_n - -# SI5397A -set_location_assignment PIN_CV47 -to si5397a_i2c_scl -set_location_assignment PIN_CR46 -to si5397a_i2c_sda -set_location_assignment PIN_CT19 -to si5397a_lol_a_n -set_location_assignment PIN_CV21 -to si5397a_lol_b_n -set_location_assignment PIN_DB17 -to si5397a_lol_c_n -set_location_assignment PIN_CT27 -to si5397a_lol_d_n -set_location_assignment PIN_CV19 -to si5397a_los_xaxb_n -set_location_assignment PIN_CT45 -to si5397a_oe_n -set_location_assignment PIN_CU46 -to si5397a_rst_n - -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_i2c_scl -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_i2c_sda -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_lol_a_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_lol_b_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_lol_c_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_lol_d_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_los_xaxb_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_oe_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to si5397a_rst_n - -# QSFP-DD -set_location_assignment PIN_BF1 -to qsfpdda_tx_p[0] ;# GXER9A_TX_CH12P -set_location_assignment PIN_BK1 -to qsfpdda_tx_p[1] ;# GXER9A_TX_CH14P -set_location_assignment PIN_BG4 -to qsfpdda_tx_p[2] ;# GXER9A_TX_CH13P -set_location_assignment PIN_BL4 -to qsfpdda_tx_p[3] ;# GXER9A_TX_CH15P -set_location_assignment PIN_BP1 -to qsfpdda_tx_p[4] ;# GXER9A_TX_CH20P -set_location_assignment PIN_BV1 -to qsfpdda_tx_p[5] ;# GXER9A_TX_CH22P -set_location_assignment PIN_BR4 -to qsfpdda_tx_p[6] ;# GXER9A_TX_CH21P -set_location_assignment PIN_BW4 -to qsfpdda_tx_p[7] ;# GXER9A_TX_CH23P -set_location_assignment PIN_BE2 -to qsfpdda_tx_n[0] ;# GXER9A_TX_CH12N -set_location_assignment PIN_BJ2 -to qsfpdda_tx_n[1] ;# GXER9A_TX_CH14N -set_location_assignment PIN_BH5 -to qsfpdda_tx_n[2] ;# GXER9A_TX_CH13N -set_location_assignment PIN_BM5 -to qsfpdda_tx_n[3] ;# GXER9A_TX_CH15N -set_location_assignment PIN_BN2 -to qsfpdda_tx_n[4] ;# GXER9A_TX_CH20N -set_location_assignment PIN_BU2 -to qsfpdda_tx_n[5] ;# GXER9A_TX_CH22N -set_location_assignment PIN_BT5 -to qsfpdda_tx_n[6] ;# GXER9A_TX_CH21N -set_location_assignment PIN_BY5 -to qsfpdda_tx_n[7] ;# GXER9A_TX_CH23N -set_location_assignment PIN_BF7 -to qsfpdda_rx_p[0] ;# GXER9A_RX_CH12P -set_location_assignment PIN_BK7 -to qsfpdda_rx_p[1] ;# GXER9A_RX_CH14P -set_location_assignment PIN_BG10 -to qsfpdda_rx_p[2] ;# GXER9A_RX_CH13P -set_location_assignment PIN_BL10 -to qsfpdda_rx_p[3] ;# GXER9A_RX_CH15P -set_location_assignment PIN_BP7 -to qsfpdda_rx_p[4] ;# GXER9A_RX_CH20P -set_location_assignment PIN_BV7 -to qsfpdda_rx_p[5] ;# GXER9A_RX_CH22P -set_location_assignment PIN_BR10 -to qsfpdda_rx_p[6] ;# GXER9A_RX_CH21P -set_location_assignment PIN_BW10 -to qsfpdda_rx_p[7] ;# GXER9A_RX_CH23P -set_location_assignment PIN_BE8 -to qsfpdda_rx_n[0] ;# GXER9A_RX_CH12N -set_location_assignment PIN_BJ8 -to qsfpdda_rx_n[1] ;# GXER9A_RX_CH14N -set_location_assignment PIN_BH11 -to qsfpdda_rx_n[2] ;# GXER9A_RX_CH13N -set_location_assignment PIN_BM11 -to qsfpdda_rx_n[3] ;# GXER9A_RX_CH15N -set_location_assignment PIN_BN8 -to qsfpdda_rx_n[4] ;# GXER9A_RX_CH20N -set_location_assignment PIN_BU8 -to qsfpdda_rx_n[5] ;# GXER9A_RX_CH22N -set_location_assignment PIN_BT11 -to qsfpdda_rx_n[6] ;# GXER9A_RX_CH21N -set_location_assignment PIN_BY11 -to qsfpdda_rx_n[7] ;# GXER9A_RX_CH23N -set_location_assignment PIN_AJ12 -to qsfpdda_refclk_p ;# REFCLK_GXER9A_CH2P -set_location_assignment PIN_DB21 -to qsfpdda_initmode -set_location_assignment PIN_CV25 -to qsfpdda_interrupt_n -set_location_assignment PIN_CT29 -to qsfpdda_mod_prs_n -set_location_assignment PIN_DB19 -to qsfpdda_mod_sel_n -set_location_assignment PIN_DA20 -to qsfpdda_rst_n -set_location_assignment PIN_H21 -to qsfpdda_scl -set_location_assignment PIN_H23 -to qsfpdda_sda - -set_location_assignment PIN_AK1 -to qsfpddb_tx_p[0] ;# GXER9A_TX_CH0P -set_location_assignment PIN_AP1 -to qsfpddb_tx_p[1] ;# GXER9A_TX_CH2P -set_location_assignment PIN_AL4 -to qsfpddb_tx_p[2] ;# GXER9A_TX_CH1P -set_location_assignment PIN_AR4 -to qsfpddb_tx_p[3] ;# GXER9A_TX_CH3P -set_location_assignment PIN_AV1 -to qsfpddb_tx_p[4] ;# GXER9A_TX_CH8P -set_location_assignment PIN_BB1 -to qsfpddb_tx_p[5] ;# GXER9A_TX_CH10P -set_location_assignment PIN_AW4 -to qsfpddb_tx_p[6] ;# GXER9A_TX_CH9P -set_location_assignment PIN_BC4 -to qsfpddb_tx_p[7] ;# GXER9A_TX_CH11P -set_location_assignment PIN_AJ2 -to qsfpddb_tx_n[0] ;# GXER9A_TX_CH0N -set_location_assignment PIN_AN2 -to qsfpddb_tx_n[1] ;# GXER9A_TX_CH2N -set_location_assignment PIN_AM5 -to qsfpddb_tx_n[2] ;# GXER9A_TX_CH1N -set_location_assignment PIN_AT5 -to qsfpddb_tx_n[3] ;# GXER9A_TX_CH3N -set_location_assignment PIN_AU2 -to qsfpddb_tx_n[4] ;# GXER9A_TX_CH8N -set_location_assignment PIN_BA2 -to qsfpddb_tx_n[5] ;# GXER9A_TX_CH10N -set_location_assignment PIN_AY5 -to qsfpddb_tx_n[6] ;# GXER9A_TX_CH9N -set_location_assignment PIN_BD5 -to qsfpddb_tx_n[7] ;# GXER9A_TX_CH11N -set_location_assignment PIN_AK7 -to qsfpddb_rx_p[0] ;# GXER9A_RX_CH0P -set_location_assignment PIN_AP7 -to qsfpddb_rx_p[1] ;# GXER9A_RX_CH2P -set_location_assignment PIN_AL10 -to qsfpddb_rx_p[2] ;# GXER9A_RX_CH1P -set_location_assignment PIN_AR10 -to qsfpddb_rx_p[3] ;# GXER9A_RX_CH3P -set_location_assignment PIN_AV7 -to qsfpddb_rx_p[4] ;# GXER9A_RX_CH8P -set_location_assignment PIN_BB7 -to qsfpddb_rx_p[5] ;# GXER9A_RX_CH10P -set_location_assignment PIN_AW10 -to qsfpddb_rx_p[6] ;# GXER9A_RX_CH9P -set_location_assignment PIN_BC10 -to qsfpddb_rx_p[7] ;# GXER9A_RX_CH11P -set_location_assignment PIN_AJ8 -to qsfpddb_rx_n[0] ;# GXER9A_RX_CH0N -set_location_assignment PIN_AN8 -to qsfpddb_rx_n[1] ;# GXER9A_RX_CH2N -set_location_assignment PIN_AM11 -to qsfpddb_rx_n[2] ;# GXER9A_RX_CH1N -set_location_assignment PIN_AT11 -to qsfpddb_rx_n[3] ;# GXER9A_RX_CH3N -set_location_assignment PIN_AU8 -to qsfpddb_rx_n[4] ;# GXER9A_RX_CH8N -set_location_assignment PIN_BA8 -to qsfpddb_rx_n[5] ;# GXER9A_RX_CH10N -set_location_assignment PIN_AY11 -to qsfpddb_rx_n[6] ;# GXER9A_RX_CH9N -set_location_assignment PIN_BD11 -to qsfpddb_rx_n[7] ;# GXER9A_RX_CH11N -set_location_assignment PIN_AT13 -to qsfpddb_refclk_p ;# REFCLK_GXER9A_CH0P -set_location_assignment PIN_DA18 -to qsfpddb_initmode -set_location_assignment PIN_DC18 -to qsfpddb_interrupt_n -set_location_assignment PIN_CY19 -to qsfpddb_mod_prs_n -set_location_assignment PIN_CR22 -to qsfpddb_mod_sel_n -set_location_assignment PIN_CU22 -to qsfpddb_rst_n -set_location_assignment PIN_CY17 -to qsfpddb_scl -set_location_assignment PIN_H19 -to qsfpddb_sda - -set_location_assignment PIN_AR14 -to qsfpddrsv_refclk_p ;# REFCLK_GXER9A_CH1P - -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_tx_p[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_tx_p[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_tx_p[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_tx_p[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_tx_p[4] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_tx_p[5] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_tx_p[6] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_tx_p[7] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_rx_p[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_rx_p[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_rx_p[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_rx_p[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_rx_p[4] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_rx_p[5] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_rx_p[6] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdda_rx_p[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to qsfpdda_refclk_p -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdda_initmode -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdda_interrupt_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdda_mod_prs_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdda_mod_sel_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdda_rst_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdda_scl -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdda_sda - -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_tx_p[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_tx_p[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_tx_p[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_tx_p[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_tx_p[4] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_tx_p[5] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_tx_p[6] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_tx_p[7] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_rx_p[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_rx_p[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_rx_p[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_rx_p[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_rx_p[4] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_rx_p[5] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_rx_p[6] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpddb_rx_p[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to qsfpddb_refclk_p -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpddb_initmode -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpddb_interrupt_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpddb_mod_prs_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpddb_mod_sel_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpddb_rst_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpddb_scl -set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpddb_sda - -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to qsfpddrsv_refclk_p - -set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_BTI_clock=TRUE" -to qsfpdda_refclk_p -set_instance_assignment -name HSSI_PARAMETER "refclk_divider_input_freq=156250000" -to qsfpdda_refclk_p - -# DDR4A -set_location_assignment PIN_A10 -to ddr4a_refclk_p -set_location_assignment PIN_F17 -to ddr4a_a[0] -set_location_assignment PIN_H17 -to ddr4a_a[1] -set_location_assignment PIN_G16 -to ddr4a_a[2] -set_location_assignment PIN_J16 -to ddr4a_a[3] -set_location_assignment PIN_F15 -to ddr4a_a[4] -set_location_assignment PIN_H15 -to ddr4a_a[5] -set_location_assignment PIN_G14 -to ddr4a_a[6] -set_location_assignment PIN_J14 -to ddr4a_a[7] -set_location_assignment PIN_F13 -to ddr4a_a[8] -set_location_assignment PIN_H13 -to ddr4a_a[9] -set_location_assignment PIN_G12 -to ddr4a_a[10] -set_location_assignment PIN_J12 -to ddr4a_a[11] -set_location_assignment PIN_D9 -to ddr4a_a[12] -set_location_assignment PIN_A8 -to ddr4a_a[13] -set_location_assignment PIN_C8 -to ddr4a_a[14] -set_location_assignment PIN_B7 -to ddr4a_a[15] -set_location_assignment PIN_D7 -to ddr4a_a[16] -set_location_assignment PIN_C6 -to ddr4a_ba[0] -set_location_assignment PIN_B5 -to ddr4a_ba[1] -set_location_assignment PIN_D5 -to ddr4a_bg[0] -set_location_assignment PIN_B17 -to ddr4a_bg[1] -set_location_assignment PIN_B13 -to ddr4a_ck[0] -set_location_assignment PIN_F5 -to ddr4a_ck[1] -set_location_assignment PIN_D13 -to ddr4a_ck_n[0] -set_location_assignment PIN_H5 -to ddr4a_ck_n[1] -set_location_assignment PIN_A14 -to ddr4a_cke[0] -set_location_assignment PIN_C14 -to ddr4a_cke[1] -set_location_assignment PIN_T15 -to ddr4a_dqs[0] -set_location_assignment PIN_L8 -to ddr4a_dqs[1] -set_location_assignment PIN_U8 -to ddr4a_dqs[2] -set_location_assignment PIN_M15 -to ddr4a_dqs[3] -set_location_assignment PIN_B29 -to ddr4a_dqs[4] -set_location_assignment PIN_M29 -to ddr4a_dqs[5] -set_location_assignment PIN_T29 -to ddr4a_dqs[6] -set_location_assignment PIN_U22 -to ddr4a_dqs[7] -set_location_assignment PIN_L22 -to ddr4a_dqs[8] -set_location_assignment PIN_V15 -to ddr4a_dqs_n[0] -set_location_assignment PIN_N8 -to ddr4a_dqs_n[1] -set_location_assignment PIN_W8 -to ddr4a_dqs_n[2] -set_location_assignment PIN_P15 -to ddr4a_dqs_n[3] -set_location_assignment PIN_D29 -to ddr4a_dqs_n[4] -set_location_assignment PIN_P29 -to ddr4a_dqs_n[5] -set_location_assignment PIN_V29 -to ddr4a_dqs_n[6] -set_location_assignment PIN_W22 -to ddr4a_dqs_n[7] -set_location_assignment PIN_N22 -to ddr4a_dqs_n[8] -set_location_assignment PIN_W12 -to ddr4a_dq[0] -set_location_assignment PIN_W16 -to ddr4a_dq[1] -set_location_assignment PIN_U12 -to ddr4a_dq[2] -set_location_assignment PIN_V13 -to ddr4a_dq[3] -set_location_assignment PIN_T17 -to ddr4a_dq[4] -set_location_assignment PIN_V17 -to ddr4a_dq[5] -set_location_assignment PIN_T13 -to ddr4a_dq[6] -set_location_assignment PIN_U16 -to ddr4a_dq[7] -set_location_assignment PIN_N10 -to ddr4a_dq[8] -set_location_assignment PIN_P5 -to ddr4a_dq[9] -set_location_assignment PIN_L6 -to ddr4a_dq[10] -set_location_assignment PIN_L10 -to ddr4a_dq[11] -set_location_assignment PIN_N6 -to ddr4a_dq[12] -set_location_assignment PIN_P9 -to ddr4a_dq[13] -set_location_assignment PIN_M9 -to ddr4a_dq[14] -set_location_assignment PIN_M5 -to ddr4a_dq[15] -set_location_assignment PIN_U6 -to ddr4a_dq[16] -set_location_assignment PIN_V9 -to ddr4a_dq[17] -set_location_assignment PIN_W6 -to ddr4a_dq[18] -set_location_assignment PIN_T9 -to ddr4a_dq[19] -set_location_assignment PIN_W10 -to ddr4a_dq[20] -set_location_assignment PIN_T5 -to ddr4a_dq[21] -set_location_assignment PIN_V5 -to ddr4a_dq[22] -set_location_assignment PIN_U10 -to ddr4a_dq[23] -set_location_assignment PIN_N16 -to ddr4a_dq[24] -set_location_assignment PIN_L12 -to ddr4a_dq[25] -set_location_assignment PIN_M17 -to ddr4a_dq[26] -set_location_assignment PIN_P17 -to ddr4a_dq[27] -set_location_assignment PIN_P13 -to ddr4a_dq[28] -set_location_assignment PIN_M13 -to ddr4a_dq[29] -set_location_assignment PIN_L16 -to ddr4a_dq[30] -set_location_assignment PIN_N12 -to ddr4a_dq[31] -set_location_assignment PIN_B27 -to ddr4a_dq[32] -set_location_assignment PIN_A30 -to ddr4a_dq[33] -set_location_assignment PIN_B31 -to ddr4a_dq[34] -set_location_assignment PIN_A26 -to ddr4a_dq[35] -set_location_assignment PIN_C26 -to ddr4a_dq[36] -set_location_assignment PIN_D27 -to ddr4a_dq[37] -set_location_assignment PIN_D31 -to ddr4a_dq[38] -set_location_assignment PIN_C30 -to ddr4a_dq[39] -set_location_assignment PIN_M27 -to ddr4a_dq[40] -set_location_assignment PIN_N26 -to ddr4a_dq[41] -set_location_assignment PIN_N30 -to ddr4a_dq[42] -set_location_assignment PIN_P31 -to ddr4a_dq[43] -set_location_assignment PIN_P27 -to ddr4a_dq[44] -set_location_assignment PIN_L26 -to ddr4a_dq[45] -set_location_assignment PIN_L30 -to ddr4a_dq[46] -set_location_assignment PIN_M31 -to ddr4a_dq[47] -set_location_assignment PIN_T27 -to ddr4a_dq[48] -set_location_assignment PIN_U30 -to ddr4a_dq[49] -set_location_assignment PIN_W26 -to ddr4a_dq[50] -set_location_assignment PIN_V31 -to ddr4a_dq[51] -set_location_assignment PIN_V27 -to ddr4a_dq[52] -set_location_assignment PIN_U26 -to ddr4a_dq[53] -set_location_assignment PIN_T31 -to ddr4a_dq[54] -set_location_assignment PIN_W30 -to ddr4a_dq[55] -set_location_assignment PIN_V23 -to ddr4a_dq[56] -set_location_assignment PIN_V19 -to ddr4a_dq[57] -set_location_assignment PIN_U24 -to ddr4a_dq[58] -set_location_assignment PIN_U20 -to ddr4a_dq[59] -set_location_assignment PIN_W20 -to ddr4a_dq[60] -set_location_assignment PIN_T23 -to ddr4a_dq[61] -set_location_assignment PIN_W24 -to ddr4a_dq[62] -set_location_assignment PIN_T19 -to ddr4a_dq[63] -set_location_assignment PIN_M23 -to ddr4a_dq[64] -set_location_assignment PIN_N20 -to ddr4a_dq[65] -set_location_assignment PIN_L20 -to ddr4a_dq[66] -set_location_assignment PIN_P23 -to ddr4a_dq[67] -set_location_assignment PIN_P19 -to ddr4a_dq[68] -set_location_assignment PIN_M19 -to ddr4a_dq[69] -set_location_assignment PIN_L24 -to ddr4a_dq[70] -set_location_assignment PIN_N24 -to ddr4a_dq[71] -set_location_assignment PIN_U14 -to ddr4a_dbi_n[0] -set_location_assignment PIN_M7 -to ddr4a_dbi_n[1] -set_location_assignment PIN_T7 -to ddr4a_dbi_n[2] -set_location_assignment PIN_L14 -to ddr4a_dbi_n[3] -set_location_assignment PIN_A28 -to ddr4a_dbi_n[4] -set_location_assignment PIN_L28 -to ddr4a_dbi_n[5] -set_location_assignment PIN_U28 -to ddr4a_dbi_n[6] -set_location_assignment PIN_T21 -to ddr4a_dbi_n[7] -set_location_assignment PIN_M21 -to ddr4a_dbi_n[8] -set_location_assignment PIN_A16 -to ddr4a_cs_n[0] -set_location_assignment PIN_A12 -to ddr4a_cs_n[1] -set_location_assignment PIN_D17 -to ddr4a_reset_n -set_location_assignment PIN_B15 -to ddr4a_odt[0] -set_location_assignment PIN_D15 -to ddr4a_odt[1] -set_location_assignment PIN_C12 -to ddr4a_par -set_location_assignment PIN_A6 -to ddr4a_alert_n -set_location_assignment PIN_C16 -to ddr4a_act_n -set_location_assignment PIN_F29 -to ddr4a_event_n -set_location_assignment PIN_G30 -to ddr4a_scl -set_location_assignment PIN_J28 -to ddr4a_sda -set_location_assignment PIN_B9 -to ddr4a_rzq - -set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to ddr4a_refclk_p -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[2] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[3] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[4] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[5] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[6] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[7] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[9] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[10] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[11] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[12] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[13] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[14] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[15] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_a[16] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_ba[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_ba[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_bg[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_bg[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4a_ck[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4a_ck[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4a_ck_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4a_ck_n[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_cke[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_cke[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs[8] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs_n[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs_n[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs_n[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs_n[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4a_dqs_n[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[9] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[10] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[11] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[12] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[13] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[14] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[15] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[16] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[17] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[18] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[19] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[20] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[21] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[22] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[23] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[24] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[25] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[26] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[27] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[28] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[29] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[30] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[31] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[32] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[33] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[34] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[35] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[36] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[37] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[38] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[39] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[40] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[41] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[42] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[43] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[44] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[45] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[46] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[47] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[48] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[49] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[50] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[51] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[52] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[53] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[54] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[55] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[56] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[57] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[58] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[59] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[60] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[61] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[62] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[63] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[64] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[65] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[66] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[67] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[68] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[69] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[70] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dq[71] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dbi_n[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dbi_n[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dbi_n[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dbi_n[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dbi_n[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dbi_n[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dbi_n[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dbi_n[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4a_dbi_n[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_cs_n[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_cs_n[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4a_reset_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_odt[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_odt[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_par -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4a_alert_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4a_act_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4a_event_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4a_scl -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4a_sda -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4a_rzq - -# DDR4B -set_location_assignment PIN_L40 -to ddr4b_refclk_p -set_location_assignment PIN_T33 -to ddr4b_a[0] -set_location_assignment PIN_V33 -to ddr4b_a[1] -set_location_assignment PIN_U34 -to ddr4b_a[2] -set_location_assignment PIN_W34 -to ddr4b_a[3] -set_location_assignment PIN_T35 -to ddr4b_a[4] -set_location_assignment PIN_V35 -to ddr4b_a[5] -set_location_assignment PIN_U36 -to ddr4b_a[6] -set_location_assignment PIN_W36 -to ddr4b_a[7] -set_location_assignment PIN_T37 -to ddr4b_a[8] -set_location_assignment PIN_V37 -to ddr4b_a[9] -set_location_assignment PIN_U38 -to ddr4b_a[10] -set_location_assignment PIN_W38 -to ddr4b_a[11] -set_location_assignment PIN_P41 -to ddr4b_a[12] -set_location_assignment PIN_L42 -to ddr4b_a[13] -set_location_assignment PIN_N42 -to ddr4b_a[14] -set_location_assignment PIN_M43 -to ddr4b_a[15] -set_location_assignment PIN_P43 -to ddr4b_a[16] -set_location_assignment PIN_N44 -to ddr4b_ba[0] -set_location_assignment PIN_M45 -to ddr4b_ba[1] -set_location_assignment PIN_P45 -to ddr4b_bg[0] -set_location_assignment PIN_M33 -to ddr4b_bg[1] -set_location_assignment PIN_M37 -to ddr4b_ck[0] -set_location_assignment PIN_T45 -to ddr4b_ck[1] -set_location_assignment PIN_P37 -to ddr4b_ck_n[0] -set_location_assignment PIN_V45 -to ddr4b_ck_n[1] -set_location_assignment PIN_L36 -to ddr4b_cke[0] -set_location_assignment PIN_N36 -to ddr4b_cke[1] -set_location_assignment PIN_G42 -to ddr4b_dqs[0] -set_location_assignment PIN_F35 -to ddr4b_dqs[1] -set_location_assignment PIN_A42 -to ddr4b_dqs[2] -set_location_assignment PIN_B35 -to ddr4b_dqs[3] -set_location_assignment PIN_A56 -to ddr4b_dqs[4] -set_location_assignment PIN_T49 -to ddr4b_dqs[5] -set_location_assignment PIN_L56 -to ddr4b_dqs[6] -set_location_assignment PIN_U56 -to ddr4b_dqs[7] -set_location_assignment PIN_M49 -to ddr4b_dqs[8] -set_location_assignment PIN_J42 -to ddr4b_dqs_n[0] -set_location_assignment PIN_H35 -to ddr4b_dqs_n[1] -set_location_assignment PIN_C42 -to ddr4b_dqs_n[2] -set_location_assignment PIN_D35 -to ddr4b_dqs_n[3] -set_location_assignment PIN_C56 -to ddr4b_dqs_n[4] -set_location_assignment PIN_V49 -to ddr4b_dqs_n[5] -set_location_assignment PIN_N56 -to ddr4b_dqs_n[6] -set_location_assignment PIN_W56 -to ddr4b_dqs_n[7] -set_location_assignment PIN_P49 -to ddr4b_dqs_n[8] -set_location_assignment PIN_J44 -to ddr4b_dq[0] -set_location_assignment PIN_J40 -to ddr4b_dq[1] -set_location_assignment PIN_G44 -to ddr4b_dq[2] -set_location_assignment PIN_F41 -to ddr4b_dq[3] -set_location_assignment PIN_H45 -to ddr4b_dq[4] -set_location_assignment PIN_F45 -to ddr4b_dq[5] -set_location_assignment PIN_H41 -to ddr4b_dq[6] -set_location_assignment PIN_G40 -to ddr4b_dq[7] -set_location_assignment PIN_J34 -to ddr4b_dq[8] -set_location_assignment PIN_H37 -to ddr4b_dq[9] -set_location_assignment PIN_H33 -to ddr4b_dq[10] -set_location_assignment PIN_F33 -to ddr4b_dq[11] -set_location_assignment PIN_J38 -to ddr4b_dq[12] -set_location_assignment PIN_G38 -to ddr4b_dq[13] -set_location_assignment PIN_F37 -to ddr4b_dq[14] -set_location_assignment PIN_G34 -to ddr4b_dq[15] -set_location_assignment PIN_D41 -to ddr4b_dq[16] -set_location_assignment PIN_A40 -to ddr4b_dq[17] -set_location_assignment PIN_B45 -to ddr4b_dq[18] -set_location_assignment PIN_C44 -to ddr4b_dq[19] -set_location_assignment PIN_D45 -to ddr4b_dq[20] -set_location_assignment PIN_C40 -to ddr4b_dq[21] -set_location_assignment PIN_A44 -to ddr4b_dq[22] -set_location_assignment PIN_B41 -to ddr4b_dq[23] -set_location_assignment PIN_B33 -to ddr4b_dq[24] -set_location_assignment PIN_A34 -to ddr4b_dq[25] -set_location_assignment PIN_D37 -to ddr4b_dq[26] -set_location_assignment PIN_A38 -to ddr4b_dq[27] -set_location_assignment PIN_D33 -to ddr4b_dq[28] -set_location_assignment PIN_C34 -to ddr4b_dq[29] -set_location_assignment PIN_B37 -to ddr4b_dq[30] -set_location_assignment PIN_C38 -to ddr4b_dq[31] -set_location_assignment PIN_A54 -to ddr4b_dq[32] -set_location_assignment PIN_D55 -to ddr4b_dq[33] -set_location_assignment PIN_C58 -to ddr4b_dq[34] -set_location_assignment PIN_F61 -to ddr4b_dq[35] -set_location_assignment PIN_H61 -to ddr4b_dq[36] -set_location_assignment PIN_C54 -to ddr4b_dq[37] -set_location_assignment PIN_B55 -to ddr4b_dq[38] -set_location_assignment PIN_D59 -to ddr4b_dq[39] -set_location_assignment PIN_U48 -to ddr4b_dq[40] -set_location_assignment PIN_V47 -to ddr4b_dq[41] -set_location_assignment PIN_U52 -to ddr4b_dq[42] -set_location_assignment PIN_W48 -to ddr4b_dq[43] -set_location_assignment PIN_T51 -to ddr4b_dq[44] -set_location_assignment PIN_T47 -to ddr4b_dq[45] -set_location_assignment PIN_W52 -to ddr4b_dq[46] -set_location_assignment PIN_V51 -to ddr4b_dq[47] -set_location_assignment PIN_L58 -to ddr4b_dq[48] -set_location_assignment PIN_L54 -to ddr4b_dq[49] -set_location_assignment PIN_P55 -to ddr4b_dq[50] -set_location_assignment PIN_P59 -to ddr4b_dq[51] -set_location_assignment PIN_N54 -to ddr4b_dq[52] -set_location_assignment PIN_M55 -to ddr4b_dq[53] -set_location_assignment PIN_N58 -to ddr4b_dq[54] -set_location_assignment PIN_M59 -to ddr4b_dq[55] -set_location_assignment PIN_W58 -to ddr4b_dq[56] -set_location_assignment PIN_V59 -to ddr4b_dq[57] -set_location_assignment PIN_U58 -to ddr4b_dq[58] -set_location_assignment PIN_V55 -to ddr4b_dq[59] -set_location_assignment PIN_U54 -to ddr4b_dq[60] -set_location_assignment PIN_T55 -to ddr4b_dq[61] -set_location_assignment PIN_T59 -to ddr4b_dq[62] -set_location_assignment PIN_W54 -to ddr4b_dq[63] -set_location_assignment PIN_L48 -to ddr4b_dq[64] -set_location_assignment PIN_P47 -to ddr4b_dq[65] -set_location_assignment PIN_N48 -to ddr4b_dq[66] -set_location_assignment PIN_M51 -to ddr4b_dq[67] -set_location_assignment PIN_P51 -to ddr4b_dq[68] -set_location_assignment PIN_M47 -to ddr4b_dq[69] -set_location_assignment PIN_L52 -to ddr4b_dq[70] -set_location_assignment PIN_N52 -to ddr4b_dq[71] -set_location_assignment PIN_F43 -to ddr4b_dbi_n[0] -set_location_assignment PIN_G36 -to ddr4b_dbi_n[1] -set_location_assignment PIN_B43 -to ddr4b_dbi_n[2] -set_location_assignment PIN_A36 -to ddr4b_dbi_n[3] -set_location_assignment PIN_B57 -to ddr4b_dbi_n[4] -set_location_assignment PIN_U50 -to ddr4b_dbi_n[5] -set_location_assignment PIN_M57 -to ddr4b_dbi_n[6] -set_location_assignment PIN_T57 -to ddr4b_dbi_n[7] -set_location_assignment PIN_L50 -to ddr4b_dbi_n[8] -set_location_assignment PIN_L34 -to ddr4b_cs_n[0] -set_location_assignment PIN_L38 -to ddr4b_cs_n[1] -set_location_assignment PIN_P33 -to ddr4b_reset_n -set_location_assignment PIN_M35 -to ddr4b_odt[0] -set_location_assignment PIN_P35 -to ddr4b_odt[1] -set_location_assignment PIN_N38 -to ddr4b_par -set_location_assignment PIN_L44 -to ddr4b_alert_n -set_location_assignment PIN_N34 -to ddr4b_act_n -set_location_assignment PIN_J56 -to ddr4b_event_n -set_location_assignment PIN_H55 -to ddr4b_scl -set_location_assignment PIN_B19 -to ddr4b_sda -set_location_assignment PIN_M41 -to ddr4b_rzq - -set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to ddr4b_refclk_p -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[2] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[3] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[4] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[5] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[6] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[7] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[9] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[10] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[11] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[12] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[13] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[14] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[15] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_a[16] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_ba[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_ba[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_bg[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_bg[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4b_ck[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4b_ck[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4b_ck_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4b_ck_n[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_cke[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_cke[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs[8] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs_n[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs_n[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs_n[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs_n[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4b_dqs_n[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[9] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[10] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[11] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[12] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[13] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[14] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[15] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[16] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[17] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[18] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[19] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[20] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[21] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[22] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[23] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[24] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[25] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[26] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[27] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[28] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[29] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[30] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[31] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[32] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[33] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[34] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[35] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[36] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[37] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[38] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[39] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[40] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[41] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[42] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[43] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[44] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[45] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[46] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[47] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[48] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[49] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[50] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[51] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[52] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[53] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[54] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[55] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[56] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[57] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[58] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[59] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[60] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[61] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[62] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[63] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[64] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[65] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[66] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[67] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[68] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[69] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[70] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dq[71] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dbi_n[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dbi_n[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dbi_n[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dbi_n[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dbi_n[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dbi_n[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dbi_n[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dbi_n[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4b_dbi_n[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_cs_n[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_cs_n[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4b_reset_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_odt[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_odt[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_par -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4b_alert_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4b_act_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4b_event_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4b_scl -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4b_sda -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4b_rzq - -# DDR4C -set_location_assignment PIN_DC8 -to ddr4c_refclk_p -set_location_assignment PIN_CV15 -to ddr4c_a[0] -set_location_assignment PIN_CT15 -to ddr4c_a[1] -set_location_assignment PIN_CU14 -to ddr4c_a[2] -set_location_assignment PIN_CR14 -to ddr4c_a[3] -set_location_assignment PIN_CV13 -to ddr4c_a[4] -set_location_assignment PIN_CT13 -to ddr4c_a[5] -set_location_assignment PIN_CU12 -to ddr4c_a[6] -set_location_assignment PIN_CR12 -to ddr4c_a[7] -set_location_assignment PIN_CV11 -to ddr4c_a[8] -set_location_assignment PIN_CT11 -to ddr4c_a[9] -set_location_assignment PIN_CU10 -to ddr4c_a[10] -set_location_assignment PIN_CR10 -to ddr4c_a[11] -set_location_assignment PIN_CY7 -to ddr4c_a[12] -set_location_assignment PIN_DC6 -to ddr4c_a[13] -set_location_assignment PIN_DA6 -to ddr4c_a[14] -set_location_assignment PIN_DB5 -to ddr4c_a[15] -set_location_assignment PIN_CY5 -to ddr4c_a[16] -set_location_assignment PIN_CY3 -to ddr4c_ba[0] -set_location_assignment PIN_CV1 -to ddr4c_ba[1] -set_location_assignment PIN_CT1 -to ddr4c_bg[0] -set_location_assignment PIN_DB15 -to ddr4c_bg[1] -set_location_assignment PIN_DB11 -to ddr4c_ck[0] -set_location_assignment PIN_CV3 -to ddr4c_ck[1] -set_location_assignment PIN_CY11 -to ddr4c_ck_n[0] -set_location_assignment PIN_CT3 -to ddr4c_ck_n[1] -set_location_assignment PIN_DC12 -to ddr4c_cke[0] -set_location_assignment PIN_DA12 -to ddr4c_cke[1] -set_location_assignment PIN_CH27 -to ddr4c_dqs[0] -set_location_assignment PIN_CM27 -to ddr4c_dqs[1] -set_location_assignment PIN_CG20 -to ddr4c_dqs[2] -set_location_assignment PIN_CN20 -to ddr4c_dqs[3] -set_location_assignment PIN_CH13 -to ddr4c_dqs[4] -set_location_assignment PIN_CM13 -to ddr4c_dqs[5] -set_location_assignment PIN_CG6 -to ddr4c_dqs[6] -set_location_assignment PIN_CN6 -to ddr4c_dqs[7] -set_location_assignment PIN_DB27 -to ddr4c_dqs[8] -set_location_assignment PIN_CF27 -to ddr4c_dqs_n[0] -set_location_assignment PIN_CK27 -to ddr4c_dqs_n[1] -set_location_assignment PIN_CE20 -to ddr4c_dqs_n[2] -set_location_assignment PIN_CL20 -to ddr4c_dqs_n[3] -set_location_assignment PIN_CF13 -to ddr4c_dqs_n[4] -set_location_assignment PIN_CK13 -to ddr4c_dqs_n[5] -set_location_assignment PIN_CE6 -to ddr4c_dqs_n[6] -set_location_assignment PIN_CL6 -to ddr4c_dqs_n[7] -set_location_assignment PIN_CY27 -to ddr4c_dqs_n[8] -set_location_assignment PIN_CH25 -to ddr4c_dq[0] -set_location_assignment PIN_CF29 -to ddr4c_dq[1] -set_location_assignment PIN_CG24 -to ddr4c_dq[2] -set_location_assignment PIN_CH29 -to ddr4c_dq[3] -set_location_assignment PIN_CE28 -to ddr4c_dq[4] -set_location_assignment PIN_CF25 -to ddr4c_dq[5] -set_location_assignment PIN_CE24 -to ddr4c_dq[6] -set_location_assignment PIN_CG28 -to ddr4c_dq[7] -set_location_assignment PIN_CN28 -to ddr4c_dq[8] -set_location_assignment PIN_CK25 -to ddr4c_dq[9] -set_location_assignment PIN_CK29 -to ddr4c_dq[10] -set_location_assignment PIN_CM25 -to ddr4c_dq[11] -set_location_assignment PIN_CM29 -to ddr4c_dq[12] -set_location_assignment PIN_CL24 -to ddr4c_dq[13] -set_location_assignment PIN_CN24 -to ddr4c_dq[14] -set_location_assignment PIN_CL28 -to ddr4c_dq[15] -set_location_assignment PIN_CF21 -to ddr4c_dq[16] -set_location_assignment PIN_CE22 -to ddr4c_dq[17] -set_location_assignment PIN_CG18 -to ddr4c_dq[18] -set_location_assignment PIN_CH17 -to ddr4c_dq[19] -set_location_assignment PIN_CF17 -to ddr4c_dq[20] -set_location_assignment PIN_CE18 -to ddr4c_dq[21] -set_location_assignment PIN_CG22 -to ddr4c_dq[22] -set_location_assignment PIN_CH21 -to ddr4c_dq[23] -set_location_assignment PIN_CN18 -to ddr4c_dq[24] -set_location_assignment PIN_CL22 -to ddr4c_dq[25] -set_location_assignment PIN_CM21 -to ddr4c_dq[26] -set_location_assignment PIN_CK17 -to ddr4c_dq[27] -set_location_assignment PIN_CL18 -to ddr4c_dq[28] -set_location_assignment PIN_CK21 -to ddr4c_dq[29] -set_location_assignment PIN_CN22 -to ddr4c_dq[30] -set_location_assignment PIN_CM17 -to ddr4c_dq[31] -set_location_assignment PIN_CF11 -to ddr4c_dq[32] -set_location_assignment PIN_CE14 -to ddr4c_dq[33] -set_location_assignment PIN_CG14 -to ddr4c_dq[34] -set_location_assignment PIN_CF15 -to ddr4c_dq[35] -set_location_assignment PIN_CE10 -to ddr4c_dq[36] -set_location_assignment PIN_CG10 -to ddr4c_dq[37] -set_location_assignment PIN_CH15 -to ddr4c_dq[38] -set_location_assignment PIN_CH11 -to ddr4c_dq[39] -set_location_assignment PIN_CN14 -to ddr4c_dq[40] -set_location_assignment PIN_CM15 -to ddr4c_dq[41] -set_location_assignment PIN_CM11 -to ddr4c_dq[42] -set_location_assignment PIN_CL10 -to ddr4c_dq[43] -set_location_assignment PIN_CL14 -to ddr4c_dq[44] -set_location_assignment PIN_CK15 -to ddr4c_dq[45] -set_location_assignment PIN_CK11 -to ddr4c_dq[46] -set_location_assignment PIN_CN10 -to ddr4c_dq[47] -set_location_assignment PIN_CG4 -to ddr4c_dq[48] -set_location_assignment PIN_CG8 -to ddr4c_dq[49] -set_location_assignment PIN_CF7 -to ddr4c_dq[50] -set_location_assignment PIN_CF3 -to ddr4c_dq[51] -set_location_assignment PIN_CE8 -to ddr4c_dq[52] -set_location_assignment PIN_CH7 -to ddr4c_dq[53] -set_location_assignment PIN_CE4 -to ddr4c_dq[54] -set_location_assignment PIN_CH3 -to ddr4c_dq[55] -set_location_assignment PIN_CM7 -to ddr4c_dq[56] -set_location_assignment PIN_CN8 -to ddr4c_dq[57] -set_location_assignment PIN_CM3 -to ddr4c_dq[58] -set_location_assignment PIN_CL4 -to ddr4c_dq[59] -set_location_assignment PIN_CL8 -to ddr4c_dq[60] -set_location_assignment PIN_CK7 -to ddr4c_dq[61] -set_location_assignment PIN_CN4 -to ddr4c_dq[62] -set_location_assignment PIN_CK3 -to ddr4c_dq[63] -set_location_assignment PIN_DA28 -to ddr4c_dq[64] -set_location_assignment PIN_DB29 -to ddr4c_dq[65] -set_location_assignment PIN_CY25 -to ddr4c_dq[66] -set_location_assignment PIN_DC24 -to ddr4c_dq[67] -set_location_assignment PIN_DA24 -to ddr4c_dq[68] -set_location_assignment PIN_CY29 -to ddr4c_dq[69] -set_location_assignment PIN_DC28 -to ddr4c_dq[70] -set_location_assignment PIN_DB25 -to ddr4c_dq[71] -set_location_assignment PIN_CG26 -to ddr4c_dbi_n[0] -set_location_assignment PIN_CN26 -to ddr4c_dbi_n[1] -set_location_assignment PIN_CH19 -to ddr4c_dbi_n[2] -set_location_assignment PIN_CM19 -to ddr4c_dbi_n[3] -set_location_assignment PIN_CG12 -to ddr4c_dbi_n[4] -set_location_assignment PIN_CN12 -to ddr4c_dbi_n[5] -set_location_assignment PIN_CH5 -to ddr4c_dbi_n[6] -set_location_assignment PIN_CM5 -to ddr4c_dbi_n[7] -set_location_assignment PIN_DC26 -to ddr4c_dbi_n[8] -set_location_assignment PIN_DC14 -to ddr4c_cs_n[0] -set_location_assignment PIN_DC10 -to ddr4c_cs_n[1] -set_location_assignment PIN_CY15 -to ddr4c_reset_n -set_location_assignment PIN_DB13 -to ddr4c_odt[0] -set_location_assignment PIN_CY13 -to ddr4c_odt[1] -set_location_assignment PIN_DA10 -to ddr4c_par -set_location_assignment PIN_DA4 -to ddr4c_alert_n -set_location_assignment PIN_DA14 -to ddr4c_act_n -set_location_assignment PIN_CR20 -to ddr4c_event_n -set_location_assignment PIN_CT21 -to ddr4c_scl -set_location_assignment PIN_CU20 -to ddr4c_sda -set_location_assignment PIN_DB7 -to ddr4c_rzq - -set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to ddr4c_refclk_p -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[2] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[3] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[4] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[5] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[6] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[7] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[9] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[10] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[11] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[12] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[13] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[14] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[15] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_a[16] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_ba[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_ba[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_bg[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_bg[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4c_ck[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4c_ck[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4c_ck_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4c_ck_n[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_cke[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_cke[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs[8] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs_n[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs_n[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs_n[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs_n[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4c_dqs_n[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[9] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[10] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[11] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[12] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[13] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[14] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[15] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[16] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[17] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[18] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[19] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[20] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[21] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[22] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[23] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[24] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[25] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[26] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[27] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[28] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[29] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[30] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[31] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[32] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[33] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[34] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[35] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[36] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[37] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[38] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[39] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[40] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[41] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[42] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[43] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[44] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[45] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[46] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[47] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[48] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[49] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[50] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[51] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[52] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[53] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[54] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[55] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[56] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[57] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[58] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[59] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[60] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[61] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[62] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[63] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[64] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[65] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[66] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[67] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[68] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[69] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[70] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dq[71] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dbi_n[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dbi_n[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dbi_n[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dbi_n[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dbi_n[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dbi_n[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dbi_n[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dbi_n[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4c_dbi_n[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_cs_n[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_cs_n[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4c_reset_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_odt[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_odt[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_par -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4c_alert_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4c_act_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4c_event_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4c_scl -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4c_sda -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4c_rzq - -# DDR4D -set_location_assignment PIN_CN38 -to ddr4d_refclk_p -set_location_assignment PIN_CH31 -to ddr4d_a[0] -set_location_assignment PIN_CF31 -to ddr4d_a[1] -set_location_assignment PIN_CG32 -to ddr4d_a[2] -set_location_assignment PIN_CE32 -to ddr4d_a[3] -set_location_assignment PIN_CH33 -to ddr4d_a[4] -set_location_assignment PIN_CF33 -to ddr4d_a[5] -set_location_assignment PIN_CG34 -to ddr4d_a[6] -set_location_assignment PIN_CE34 -to ddr4d_a[7] -set_location_assignment PIN_CH35 -to ddr4d_a[8] -set_location_assignment PIN_CF35 -to ddr4d_a[9] -set_location_assignment PIN_CG36 -to ddr4d_a[10] -set_location_assignment PIN_CE36 -to ddr4d_a[11] -set_location_assignment PIN_CK39 -to ddr4d_a[12] -set_location_assignment PIN_CN40 -to ddr4d_a[13] -set_location_assignment PIN_CL40 -to ddr4d_a[14] -set_location_assignment PIN_CM41 -to ddr4d_a[15] -set_location_assignment PIN_CK41 -to ddr4d_a[16] -set_location_assignment PIN_CL42 -to ddr4d_ba[0] -set_location_assignment PIN_CM43 -to ddr4d_ba[1] -set_location_assignment PIN_CK43 -to ddr4d_bg[0] -set_location_assignment PIN_CM31 -to ddr4d_bg[1] -set_location_assignment PIN_CM35 -to ddr4d_ck[0] -set_location_assignment PIN_CH43 -to ddr4d_ck[1] -set_location_assignment PIN_CK35 -to ddr4d_ck_n[0] -set_location_assignment PIN_CF43 -to ddr4d_ck_n[1] -set_location_assignment PIN_CN34 -to ddr4d_cke[0] -set_location_assignment PIN_CL34 -to ddr4d_cke[1] -set_location_assignment PIN_CG54 -to ddr4d_dqs[0] -set_location_assignment PIN_CN54 -to ddr4d_dqs[1] -set_location_assignment PIN_CH47 -to ddr4d_dqs[2] -set_location_assignment PIN_DB47 -to ddr4d_dqs[3] -set_location_assignment PIN_DC40 -to ddr4d_dqs[4] -set_location_assignment PIN_CM47 -to ddr4d_dqs[5] -set_location_assignment PIN_DB33 -to ddr4d_dqs[6] -set_location_assignment PIN_CV33 -to ddr4d_dqs[7] -set_location_assignment PIN_CU40 -to ddr4d_dqs[8] -set_location_assignment PIN_CE54 -to ddr4d_dqs_n[0] -set_location_assignment PIN_CL54 -to ddr4d_dqs_n[1] -set_location_assignment PIN_CF47 -to ddr4d_dqs_n[2] -set_location_assignment PIN_CY47 -to ddr4d_dqs_n[3] -set_location_assignment PIN_DA40 -to ddr4d_dqs_n[4] -set_location_assignment PIN_CK47 -to ddr4d_dqs_n[5] -set_location_assignment PIN_CY33 -to ddr4d_dqs_n[6] -set_location_assignment PIN_CT33 -to ddr4d_dqs_n[7] -set_location_assignment PIN_CR40 -to ddr4d_dqs_n[8] -set_location_assignment PIN_CF57 -to ddr4d_dq[0] -set_location_assignment PIN_CG56 -to ddr4d_dq[1] -set_location_assignment PIN_CG52 -to ddr4d_dq[2] -set_location_assignment PIN_CH53 -to ddr4d_dq[3] -set_location_assignment PIN_CF53 -to ddr4d_dq[4] -set_location_assignment PIN_CE56 -to ddr4d_dq[5] -set_location_assignment PIN_CE52 -to ddr4d_dq[6] -set_location_assignment PIN_CH57 -to ddr4d_dq[7] -set_location_assignment PIN_CM57 -to ddr4d_dq[8] -set_location_assignment PIN_CN56 -to ddr4d_dq[9] -set_location_assignment PIN_CM53 -to ddr4d_dq[10] -set_location_assignment PIN_CL52 -to ddr4d_dq[11] -set_location_assignment PIN_CK57 -to ddr4d_dq[12] -set_location_assignment PIN_CL56 -to ddr4d_dq[13] -set_location_assignment PIN_CN52 -to ddr4d_dq[14] -set_location_assignment PIN_CK53 -to ddr4d_dq[15] -set_location_assignment PIN_CH45 -to ddr4d_dq[16] -set_location_assignment PIN_CE50 -to ddr4d_dq[17] -set_location_assignment PIN_CF49 -to ddr4d_dq[18] -set_location_assignment PIN_CH49 -to ddr4d_dq[19] -set_location_assignment PIN_CF45 -to ddr4d_dq[20] -set_location_assignment PIN_CG46 -to ddr4d_dq[21] -set_location_assignment PIN_CE46 -to ddr4d_dq[22] -set_location_assignment PIN_CG50 -to ddr4d_dq[23] -set_location_assignment PIN_DA50 -to ddr4d_dq[24] -set_location_assignment PIN_CY49 -to ddr4d_dq[25] -set_location_assignment PIN_DC46 -to ddr4d_dq[26] -set_location_assignment PIN_CY45 -to ddr4d_dq[27] -set_location_assignment PIN_DC50 -to ddr4d_dq[28] -set_location_assignment PIN_DB49 -to ddr4d_dq[29] -set_location_assignment PIN_DA46 -to ddr4d_dq[30] -set_location_assignment PIN_DB45 -to ddr4d_dq[31] -set_location_assignment PIN_CY43 -to ddr4d_dq[32] -set_location_assignment PIN_DA42 -to ddr4d_dq[33] -set_location_assignment PIN_DC38 -to ddr4d_dq[34] -set_location_assignment PIN_DA38 -to ddr4d_dq[35] -set_location_assignment PIN_DB43 -to ddr4d_dq[36] -set_location_assignment PIN_DC42 -to ddr4d_dq[37] -set_location_assignment PIN_CY39 -to ddr4d_dq[38] -set_location_assignment PIN_DB39 -to ddr4d_dq[39] -set_location_assignment PIN_CM45 -to ddr4d_dq[40] -set_location_assignment PIN_CN50 -to ddr4d_dq[41] -set_location_assignment PIN_CL46 -to ddr4d_dq[42] -set_location_assignment PIN_CK49 -to ddr4d_dq[43] -set_location_assignment PIN_CK45 -to ddr4d_dq[44] -set_location_assignment PIN_CM49 -to ddr4d_dq[45] -set_location_assignment PIN_CN46 -to ddr4d_dq[46] -set_location_assignment PIN_CL50 -to ddr4d_dq[47] -set_location_assignment PIN_DA36 -to ddr4d_dq[48] -set_location_assignment PIN_DC32 -to ddr4d_dq[49] -set_location_assignment PIN_CY31 -to ddr4d_dq[50] -set_location_assignment PIN_DB31 -to ddr4d_dq[51] -set_location_assignment PIN_CY35 -to ddr4d_dq[52] -set_location_assignment PIN_DC36 -to ddr4d_dq[53] -set_location_assignment PIN_DB35 -to ddr4d_dq[54] -set_location_assignment PIN_DA32 -to ddr4d_dq[55] -set_location_assignment PIN_CT31 -to ddr4d_dq[56] -set_location_assignment PIN_CR36 -to ddr4d_dq[57] -set_location_assignment PIN_CV35 -to ddr4d_dq[58] -set_location_assignment PIN_CT35 -to ddr4d_dq[59] -set_location_assignment PIN_CU32 -to ddr4d_dq[60] -set_location_assignment PIN_CV31 -to ddr4d_dq[61] -set_location_assignment PIN_CR32 -to ddr4d_dq[62] -set_location_assignment PIN_CU36 -to ddr4d_dq[63] -set_location_assignment PIN_CV39 -to ddr4d_dq[64] -set_location_assignment PIN_CR42 -to ddr4d_dq[65] -set_location_assignment PIN_CT43 -to ddr4d_dq[66] -set_location_assignment PIN_CV43 -to ddr4d_dq[67] -set_location_assignment PIN_CR38 -to ddr4d_dq[68] -set_location_assignment PIN_CT39 -to ddr4d_dq[69] -set_location_assignment PIN_CU42 -to ddr4d_dq[70] -set_location_assignment PIN_CU38 -to ddr4d_dq[71] -set_location_assignment PIN_CH55 -to ddr4d_dbi_n[0] -set_location_assignment PIN_CM55 -to ddr4d_dbi_n[1] -set_location_assignment PIN_CG48 -to ddr4d_dbi_n[2] -set_location_assignment PIN_DC48 -to ddr4d_dbi_n[3] -set_location_assignment PIN_DB41 -to ddr4d_dbi_n[4] -set_location_assignment PIN_CN48 -to ddr4d_dbi_n[5] -set_location_assignment PIN_DC34 -to ddr4d_dbi_n[6] -set_location_assignment PIN_CU34 -to ddr4d_dbi_n[7] -set_location_assignment PIN_CV41 -to ddr4d_dbi_n[8] -set_location_assignment PIN_CN32 -to ddr4d_cs_n[0] -set_location_assignment PIN_CN36 -to ddr4d_cs_n[1] -set_location_assignment PIN_CK31 -to ddr4d_reset_n -set_location_assignment PIN_CM33 -to ddr4d_odt[0] -set_location_assignment PIN_CK33 -to ddr4d_odt[1] -set_location_assignment PIN_CL36 -to ddr4d_par -set_location_assignment PIN_CN42 -to ddr4d_alert_n -set_location_assignment PIN_CL32 -to ddr4d_act_n -set_location_assignment PIN_CY53 -to ddr4d_event_n -set_location_assignment PIN_DC54 -to ddr4d_scl -set_location_assignment PIN_DB53 -to ddr4d_sda -set_location_assignment PIN_CM39 -to ddr4d_rzq - -set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to ddr4d_refclk_p -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[2] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[3] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[4] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[5] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[6] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[7] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[9] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[10] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[11] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[12] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[13] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[14] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[15] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_a[16] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_ba[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_ba[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_bg[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_bg[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4d_ck[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4d_ck[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4d_ck_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to ddr4d_ck_n[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_cke[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_cke[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs[8] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs_n[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs_n[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs_n[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs_n[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to ddr4d_dqs_n[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[9] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[10] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[11] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[12] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[13] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[14] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[15] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[16] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[17] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[18] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[19] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[20] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[21] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[22] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[23] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[24] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[25] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[26] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[27] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[28] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[29] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[30] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[31] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[32] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[33] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[34] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[35] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[36] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[37] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[38] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[39] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[40] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[41] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[42] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[43] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[44] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[45] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[46] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[47] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[48] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[49] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[50] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[51] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[52] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[53] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[54] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[55] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[56] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[57] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[58] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[59] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[60] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[61] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[62] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[63] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[64] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[65] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[66] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[67] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[68] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[69] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[70] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dq[71] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dbi_n[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dbi_n[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dbi_n[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dbi_n[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dbi_n[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dbi_n[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dbi_n[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dbi_n[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to ddr4d_dbi_n[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_cs_n[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_cs_n[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4d_reset_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_odt[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_odt[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_par -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4d_alert_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to ddr4d_act_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4d_event_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4d_scl -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4d_sda -set_instance_assignment -name IO_STANDARD "1.2 V" -to ddr4d_rzq diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.sdc b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.sdc deleted file mode 100644 index df0e8cbd4..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.sdc +++ /dev/null @@ -1,102 +0,0 @@ -# Timing constraints for the Terasic DE10-Agilex FPGA development board - -set_time_format -unit ns -decimal_places 3 - -# Clock constraints -create_clock -period 10.000 -name "clk_100_b2a" [ get_ports "clk_100_b2a" ] -create_clock -period 20.000 -name "clk_50_b3a" [ get_ports "clk_50_b3a" ] -create_clock -period 20.000 -name "clk_50_b3c" [ get_ports "clk_50_b3c" ] -create_clock -period 32.552 -name "clk_30m72" [ get_ports "clk_30m72" ] -create_clock -period 20.000 -name "clk_from_si5397a_0" [ get_ports "clk_from_si5397a_p[0]" ] -create_clock -period 20.000 -name "clk_from_si5397a_1" [ get_ports "clk_from_si5397a_p[1]" ] - -create_clock -period 10.000 -name "pcie_refclk_0" [ get_ports "pcie_refclk_p[0]" ] -create_clock -period 10.000 -name "pcie_refclk_1" [ get_ports "pcie_refclk_p[1]" ] - -create_clock -period 6.400 -name "qsfpdda_refclk" [ get_ports "qsfpdda_refclk_p" ] -create_clock -period 6.400 -name "qsfpddb_refclk" [ get_ports "qsfpddb_refclk_p" ] -create_clock -period 6.400 -name "qsfpddrsv_refclk" [ get_ports "qsfpddrsv_refclk_p" ] - -create_clock -period 30.000 -name "ddr4a_refclk" [ get_ports "ddr4a_refclk_p" ] -create_clock -period 30.000 -name "ddr4b_refclk" [ get_ports "ddr4b_refclk_p" ] -create_clock -period 30.000 -name "ddr4c_refclk" [ get_ports "ddr4c_refclk_p" ] -create_clock -period 30.000 -name "ddr4d_refclk" [ get_ports "ddr4d_refclk_p" ] - -derive_clock_uncertainty - -set_clock_groups -asynchronous -group [ get_clocks "clk_100_b2a" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_50_b3a" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_50_b3c" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_30m72" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_from_si5397a_0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_from_si5397a_1" ] - -set_clock_groups -asynchronous -group [ get_clocks "pcie_refclk_0" ] -set_clock_groups -asynchronous -group [ get_clocks "pcie_refclk_1" ] - -set_clock_groups -asynchronous -group [ get_clocks "qsfpdda_refclk" ] -set_clock_groups -asynchronous -group [ get_clocks "qsfpddb_refclk" ] -set_clock_groups -asynchronous -group [ get_clocks "qsfpddrsv_refclk" ] - -set_clock_groups -asynchronous -group [ get_clocks "ddr4a_refclk" ] -set_clock_groups -asynchronous -group [ get_clocks "ddr4b_refclk" ] -set_clock_groups -asynchronous -group [ get_clocks "ddr4c_refclk" ] -set_clock_groups -asynchronous -group [ get_clocks "ddr4d_refclk" ] - -# JTAG constraints -# create_clock -name "altera_reserved_tck" -period 40.800 "altera_reserved_tck" - -# set_clock_groups -asynchronous -group [get_clocks "altera_reserved_tck"] - -# IO constraints -set_false_path -from "cpu_resetn" -set_false_path -from "button[*]" -set_false_path -from "sw[*]" -set_false_path -to "led[*]" -set_false_path -to "led_bracket[*]" - -set_false_path -from "pcie_perst_n" - - -source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc - -# clocking infrastructure -constrain_sync_reset_inst "sync_reset_100mhz_inst" -constrain_sync_reset_inst "ptp_rst_reset_sync_inst" - -# PCIe clock -set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_ptile_ast_0|inst|inst|maib_and_tile|xcvr_hip_native|rx_ch15" ] - -# E-Tile MACs -set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_refclk" ] -set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_outclk0" ] - -proc constrain_etile_mac_dual_quad { inst } { - puts "Inserting timing constraints for MAC quad $inst" - - foreach mac {mac_02_inst mac_13_inst} { - for {set i 0} {$i < 4} {incr i} { - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ] - } - - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp_plloff|tx_transfer_clk|ch0" ] - } - - for {set i 0} {$i < 8} {incr i} { - constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_reset_sync_inst" - constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_ptp_reset_sync_inst" - constrain_sync_reset_inst "$inst|mac_ch[$i].mac_rx_ptp_reset_sync_inst" - } -} - -constrain_etile_mac_dual_quad "qsfpdda_mac_inst" -constrain_etile_mac_dual_quad "qsfpddb_mac_inst" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/ip/pcie.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/ip/pcie.tcl deleted file mode 100644 index af4fd3ea9..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/ip/pcie.tcl +++ /dev/null @@ -1,2294 +0,0 @@ -package require -exact qsys 21.3 - -# create the system "pcie" -proc do_create_pcie {} { - # create the system - create_system pcie - set_project_property DEVICE {AGFB014R24B2E2V} - set_project_property DEVICE_FAMILY {Agilex} - set_project_property HIDE_FROM_IP_CATALOG {true} - set_use_testbench_naming_pattern 0 {} - - # add HDL parameters - - # add the components - add_instance intel_pcie_ptile_ast_0 intel_pcie_ptile_ast - set_instance_parameter_value intel_pcie_ptile_ast_0 {aib_csr_top_dfd_ctrl_src_sel_hwtcl} {cfg_avmm_src} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aib_csr_top_ecc_enable_mode_hwtcl} {Disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibnd_rx_sup_mode_hwtcl} {engineering_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibnd_tx_sup_mode_hwtcl} {engineering_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibwraux_top_wrp_dft_aux_en_hwtcl} {disable_dft} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibwraux_top_wrp_dft_dll_osc_dftsel_hwtcl} {disable_dll_osc_dftsel} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibwraux_top_wrp_dft_osc_dftcounter_hwtcl} {disable_osc_dftcounter} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibwraux_top_wrp_redundancy_en_hwtcl} {Disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {apps_type_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {avmm_enabled_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_adptwrap_dummy_func_mode_hwtcl} {c3adpt_disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_adptwrap_dummy_sup_mode_hwtcl} {advanced_user_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_aibio_dummy_sup_mode_hwtcl} {engineering_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_10g_rx_crc32_err_rst_val_hwtcl} {set0_reset_to_one_crc32} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_8g_sigdet_out_rst_val_hwtcl} {set0_reset_to_one_sigdet} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_ltd_b_rst_val_hwtcl} {set0_reset_to_one_ltdb} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_ltr_rst_val_hwtcl} {set0_reset_to_one_ltr} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_rx_fifo_align_clr_rst_val_hwtcl} {set0_reset_to_one_alignclr} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_rxfifowr_post_ct_sel_hwtcl} {set0_rxfifowr_post_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_rxfifowr_pre_ct_sel_hwtcl} {set0_rxfifowr_pre_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_fsr_pld_8g_sigdet_out_rst_val_hwtcl} {set1_reset_to_one_sigdet} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_rxfiford_post_ct_sel_hwtcl} {set1_rxfiford_post_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_rxfifowr_post_ct_sel_hwtcl} {set1_rxfifowr_post_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_txfiford_pre_ct_sel_hwtcl} {set1_txfiford_pre_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_txfifowr_from_aib_sel_hwtcl} {set1_txfifowr_from_aib} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit0_rst_val_hwtcl} {set0_reset_to_one_hfsrin0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit1_rst_val_hwtcl} {set0_reset_to_one_hfsrin1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit2_rst_val_hwtcl} {set0_reset_to_one_hfsrin2} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit3_rst_val_hwtcl} {set0_reset_to_one_hfsrin3} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit0_rst_val_hwtcl} {set0_reset_to_one_hfsrout0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit1_rst_val_hwtcl} {set0_reset_to_one_hfsrout1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit2_rst_val_hwtcl} {set0_reset_to_one_hfsrout2} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit3_rst_val_hwtcl} {set0_reset_to_one_hfsrout3} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_mask_tx_pll_rst_val_hwtcl} {set0_reset_to_one_maskpll} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit0_rst_val_hwtcl} {set1_reset_to_one_hfsrin0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit1_rst_val_hwtcl} {set1_reset_to_one_hfsrin1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit2_rst_val_hwtcl} {set1_reset_to_one_hfsrin2} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit3_rst_val_hwtcl} {set1_reset_to_one_hfsrin3} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit0_rst_val_hwtcl} {set1_reset_to_one_hfsrout0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit1_rst_val_hwtcl} {set1_reset_to_one_hfsrout1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit2_rst_val_hwtcl} {set1_reset_to_one_hfsrout2} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit3_rst_val_hwtcl} {set1_reset_to_one_hfsrout3} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_mask_tx_pll_rst_val_hwtcl} {set1_reset_to_one_maskpll} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bfm_drive_interface_clk_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bfm_drive_interface_pin_perst_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bfm_drive_interface_pipe_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bfm_drive_interface_test_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {chosen_devkit_hwtcl} {NONE} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_avmm_enabled_virtio_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_cap_ext_tag_supp_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_ceb_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_cvp_user_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_10bit_tag_support_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_app_xfer_pending_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_apps_pm_xmt_turnoff_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_apps_ready_entr_l23_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_cii_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_cpl_timeout_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_ecc_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_error_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_hotplug_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_legacy_int_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_legacy_interrupt_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_multi_func_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_pld_warm_rst_rdy_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_power_mgnt_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_prs_event_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_rx_buffer_limit_ports_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_sriov_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_test_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_test_out_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_virtio_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf0} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf1} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf2} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf3} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf4} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf5} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf6} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf7} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf0} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf1} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf2} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf3} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf4} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf5} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf6} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf7} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_flr_cap_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_hip_reconfig_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar0_address_width_user_hwtcl} {24} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar0_type_user_hwtcl} {64-bit prefetchable memory} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_class_code_hwtcl} {131072} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_dsp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_dsp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_gen3_eq_pset_req_vec_atg4_hwtcl} {624} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_gen3_eq_pset_req_vec_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_offset_hwtcl} {12288.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_offset_hwtcl} {8192.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_size_hwtcl} {31} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_type0_device_id_hwtcl} {4097} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_type0_vendor_id_hwtcl} {4660} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_cap_phy_slot_num_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_cap_port_num_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_cap_slot_power_limit_value_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_slot_imp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pme_support_hwtcl} {15} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_revision_id_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_rp_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_subsys_dev_id_hwtcl} {45066} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_subsys_vendor_id_hwtcl} {4466} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_usp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_usp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf_ceb_pointer_addr_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf_no_soft_rst_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_sn_ser_num_reg_1_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_sn_ser_num_reg_2_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_total_pf_count_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_use_ast_parity_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_user_mode_to_pld_in_use_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_user_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_user_pcie_cap_ep_l1_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_user_vsec_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_vf_ceb_pointer_addr_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtio_start_byte_address_hwtcl} {72} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_drop_vendor0_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_drop_vendor1_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_ecrc_strip_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_ep_native_hwtcl} {Native} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_hrdrstctrl_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_maxpayload_size_hwtcl} {512} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_num_of_lanes_hwtcl} {num_1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_io_decode_hwtcl} {io16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_ltr_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_msix_enable_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_prefetch_decode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_ras_des_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_sn_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_txeq_mode_hwtcl} {eq_fom_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_uc_calibration_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_vsec_next_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_cap_ext_tag_supp_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_cvp_user_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_app_xfer_pending_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_apps_pm_xmt_turnoff_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_apps_ready_entr_l23_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_cpl_timeout_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_ecc_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_error_intf_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_hotplug_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_legacy_int_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_legacy_interrupt_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_pld_warm_rst_rdy_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_power_mgnt_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_rx_buffer_limit_ports_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_test_intf_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_test_out_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_flr_cap_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_hip_reconfig_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_dsp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_dsp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_gen3_eq_pset_req_vec_atg4_hwtcl} {624} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_gen3_eq_pset_req_vec_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_type0_vendor_id_hwtcl} {4466} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_cap_phy_slot_num_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_cap_port_num_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_cap_slot_power_limit_value_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_slot_imp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_revision_id_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_rp_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_tph_req_cap_st_table_loc_1_hwtcl} {pf0_not_in_msix_table} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_usp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_usp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf1_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf1vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf2_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf2vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf3_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf3vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf4_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf4vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf5_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf5vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf6_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf6vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf7_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf7vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_sn_ser_num_reg_1_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_sn_ser_num_reg_2_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_use_ast_parity_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_user_mode_to_pld_in_use_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_user_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_user_pcie_cap_ep_l1_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_user_vsec_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_drop_vendor0_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_drop_vendor1_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_ecrc_strip_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_ep_native_hwtcl} {Native} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_hrdrstctrl_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_maxpayload_size_hwtcl} {512} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_num_of_lanes_hwtcl} {num_1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_io_decode_hwtcl} {io16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_msix_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_prefetch_decode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_ras_des_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_sn_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_txeq_mode_hwtcl} {eq_fom_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_uc_calibration_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_vsec_next_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_cap_ext_tag_supp_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_cvp_user_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_app_xfer_pending_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_apps_pm_xmt_turnoff_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_apps_ready_entr_l23_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_cpl_timeout_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_ecc_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_error_intf_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_hotplug_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_legacy_int_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_legacy_interrupt_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_pld_warm_rst_rdy_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_power_mgnt_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_rx_buffer_limit_ports_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_test_intf_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_test_out_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_flr_cap_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_hip_reconfig_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_dsp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_dsp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_gen3_eq_pset_req_vec_atg4_hwtcl} {624} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_gen3_eq_pset_req_vec_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_type0_vendor_id_hwtcl} {4466} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_cap_phy_slot_num_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_cap_port_num_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_cap_slot_power_limit_value_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_slot_imp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_revision_id_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_rp_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_tph_req_cap_st_table_loc_1_hwtcl} {pf0_not_in_msix_table} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_usp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_usp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf1_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf1vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf2_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf2vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf3_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf3vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf4_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf4vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf5_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf5vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf6_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf6vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf7_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf7vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_sn_ser_num_reg_1_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_sn_ser_num_reg_2_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_use_ast_parity_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_user_mode_to_pld_in_use_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_user_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_user_pcie_cap_ep_l1_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_user_vsec_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_drop_vendor0_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_drop_vendor1_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_ecrc_strip_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_ep_native_hwtcl} {Native} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_hrdrstctrl_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_maxpayload_size_hwtcl} {512} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_num_of_lanes_hwtcl} {num_1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_io_decode_hwtcl} {io16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_msix_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_prefetch_decode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_ras_des_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_sn_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_txeq_mode_hwtcl} {eq_fom_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_uc_calibration_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_vsec_next_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_avmm_enabled_virtio_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_cap_ext_tag_supp_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_ceb_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_cvp_user_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_app_xfer_pending_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_apps_pm_xmt_turnoff_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_apps_ready_entr_l23_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_cii_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_cpl_timeout_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_ecc_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_error_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_hotplug_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_legacy_int_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_legacy_interrupt_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_multi_func_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_pld_warm_rst_rdy_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_power_mgnt_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_prs_event_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_rx_buffer_limit_ports_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_sriov_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_test_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_test_out_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_virtio_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf0} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf1} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf2} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf3} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf4} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf5} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf6} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf7} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf0} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf1} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf2} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf3} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf4} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf5} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf6} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf7} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_flr_cap_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_hip_reconfig_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar0_address_width_user_hwtcl} {16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar0_type_user_hwtcl} {64-bit prefetchable memory} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_dsp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_dsp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_gen3_eq_pset_req_vec_atg4_hwtcl} {624} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_gen3_eq_pset_req_vec_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_type0_vendor_id_hwtcl} {4466} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_cap_phy_slot_num_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_cap_port_num_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_cap_slot_power_limit_value_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_slot_imp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_revision_id_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_rp_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_usp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_usp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf_ceb_pointer_addr_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf_no_soft_rst_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_refclk_init_active_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_sn_ser_num_reg_1_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_sn_ser_num_reg_2_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_total_pf_count_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_use_ast_parity_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_user_mode_to_pld_in_use_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_user_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_user_pcie_cap_ep_l1_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_user_vsec_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_vf_ceb_pointer_addr_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtio_start_byte_address_hwtcl} {72} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_drop_vendor0_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_drop_vendor1_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_ecrc_strip_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_ep_native_hwtcl} {Native} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_hrdrstctrl_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_maxpayload_size_hwtcl} {512} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_num_of_lanes_hwtcl} {num_1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_io_decode_hwtcl} {io16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_ltr_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_prefetch_decode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_ras_des_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_sn_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_txeq_mode_hwtcl} {eq_fom_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_uc_calibration_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_vsec_next_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {design_environment} {NATIVE} - set_instance_parameter_value intel_pcie_ptile_ast_0 {enable_example_design_sim_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {enable_example_design_synth_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {enable_example_design_tb_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {enable_switch_port_termination_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {example_design_mode_hwtcl} {PIO/SRIOV} - set_instance_parameter_value intel_pcie_ptile_ast_0 {g3_pld_clkfreq_user_hwtcl} {250MHz} - set_instance_parameter_value intel_pcie_ptile_ast_0 {g4_pld_clkfreq_user_hwtcl} {400MHz} - set_instance_parameter_value intel_pcie_ptile_ast_0 {hrc_cpll_ena_warm_reset_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {hrc_pin_perst_is_full_rst_hwtcl} {true} - set_instance_parameter_value intel_pcie_ptile_ast_0 {if_pldadapt_hip_mode_hwtcl} {user_chnl} - set_instance_parameter_value intel_pcie_ptile_ast_0 {is_cvp_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {mcdma_enabled_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {mlab_ram_block_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pcs_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pld_clrpcs_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pldadapt_rx_aib_clk2_sel_hwtcl} {aib_clk2_pld_pcs_rx_clk_out} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pldadapt_rx_pld_clk1_sel_hwtcl} {pld_clk1_dcm} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pldadapt_tx_pld_clk1_sel_hwtcl} {pld_clk1_dcm} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_0_bs_mode_hwtcl} {bs_ac_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_0_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_1_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_2_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_3_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_4_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {ptile_debug_toolkit_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {ptile_enable_pciess_register_access_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {ptile_link_insp_avmm_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {ref_clk_mode_hwtcl} {ref_clk_separate} - set_instance_parameter_value intel_pcie_ptile_ast_0 {rx_dft_hssitestip_dll_dcc_en_hwtcl} {disable_dft} - set_instance_parameter_value intel_pcie_ptile_ast_0 {select_design_example_rtl_lang_hwtcl} {Verilog} - set_instance_parameter_value intel_pcie_ptile_ast_0 {serial_sim_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {sim_mode_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {standard_interface_selection_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {subtopology_pcie_x8_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {sup_mode_hwtcl} {user_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {targeted_devkit_hwtcl} {NONE} - set_instance_parameter_value intel_pcie_ptile_ast_0 {top_4_es_mode_hwtcl} {common_ref_clk} - set_instance_parameter_value intel_pcie_ptile_ast_0 {top_topology_hwtcl} {Gen3x16, Interface - 512 bit} - set_instance_parameter_value intel_pcie_ptile_ast_0 {tx_dfd_dll_dcc_en_hwtcl} {disable_dfd} - set_instance_parameter_value intel_pcie_ptile_ast_0 {tx_dft_hssitestip_dll_dcc_en_hwtcl} {disable_dft} - set_instance_parameter_value intel_pcie_ptile_ast_0 {upi_core_lpbk_mode_hwtcl} {lpbk_comp_slave} - set_instance_parameter_value intel_pcie_ptile_ast_0 {upi_core_u_upiphy_agent_slow_mode_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {virtual_rp_ep_mode_hwtcl} {Native Endpoint} - set_instance_parameter_value intel_pcie_ptile_ast_0 {virtual_sris_enable_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {virtual_tlp_bypass_en_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch0_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch10_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch11_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch12_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch13_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch14_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch15_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch16_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch17_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch18_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch19_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch1_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch20_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch21_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch22_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch23_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch2_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch3_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch4_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch5_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch6_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch7_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch8_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch9_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibcmn_top_u_bcmrbc_adptwrap_dummy_powermode_ac_hwtcl} {disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {xcvr_reconfig_user_hwtcl} {0} - set_instance_property intel_pcie_ptile_ast_0 AUTO_EXPORT true - - # add wirelevel expressions - - # preserve ports for debug - - # add the exports - set_interface_property p0_rx_st EXPORT_OF intel_pcie_ptile_ast_0.p0_rx_st - set_interface_property p0_rx_st_misc EXPORT_OF intel_pcie_ptile_ast_0.p0_rx_st_misc - set_interface_property p0_tx_st EXPORT_OF intel_pcie_ptile_ast_0.p0_tx_st - set_interface_property p0_tx_st_misc EXPORT_OF intel_pcie_ptile_ast_0.p0_tx_st_misc - set_interface_property p0_tx_cred EXPORT_OF intel_pcie_ptile_ast_0.p0_tx_cred - set_interface_property p0_config_tl EXPORT_OF intel_pcie_ptile_ast_0.p0_config_tl - set_interface_property p0_reset_status_n EXPORT_OF intel_pcie_ptile_ast_0.p0_reset_status_n - set_interface_property p0_pin_perst EXPORT_OF intel_pcie_ptile_ast_0.p0_pin_perst - set_interface_property p0_hip_status EXPORT_OF intel_pcie_ptile_ast_0.p0_hip_status - set_interface_property hip_serial EXPORT_OF intel_pcie_ptile_ast_0.hip_serial - set_interface_property coreclkout_hip EXPORT_OF intel_pcie_ptile_ast_0.coreclkout_hip - set_interface_property refclk0 EXPORT_OF intel_pcie_ptile_ast_0.refclk0 - set_interface_property refclk1 EXPORT_OF intel_pcie_ptile_ast_0.refclk1 - set_interface_property pin_perst EXPORT_OF intel_pcie_ptile_ast_0.pin_perst - set_interface_property ninit_done EXPORT_OF intel_pcie_ptile_ast_0.ninit_done - - # set values for exposed HDL parameters - - # set the the module properties - set_module_property BONUS_DATA { - - - - - -} - set_module_property FILE {pcie.ip} - set_module_property GENERATION_ID {0x00000000} - set_module_property NAME {pcie} - - # save the system - sync_sysinfo_parameters - save_system pcie -} - -proc do_set_exported_interface_sysinfo_parameters {} { -} - -# create all the systems, from bottom up -do_create_pcie - -# set system info parameters on exported interface, from bottom up -do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/ip/reset_release.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/ip/reset_release.tcl deleted file mode 100644 index 2adf917e8..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/ip/reset_release.tcl +++ /dev/null @@ -1,52 +0,0 @@ -package require -exact qsys 21.3 - -# create the system "reset_release" -proc do_create_reset_release {} { - # create the system - create_system reset_release - set_project_property DEVICE {AGFB014R24B2E2V} - set_project_property DEVICE_FAMILY {Agilex} - set_project_property HIDE_FROM_IP_CATALOG {true} - set_use_testbench_naming_pattern 0 {} - - # add HDL parameters - - # add the components - add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate - set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} - set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true - - # add wirelevel expressions - - # preserve ports for debug - - # add the exports - set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done - - # set values for exposed HDL parameters - - # set the the module properties - set_module_property BONUS_DATA { - - - - - -} - set_module_property FILE {reset_release.ip} - set_module_property GENERATION_ID {0x00000000} - set_module_property NAME {reset_release} - - # save the system - sync_sysinfo_parameters - save_system reset_release -} - -proc do_set_exported_interface_sysinfo_parameters {} { -} - -# create all the systems, from bottom up -do_create_reset_release - -# set system info parameters on exported interface, from bottom up -do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/lib b/fpga/mqnic/DE10_Agilex/fpga_25g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/axis_fifo.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/axis_fifo.v deleted file mode 100644 index 45b7232f1..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/axis_fifo.v +++ /dev/null @@ -1,565 +0,0 @@ -/* - -Copyright (c) 2013-2023 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4-Stream FIFO - */ -module axis_fifo # -( - // FIFO depth in words - // KEEP_WIDTH words per cycle if KEEP_ENABLE set - // Rounded up to nearest power of 2 cycles - parameter DEPTH = 4096, - // Width of AXI stream interfaces in bits - parameter DATA_WIDTH = 8, - // Propagate tkeep signal - // If disabled, tkeep assumed to be 1'b1 - parameter KEEP_ENABLE = (DATA_WIDTH>8), - // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), - // Propagate tlast signal - parameter LAST_ENABLE = 1, - // Propagate tid signal - parameter ID_ENABLE = 0, - // tid signal width - parameter ID_WIDTH = 8, - // Propagate tdest signal - parameter DEST_ENABLE = 0, - // tdest signal width - parameter DEST_WIDTH = 8, - // Propagate tuser signal - parameter USER_ENABLE = 1, - // tuser signal width - parameter USER_WIDTH = 1, - // number of RAM pipeline registers - parameter RAM_PIPELINE = 1, - // use output FIFO - // When set, the RAM read enable and pipeline clock enables are removed - parameter OUTPUT_FIFO_ENABLE = 0, - // Frame FIFO mode - operate on frames instead of cycles - // When set, m_axis_tvalid will not be deasserted within a frame - // Requires LAST_ENABLE set - parameter FRAME_FIFO = 0, - // tuser value for bad frame marker - parameter USER_BAD_FRAME_VALUE = 1'b1, - // tuser mask for bad frame marker - parameter USER_BAD_FRAME_MASK = 1'b1, - // Drop frames larger than FIFO - // Requires FRAME_FIFO set - parameter DROP_OVERSIZE_FRAME = FRAME_FIFO, - // Drop frames marked bad - // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set - parameter DROP_BAD_FRAME = 0, - // Drop incoming frames when full - // When set, s_axis_tready is always asserted - // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set - parameter DROP_WHEN_FULL = 0, - // Mark incoming frames as bad frames when full - // When set, s_axis_tready is always asserted - // Requires FRAME_FIFO to be clear - parameter MARK_WHEN_FULL = 0, - // Enable pause request input - parameter PAUSE_ENABLE = 0, - // Pause between frames - parameter FRAME_PAUSE = FRAME_FIFO -) -( - input wire clk, - input wire rst, - - /* - * AXI input - */ - input wire [DATA_WIDTH-1:0] s_axis_tdata, - input wire [KEEP_WIDTH-1:0] s_axis_tkeep, - input wire s_axis_tvalid, - output wire s_axis_tready, - input wire s_axis_tlast, - input wire [ID_WIDTH-1:0] s_axis_tid, - input wire [DEST_WIDTH-1:0] s_axis_tdest, - input wire [USER_WIDTH-1:0] s_axis_tuser, - - /* - * AXI output - */ - output wire [DATA_WIDTH-1:0] m_axis_tdata, - output wire [KEEP_WIDTH-1:0] m_axis_tkeep, - output wire m_axis_tvalid, - input wire m_axis_tready, - output wire m_axis_tlast, - output wire [ID_WIDTH-1:0] m_axis_tid, - output wire [DEST_WIDTH-1:0] m_axis_tdest, - output wire [USER_WIDTH-1:0] m_axis_tuser, - - /* - * Pause - */ - input wire pause_req, - output wire pause_ack, - - /* - * Status - */ - output wire [$clog2(DEPTH):0] status_depth, - output wire [$clog2(DEPTH):0] status_depth_commit, - output wire status_overflow, - output wire status_bad_frame, - output wire status_good_frame -); - -parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH); - -parameter OUTPUT_FIFO_ADDR_WIDTH = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7); - -// check configuration -initial begin - if (FRAME_FIFO && !LAST_ENABLE) begin - $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); - $finish; - end - - if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin - $error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)"); - $finish; - end - - if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin - $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)"); - $finish; - end - - if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin - $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)"); - $finish; - end - - if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin - $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); - $finish; - end - - if (MARK_WHEN_FULL && FRAME_FIFO) begin - $error("Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)"); - $finish; - end - - if (MARK_WHEN_FULL && !LAST_ENABLE) begin - $error("Error: MARK_WHEN_FULL set requires LAST_ENABLE set (instance %m)"); - $finish; - end -end - -localparam KEEP_OFFSET = DATA_WIDTH; -localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0); -localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0); -localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0); -localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0); -localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0); - -reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}; -reg [ADDR_WIDTH:0] wr_ptr_commit_reg = {ADDR_WIDTH+1{1'b0}}; -reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}; - -// (* ramstyle = "no_rw_check" *) -// Workaround for Quartus MLAB RAM read enable bug -// https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html -(* ramstyle = "no_rw_check, m20k" *) -reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0]; -reg mem_read_data_valid_reg = 1'b0; - -(* shreg_extract = "no" *) -reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0]; -reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0; - -// full when first MSB different but rest same -wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); -// empty when pointers match exactly -wire empty = wr_ptr_commit_reg == rd_ptr_reg; -// overflow within packet -wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); - -reg s_frame_reg = 1'b0; - -reg drop_frame_reg = 1'b0; -reg mark_frame_reg = 1'b0; -reg send_frame_reg = 1'b0; -reg [ADDR_WIDTH:0] depth_reg = 0; -reg [ADDR_WIDTH:0] depth_commit_reg = 0; -reg overflow_reg = 1'b0; -reg bad_frame_reg = 1'b0; -reg good_frame_reg = 1'b0; - -assign s_axis_tready = FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL); - -wire [WIDTH-1:0] s_axis; - -generate - assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata; - if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep; - if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast | mark_frame_reg; - if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid; - if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest; - if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = mark_frame_reg ? USER_BAD_FRAME_VALUE : s_axis_tuser; -endgenerate - -wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1]; - -wire m_axis_tready_pipe; -wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1]; - -wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0]; -wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}}; -wire m_axis_tlast_pipe = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1; -wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}}; -wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}}; -wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}}; - -wire m_axis_tready_out; -wire m_axis_tvalid_out; - -wire [DATA_WIDTH-1:0] m_axis_tdata_out; -wire [KEEP_WIDTH-1:0] m_axis_tkeep_out; -wire m_axis_tlast_out; -wire [ID_WIDTH-1:0] m_axis_tid_out; -wire [DEST_WIDTH-1:0] m_axis_tdest_out; -wire [USER_WIDTH-1:0] m_axis_tuser_out; - -wire pipe_ready; - -assign status_depth = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_reg; -assign status_depth_commit = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_commit_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_commit_reg; -assign status_overflow = overflow_reg; -assign status_bad_frame = bad_frame_reg; -assign status_good_frame = good_frame_reg; - -// Write logic -always @(posedge clk) begin - overflow_reg <= 1'b0; - bad_frame_reg <= 1'b0; - good_frame_reg <= 1'b0; - - if (s_axis_tready && s_axis_tvalid && LAST_ENABLE) begin - // track input frame status - s_frame_reg <= !s_axis_tlast; - end - - if (FRAME_FIFO) begin - // frame FIFO mode - if (s_axis_tready && s_axis_tvalid) begin - // transfer in - if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin - // full, packet overflow, or currently dropping frame - // drop frame - drop_frame_reg <= 1'b1; - if (s_axis_tlast) begin - // end of frame, reset write pointer - wr_ptr_reg <= wr_ptr_commit_reg; - drop_frame_reg <= 1'b0; - overflow_reg <= 1'b1; - end - end else begin - // store it - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_reg <= wr_ptr_reg + 1; - if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin - // end of frame or send frame - send_frame_reg <= !s_axis_tlast; - if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin - // bad packet, reset write pointer - wr_ptr_reg <= wr_ptr_commit_reg; - bad_frame_reg <= 1'b1; - end else begin - // good packet or packet overflow, update write pointer - wr_ptr_commit_reg <= wr_ptr_reg + 1; - good_frame_reg <= s_axis_tlast; - end - end - end - end else if (s_axis_tvalid && full_wr && !DROP_OVERSIZE_FRAME) begin - // data valid with packet overflow - // update write pointer - send_frame_reg <= 1'b1; - wr_ptr_commit_reg <= wr_ptr_reg; - end - end else begin - // normal FIFO mode - if (s_axis_tready && s_axis_tvalid) begin - if (drop_frame_reg && MARK_WHEN_FULL) begin - // currently dropping frame - if (s_axis_tlast) begin - // end of frame - if (!full && mark_frame_reg) begin - // terminate marked frame - mark_frame_reg <= 1'b0; - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_reg <= wr_ptr_reg + 1; - wr_ptr_commit_reg <= wr_ptr_reg + 1; - end - // end of frame, clear drop flag - drop_frame_reg <= 1'b0; - overflow_reg <= 1'b1; - end - end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin - // full or marking frame - // drop frame; mark if this isn't the first cycle - drop_frame_reg <= 1'b1; - mark_frame_reg <= mark_frame_reg || s_frame_reg; - if (s_axis_tlast) begin - drop_frame_reg <= 1'b0; - overflow_reg <= 1'b1; - end - end else begin - // transfer in - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_reg <= wr_ptr_reg + 1; - wr_ptr_commit_reg <= wr_ptr_reg + 1; - end - end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin - // terminate marked frame - mark_frame_reg <= 1'b0; - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_reg <= wr_ptr_reg + 1; - wr_ptr_commit_reg <= wr_ptr_reg + 1; - end - end - - if (rst) begin - wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; - wr_ptr_commit_reg <= {ADDR_WIDTH+1{1'b0}}; - - s_frame_reg <= 1'b0; - - drop_frame_reg <= 1'b0; - mark_frame_reg <= 1'b0; - send_frame_reg <= 1'b0; - overflow_reg <= 1'b0; - bad_frame_reg <= 1'b0; - good_frame_reg <= 1'b0; - end -end - -// Status -always @(posedge clk) begin - depth_reg <= wr_ptr_reg - rd_ptr_reg; - depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_reg; -end - -// Read logic -integer j; - -always @(posedge clk) begin - if (m_axis_tready_pipe) begin - // output ready; invalidate stage - m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0; - end - - for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin - if (m_axis_tready_pipe || ((~m_axis_tvalid_pipe_reg) >> j)) begin - // output ready or bubble in pipeline; transfer down pipeline - m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1]; - m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1]; - m_axis_tvalid_pipe_reg[j-1] <= 1'b0; - end - end - - if (m_axis_tready_pipe || ~m_axis_tvalid_pipe_reg) begin - // output ready or bubble in pipeline; read new data from FIFO - m_axis_tvalid_pipe_reg[0] <= 1'b0; - m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]]; - if (!empty && pipe_ready) begin - // not empty, increment pointer - m_axis_tvalid_pipe_reg[0] <= 1'b1; - rd_ptr_reg <= rd_ptr_reg + 1; - end - end - - if (rst) begin - rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; - m_axis_tvalid_pipe_reg <= 0; - end -end - -generate - -if (!OUTPUT_FIFO_ENABLE) begin - - assign pipe_ready = 1'b1; - - assign m_axis_tready_pipe = m_axis_tready_out; - assign m_axis_tvalid_out = m_axis_tvalid_pipe; - - assign m_axis_tdata_out = m_axis_tdata_pipe; - assign m_axis_tkeep_out = m_axis_tkeep_pipe; - assign m_axis_tlast_out = m_axis_tlast_pipe; - assign m_axis_tid_out = m_axis_tid_pipe; - assign m_axis_tdest_out = m_axis_tdest_pipe; - assign m_axis_tuser_out = m_axis_tuser_pipe; - -end else begin : output_fifo - - // output datapath logic - reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; - reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; - reg m_axis_tvalid_reg = 1'b0; - reg m_axis_tlast_reg = 1'b0; - reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; - reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; - reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; - - reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0; - reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0; - reg out_fifo_half_full_reg = 1'b0; - - wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}}); - wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg; - - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - - assign pipe_ready = !out_fifo_half_full_reg; - - assign m_axis_tready_pipe = 1'b1; - - assign m_axis_tdata_out = m_axis_tdata_reg; - assign m_axis_tkeep_out = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; - assign m_axis_tvalid_out = m_axis_tvalid_reg; - assign m_axis_tlast_out = LAST_ENABLE ? m_axis_tlast_reg : 1'b1; - assign m_axis_tid_out = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; - assign m_axis_tdest_out = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; - assign m_axis_tuser_out = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; - - always @(posedge clk) begin - m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out; - - out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1); - - if (!out_fifo_full && m_axis_tvalid_pipe) begin - out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_pipe; - out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_pipe; - out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_pipe; - out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_pipe; - out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_pipe; - out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_pipe; - out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1; - end - - if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin - m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tvalid_reg <= 1'b1; - m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1; - end - - if (rst) begin - out_fifo_wr_ptr_reg <= 0; - out_fifo_rd_ptr_reg <= 0; - m_axis_tvalid_reg <= 1'b0; - end - end - -end - -if (PAUSE_ENABLE) begin : pause - - // Pause logic - reg pause_reg = 1'b0; - reg pause_frame_reg = 1'b0; - - assign m_axis_tready_out = m_axis_tready && !pause_reg; - assign m_axis_tvalid = m_axis_tvalid_out && !pause_reg; - - assign m_axis_tdata = m_axis_tdata_out; - assign m_axis_tkeep = m_axis_tkeep_out; - assign m_axis_tlast = m_axis_tlast_out; - assign m_axis_tid = m_axis_tid_out; - assign m_axis_tdest = m_axis_tdest_out; - assign m_axis_tuser = m_axis_tuser_out; - - assign pause_ack = pause_reg; - - always @(posedge clk) begin - if (FRAME_PAUSE) begin - if (m_axis_tvalid && m_axis_tready) begin - if (m_axis_tlast) begin - pause_frame_reg <= 1'b0; - pause_reg <= pause_req; - end else begin - pause_frame_reg <= 1'b1; - end - end else begin - if (!pause_frame_reg) begin - pause_reg <= pause_req; - end - end - end else begin - pause_reg <= pause_req; - end - - if (rst) begin - pause_frame_reg <= 1'b0; - pause_reg <= 1'b0; - end - end - -end else begin - - assign m_axis_tready_out = m_axis_tready; - assign m_axis_tvalid = m_axis_tvalid_out; - - assign m_axis_tdata = m_axis_tdata_out; - assign m_axis_tkeep = m_axis_tkeep_out; - assign m_axis_tlast = m_axis_tlast_out; - assign m_axis_tid = m_axis_tid_out; - assign m_axis_tdest = m_axis_tdest_out; - assign m_axis_tuser = m_axis_tuser_out; - - assign pause_ack = 1'b0; - -end - -endgenerate - -endmodule - -`resetall diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/common b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/debounce_switch.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/debounce_switch.v deleted file mode 100644 index 8e93a50c4..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/debounce_switch.v +++ /dev/null @@ -1,93 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes switch and button inputs with a slow sampled shift register - */ -module debounce_switch #( - parameter WIDTH=1, // width of the input and output signals - parameter N=3, // length of shift register - parameter RATE=125000 // clock division factor -)( - input wire clk, - input wire rst, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [23:0] cnt_reg = 24'd0; - -reg [N-1:0] debounce_reg[WIDTH-1:0]; - -reg [WIDTH-1:0] state; - -/* - * The synchronized output is the state register - */ -assign out = state; - -integer k; - -always @(posedge clk or posedge rst) begin - if (rst) begin - cnt_reg <= 0; - state <= 0; - - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= 0; - end - end else begin - if (cnt_reg < RATE) begin - cnt_reg <= cnt_reg + 24'd1; - end else begin - cnt_reg <= 24'd0; - end - - if (cnt_reg == 24'd0) begin - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; - end - end - - for (k = 0; k < WIDTH; k = k + 1) begin - if (|debounce_reg[k] == 0) begin - state[k] <= 0; - end else if (&debounce_reg[k] == 1) begin - state[k] <= 1; - end else begin - state[k] <= state[k]; - end - end - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v deleted file mode 100644 index 7171c847e..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v +++ /dev/null @@ -1,2625 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2022-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga # -( - // FW and board IDs - parameter FPGA_ID = 32'hC341A0DD, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h1172_B00A, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd1563227611, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 1, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 10, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter SEG_COUNT = 2, - parameter SEG_DATA_WIDTH = 256, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, - parameter AXIS_ETH_TX_PIPELINE = 0, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, - parameter AXIS_ETH_TX_TS_PIPELINE = 0, - parameter AXIS_ETH_RX_PIPELINE = 0, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, - parameter MAC_RSFEC = 1, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 100 MHz - * Reset: Push button, active low - */ - input wire clk_100_b2a, - // input wire clk_50_b3a, - // input wire clk_50_b3c, - // input wire cpu_reset_n, - - /* - * GPIO - */ - input wire [1:0] button, - input wire [1:0] sw, - output wire [3:0] led, - output wire [3:0] led_bracket, - - /* - * PCIe: gen 4 x16 - */ - output wire [15:0] pcie_tx_p, - output wire [15:0] pcie_tx_n, - input wire [15:0] pcie_rx_p, - input wire [15:0] pcie_rx_n, - input wire [1:0] pcie_refclk_p, - input wire pcie_perst_n, - - /* - * Ethernet: QSFP-DD - */ - output wire [7:0] qsfpdda_tx_p, - output wire [7:0] qsfpdda_tx_n, - input wire [7:0] qsfpdda_rx_p, - input wire [7:0] qsfpdda_rx_n, - output wire [7:0] qsfpddb_tx_p, - output wire [7:0] qsfpddb_tx_n, - input wire [7:0] qsfpddb_rx_p, - input wire [7:0] qsfpddb_rx_n, - input wire qsfpdda_refclk_p, - input wire qsfpddb_refclk_p, - input wire qsfpddrsv_refclk_p, - output wire qsfpdda_initmode, - input wire qsfpdda_interrupt_n, - input wire qsfpdda_mod_prs_n, - output wire qsfpdda_mod_sel_n, - output wire qsfpdda_rst_n, - inout wire qsfpdda_scl, - inout wire qsfpdda_sda, - output wire qsfpddb_initmode, - input wire qsfpddb_interrupt_n, - input wire qsfpddb_mod_prs_n, - output wire qsfpddb_mod_sel_n, - output wire qsfpddb_rst_n, - inout wire qsfpddb_scl, - inout wire qsfpddb_sda -); - -// PTP configuration -parameter PTP_CLK_PERIOD_NS_NUM = 2048; -parameter PTP_CLK_PERIOD_NS_DENOM = 825; -parameter PTP_TS_WIDTH = 96; -parameter PTP_TAG_WIDTH = 8; - -// Interface configuration -parameter TX_TAG_WIDTH = PTP_TAG_WIDTH; - -// PCIe interface configuration -parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32); -parameter SEG_HDR_WIDTH = 128; -parameter SEG_PRFX_WIDTH = 32; -parameter TX_SEQ_NUM_WIDTH = 6; -parameter PCIE_TAG_COUNT = 256; - -// Ethernet interface configuration -parameter AXIS_ETH_DATA_WIDTH = 64; -parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); -parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; -parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; - -// Clock and reset -wire ninit_done; - -wire pcie_clk; -wire pcie_rst; - -reset_release reset_release_inst ( - .ninit_done (ninit_done) -); - -wire clk_100mhz = clk_100_b2a; -wire rst_100mhz; - -sync_reset #( - .N(20) -) -sync_reset_100mhz_inst ( - .clk(clk_100mhz), - .rst(pcie_rst), - .out(rst_100mhz) -); - -// GPIO -wire [1:0] button_int; -wire [1:0] sw_int; -wire qsfpdda_interrupt_n_int; -wire qsfpdda_mod_prs_n_int; -wire qsfpdda_scl_i; -wire qsfpdda_scl_o; -wire qsfpdda_scl_t; -wire qsfpdda_sda_i; -wire qsfpdda_sda_o; -wire qsfpdda_sda_t; -wire qsfpddb_interrupt_n_int; -wire qsfpddb_mod_prs_n_int; -wire qsfpddb_scl_i; -wire qsfpddb_scl_o; -wire qsfpddb_scl_t; -wire qsfpddb_sda_i; -wire qsfpddb_sda_o; -wire qsfpddb_sda_t; - -reg qsfpdda_scl_o_reg; -reg qsfpdda_scl_t_reg; -reg qsfpdda_sda_o_reg; -reg qsfpdda_sda_t_reg; -reg qsfpddb_scl_o_reg; -reg qsfpddb_scl_t_reg; -reg qsfpddb_sda_o_reg; -reg qsfpddb_sda_t_reg; - -always @(posedge pcie_clk) begin - qsfpdda_scl_o_reg <= qsfpdda_scl_o; - qsfpdda_scl_t_reg <= qsfpdda_scl_t; - qsfpdda_sda_o_reg <= qsfpdda_sda_o; - qsfpdda_sda_t_reg <= qsfpdda_sda_t; - qsfpddb_scl_o_reg <= qsfpddb_scl_o; - qsfpddb_scl_t_reg <= qsfpddb_scl_t; - qsfpddb_sda_o_reg <= qsfpddb_sda_o; - qsfpddb_sda_t_reg <= qsfpddb_sda_t; -end - -debounce_switch #( - .WIDTH(4), - .N(4), - .RATE(250000) -) -debounce_switch_inst ( - .clk(pcie_clk), - .rst(pcie_rst), - .in({button, sw}), - .out({button_int, sw_int}) -); - -sync_signal #( - .WIDTH(8), - .N(2) -) -sync_signal_inst ( - .clk(pcie_clk), - .in({qsfpdda_interrupt_n, qsfpdda_mod_prs_n, qsfpdda_scl, qsfpdda_sda, - qsfpddb_interrupt_n, qsfpddb_mod_prs_n, qsfpddb_scl, qsfpddb_sda}), - .out({qsfpdda_interrupt_n_int, qsfpdda_mod_prs_n_int, qsfpdda_scl_i, qsfpdda_sda_i, - qsfpddb_interrupt_n_int, qsfpddb_mod_prs_n_int, qsfpddb_scl_i, qsfpddb_sda_i}) -); - -assign qsfpdda_scl = qsfpdda_scl_t_reg ? 1'bz : qsfpdda_scl_o_reg; -assign qsfpdda_sda = qsfpdda_sda_t_reg ? 1'bz : qsfpdda_sda_o_reg; - -assign qsfpddb_scl = qsfpddb_scl_t_reg ? 1'bz : qsfpddb_scl_o_reg; -assign qsfpddb_sda = qsfpddb_sda_t_reg ? 1'bz : qsfpddb_sda_o_reg; - -// PCIe -wire coreclkout_hip; -wire reset_status_n; - -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data; -wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty; -wire [SEG_COUNT-1:0] rx_st_sop; -wire [SEG_COUNT-1:0] rx_st_eop; -wire [SEG_COUNT-1:0] rx_st_valid; -wire rx_st_ready; -wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr; -wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx; -wire [SEG_COUNT-1:0] rx_st_vf_active = 0; -wire [SEG_COUNT*3-1:0] rx_st_func_num = 0; -wire [SEG_COUNT*11-1:0] rx_st_vf_num = 0; -wire [SEG_COUNT*3-1:0] rx_st_bar_range; -wire [SEG_COUNT-1:0] rx_st_tlp_abort; - -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data; -wire [SEG_COUNT-1:0] tx_st_sop; -wire [SEG_COUNT-1:0] tx_st_eop; -wire [SEG_COUNT-1:0] tx_st_valid; -wire tx_st_ready; -wire [SEG_COUNT-1:0] tx_st_err; -wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr; -wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx; - -wire [11:0] rx_buffer_limit; -wire [1:0] rx_buffer_limit_tdm_idx; - -wire [15:0] tx_cdts_limit; -wire [2:0] tx_cdts_limit_tdm_idx; - -wire [15:0] tl_cfg_ctl; -wire [4:0] tl_cfg_add; -wire [2:0] tl_cfg_func; - -assign pcie_clk = coreclkout_hip; -assign pcie_rst = !reset_status_n; - -pcie pcie_hip_inst ( - .p0_rx_st_ready_i(rx_st_ready), - .p0_rx_st_sop_o(rx_st_sop), - .p0_rx_st_eop_o(rx_st_eop), - .p0_rx_st_data_o(rx_st_data), - .p0_rx_st_valid_o(rx_st_valid), - .p0_rx_st_empty_o(rx_st_empty), - .p0_rx_st_hdr_o(rx_st_hdr), - .p0_rx_st_tlp_prfx_o(rx_st_tlp_prfx), - .p0_rx_st_bar_range_o(rx_st_bar_range), - .p0_rx_st_tlp_abort_o(rx_st_tlp_abort), - .p0_rx_par_err_o(), - .p0_tx_st_sop_i(tx_st_sop), - .p0_tx_st_eop_i(tx_st_eop), - .p0_tx_st_data_i(tx_st_data), - .p0_tx_st_valid_i(tx_st_valid), - .p0_tx_st_err_i(tx_st_err), - .p0_tx_st_ready_o(tx_st_ready), - .p0_tx_st_hdr_i(tx_st_hdr), - .p0_tx_st_tlp_prfx_i(tx_st_tlp_prfx), - .p0_tx_par_err_o(), - .p0_tx_cdts_limit_o(tx_cdts_limit), - .p0_tx_cdts_limit_tdm_idx_o(tx_cdts_limit_tdm_idx), - .p0_tl_cfg_func_o(tl_cfg_func), - .p0_tl_cfg_add_o(tl_cfg_add), - .p0_tl_cfg_ctl_o(tl_cfg_ctl), - .p0_dl_timer_update_o(), - .p0_reset_status_n(reset_status_n), - .p0_pin_perst_n(), - .p0_link_up_o(), - .p0_dl_up_o(), - .p0_surprise_down_err_o(), - .p0_ltssm_state_o(), - .rx_n_in0(pcie_rx_n[0]), - .rx_n_in1(pcie_rx_n[1]), - .rx_n_in2(pcie_rx_n[2]), - .rx_n_in3(pcie_rx_n[3]), - .rx_n_in4(pcie_rx_n[4]), - .rx_n_in5(pcie_rx_n[5]), - .rx_n_in6(pcie_rx_n[6]), - .rx_n_in7(pcie_rx_n[7]), - .rx_n_in8(pcie_rx_n[8]), - .rx_n_in9(pcie_rx_n[9]), - .rx_n_in10(pcie_rx_n[10]), - .rx_n_in11(pcie_rx_n[11]), - .rx_n_in12(pcie_rx_n[12]), - .rx_n_in13(pcie_rx_n[13]), - .rx_n_in14(pcie_rx_n[14]), - .rx_n_in15(pcie_rx_n[15]), - .rx_p_in0(pcie_rx_p[0]), - .rx_p_in1(pcie_rx_p[1]), - .rx_p_in2(pcie_rx_p[2]), - .rx_p_in3(pcie_rx_p[3]), - .rx_p_in4(pcie_rx_p[4]), - .rx_p_in5(pcie_rx_p[5]), - .rx_p_in6(pcie_rx_p[6]), - .rx_p_in7(pcie_rx_p[7]), - .rx_p_in8(pcie_rx_p[8]), - .rx_p_in9(pcie_rx_p[9]), - .rx_p_in10(pcie_rx_p[10]), - .rx_p_in11(pcie_rx_p[11]), - .rx_p_in12(pcie_rx_p[12]), - .rx_p_in13(pcie_rx_p[13]), - .rx_p_in14(pcie_rx_p[14]), - .rx_p_in15(pcie_rx_p[15]), - .tx_n_out0(pcie_tx_n[0]), - .tx_n_out1(pcie_tx_n[1]), - .tx_n_out2(pcie_tx_n[2]), - .tx_n_out3(pcie_tx_n[3]), - .tx_n_out4(pcie_tx_n[4]), - .tx_n_out5(pcie_tx_n[5]), - .tx_n_out6(pcie_tx_n[6]), - .tx_n_out7(pcie_tx_n[7]), - .tx_n_out8(pcie_tx_n[8]), - .tx_n_out9(pcie_tx_n[9]), - .tx_n_out10(pcie_tx_n[10]), - .tx_n_out11(pcie_tx_n[11]), - .tx_n_out12(pcie_tx_n[12]), - .tx_n_out13(pcie_tx_n[13]), - .tx_n_out14(pcie_tx_n[14]), - .tx_n_out15(pcie_tx_n[15]), - .tx_p_out0(pcie_tx_p[0]), - .tx_p_out1(pcie_tx_p[1]), - .tx_p_out2(pcie_tx_p[2]), - .tx_p_out3(pcie_tx_p[3]), - .tx_p_out4(pcie_tx_p[4]), - .tx_p_out5(pcie_tx_p[5]), - .tx_p_out6(pcie_tx_p[6]), - .tx_p_out7(pcie_tx_p[7]), - .tx_p_out8(pcie_tx_p[8]), - .tx_p_out9(pcie_tx_p[9]), - .tx_p_out10(pcie_tx_p[10]), - .tx_p_out11(pcie_tx_p[11]), - .tx_p_out12(pcie_tx_p[12]), - .tx_p_out13(pcie_tx_p[13]), - .tx_p_out14(pcie_tx_p[14]), - .tx_p_out15(pcie_tx_p[15]), - .coreclkout_hip(coreclkout_hip), - .refclk0(pcie_refclk_p[0]), - .refclk1(pcie_refclk_p[1]), - .pin_perst_n(pcie_perst_n), - .ninit_done(ninit_done) -); - -// QSFP28 interfaces - -wire etile_iopll_locked; -wire etile_ptp_sample_clk; - -iopll_etile_ptp iopll_etile_ptp_inst ( - .rst (rst_100mhz), - .refclk (clk_100mhz), - .locked (etile_iopll_locked), - .outclk_0 (etile_ptp_sample_clk) -); - -// QSFP-DD A -wire qsfpdda_mac_1_tx_clk_int; -wire qsfpdda_mac_1_tx_rst_int; - -wire qsfpdda_mac_1_tx_ptp_clk_int; -wire qsfpdda_mac_1_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_ts_tag_int; -wire qsfpdda_mac_1_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tkeep_int; -wire qsfpdda_mac_1_tx_axis_tvalid_int; -wire qsfpdda_mac_1_tx_axis_tready_int; -wire qsfpdda_mac_1_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tuser_int; - -wire qsfpdda_mac_1_tx_status_int; -wire qsfpdda_mac_1_tx_lfc_req_int; -wire [7:0] qsfpdda_mac_1_tx_pfc_req_int; - -wire qsfpdda_mac_1_rx_clk_int; -wire qsfpdda_mac_1_rx_rst_int; - -wire qsfpdda_mac_1_rx_ptp_clk_int; -wire qsfpdda_mac_1_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tkeep_int; -wire qsfpdda_mac_1_rx_axis_tvalid_int; -wire qsfpdda_mac_1_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tuser_int; - -wire qsfpdda_mac_1_rx_status_int; -wire qsfpdda_mac_1_rx_lfc_req_int; -wire [7:0] qsfpdda_mac_1_rx_pfc_req_int; - -wire qsfpdda_mac_2_tx_clk_int; -wire qsfpdda_mac_2_tx_rst_int; - -wire qsfpdda_mac_2_tx_ptp_clk_int; -wire qsfpdda_mac_2_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_ts_tag_int; -wire qsfpdda_mac_2_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tkeep_int; -wire qsfpdda_mac_2_tx_axis_tvalid_int; -wire qsfpdda_mac_2_tx_axis_tready_int; -wire qsfpdda_mac_2_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tuser_int; - -wire qsfpdda_mac_2_tx_status_int; -wire qsfpdda_mac_2_tx_lfc_req_int; -wire [7:0] qsfpdda_mac_2_tx_pfc_req_int; - -wire qsfpdda_mac_2_rx_clk_int; -wire qsfpdda_mac_2_rx_rst_int; - -wire qsfpdda_mac_2_rx_ptp_clk_int; -wire qsfpdda_mac_2_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tkeep_int; -wire qsfpdda_mac_2_rx_axis_tvalid_int; -wire qsfpdda_mac_2_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tuser_int; - -wire qsfpdda_mac_2_rx_status_int; -wire qsfpdda_mac_2_rx_lfc_req_int; -wire [7:0] qsfpdda_mac_2_rx_pfc_req_int; - -wire qsfpdda_mac_3_tx_clk_int; -wire qsfpdda_mac_3_tx_rst_int; - -wire qsfpdda_mac_3_tx_ptp_clk_int; -wire qsfpdda_mac_3_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_3_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_3_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_3_tx_ptp_ts_tag_int; -wire qsfpdda_mac_3_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_3_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_3_tx_axis_tkeep_int; -wire qsfpdda_mac_3_tx_axis_tvalid_int; -wire qsfpdda_mac_3_tx_axis_tready_int; -wire qsfpdda_mac_3_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_3_tx_axis_tuser_int; - -wire qsfpdda_mac_3_tx_status_int; -wire qsfpdda_mac_3_tx_lfc_req_int; -wire [7:0] qsfpdda_mac_3_tx_pfc_req_int; - -wire qsfpdda_mac_3_rx_clk_int; -wire qsfpdda_mac_3_rx_rst_int; - -wire qsfpdda_mac_3_rx_ptp_clk_int; -wire qsfpdda_mac_3_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_3_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_3_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_3_rx_axis_tkeep_int; -wire qsfpdda_mac_3_rx_axis_tvalid_int; -wire qsfpdda_mac_3_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_3_rx_axis_tuser_int; - -wire qsfpdda_mac_3_rx_status_int; -wire qsfpdda_mac_3_rx_lfc_req_int; -wire [7:0] qsfpdda_mac_3_rx_pfc_req_int; - -wire qsfpdda_mac_4_tx_clk_int; -wire qsfpdda_mac_4_tx_rst_int; - -wire qsfpdda_mac_4_tx_ptp_clk_int; -wire qsfpdda_mac_4_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_4_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_4_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_4_tx_ptp_ts_tag_int; -wire qsfpdda_mac_4_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_4_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_4_tx_axis_tkeep_int; -wire qsfpdda_mac_4_tx_axis_tvalid_int; -wire qsfpdda_mac_4_tx_axis_tready_int; -wire qsfpdda_mac_4_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_4_tx_axis_tuser_int; - -wire qsfpdda_mac_4_tx_status_int; -wire qsfpdda_mac_4_tx_lfc_req_int; -wire [7:0] qsfpdda_mac_4_tx_pfc_req_int; - -wire qsfpdda_mac_4_rx_clk_int; -wire qsfpdda_mac_4_rx_rst_int; - -wire qsfpdda_mac_4_rx_ptp_clk_int; -wire qsfpdda_mac_4_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_4_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_4_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_4_rx_axis_tkeep_int; -wire qsfpdda_mac_4_rx_axis_tvalid_int; -wire qsfpdda_mac_4_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_4_rx_axis_tuser_int; - -wire qsfpdda_mac_4_rx_status_int; -wire qsfpdda_mac_4_rx_lfc_req_int; -wire [7:0] qsfpdda_mac_4_rx_pfc_req_int; - -wire qsfpdda_mac_5_tx_clk_int; -wire qsfpdda_mac_5_tx_rst_int; - -wire qsfpdda_mac_5_tx_ptp_clk_int; -wire qsfpdda_mac_5_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_5_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_5_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_5_tx_ptp_ts_tag_int; -wire qsfpdda_mac_5_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_5_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_5_tx_axis_tkeep_int; -wire qsfpdda_mac_5_tx_axis_tvalid_int; -wire qsfpdda_mac_5_tx_axis_tready_int; -wire qsfpdda_mac_5_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_5_tx_axis_tuser_int; - -wire qsfpdda_mac_5_tx_status_int; -wire qsfpdda_mac_5_tx_lfc_req_int; -wire [7:0] qsfpdda_mac_5_tx_pfc_req_int; - -wire qsfpdda_mac_5_rx_clk_int; -wire qsfpdda_mac_5_rx_rst_int; - -wire qsfpdda_mac_5_rx_ptp_clk_int; -wire qsfpdda_mac_5_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_5_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_5_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_5_rx_axis_tkeep_int; -wire qsfpdda_mac_5_rx_axis_tvalid_int; -wire qsfpdda_mac_5_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_5_rx_axis_tuser_int; - -wire qsfpdda_mac_5_rx_status_int; -wire qsfpdda_mac_5_rx_lfc_req_int; -wire [7:0] qsfpdda_mac_5_rx_pfc_req_int; - -wire qsfpdda_mac_6_tx_clk_int; -wire qsfpdda_mac_6_tx_rst_int; - -wire qsfpdda_mac_6_tx_ptp_clk_int; -wire qsfpdda_mac_6_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_6_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_6_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_6_tx_ptp_ts_tag_int; -wire qsfpdda_mac_6_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_6_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_6_tx_axis_tkeep_int; -wire qsfpdda_mac_6_tx_axis_tvalid_int; -wire qsfpdda_mac_6_tx_axis_tready_int; -wire qsfpdda_mac_6_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_6_tx_axis_tuser_int; - -wire qsfpdda_mac_6_tx_status_int; -wire qsfpdda_mac_6_tx_lfc_req_int; -wire [7:0] qsfpdda_mac_6_tx_pfc_req_int; - -wire qsfpdda_mac_6_rx_clk_int; -wire qsfpdda_mac_6_rx_rst_int; - -wire qsfpdda_mac_6_rx_ptp_clk_int; -wire qsfpdda_mac_6_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_6_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_6_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_6_rx_axis_tkeep_int; -wire qsfpdda_mac_6_rx_axis_tvalid_int; -wire qsfpdda_mac_6_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_6_rx_axis_tuser_int; - -wire qsfpdda_mac_6_rx_status_int; -wire qsfpdda_mac_6_rx_lfc_req_int; -wire [7:0] qsfpdda_mac_6_rx_pfc_req_int; - -wire qsfpdda_mac_7_tx_clk_int; -wire qsfpdda_mac_7_tx_rst_int; - -wire qsfpdda_mac_7_tx_ptp_clk_int; -wire qsfpdda_mac_7_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_7_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_7_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_7_tx_ptp_ts_tag_int; -wire qsfpdda_mac_7_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_7_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_7_tx_axis_tkeep_int; -wire qsfpdda_mac_7_tx_axis_tvalid_int; -wire qsfpdda_mac_7_tx_axis_tready_int; -wire qsfpdda_mac_7_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_7_tx_axis_tuser_int; - -wire qsfpdda_mac_7_tx_status_int; -wire qsfpdda_mac_7_tx_lfc_req_int; -wire [7:0] qsfpdda_mac_7_tx_pfc_req_int; - -wire qsfpdda_mac_7_rx_clk_int; -wire qsfpdda_mac_7_rx_rst_int; - -wire qsfpdda_mac_7_rx_ptp_clk_int; -wire qsfpdda_mac_7_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_7_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_7_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_7_rx_axis_tkeep_int; -wire qsfpdda_mac_7_rx_axis_tvalid_int; -wire qsfpdda_mac_7_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_7_rx_axis_tuser_int; - -wire qsfpdda_mac_7_rx_status_int; -wire qsfpdda_mac_7_rx_lfc_req_int; -wire [7:0] qsfpdda_mac_7_rx_pfc_req_int; - -wire qsfpdda_mac_8_tx_clk_int; -wire qsfpdda_mac_8_tx_rst_int; - -wire qsfpdda_mac_8_tx_ptp_clk_int; -wire qsfpdda_mac_8_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_8_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_8_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_8_tx_ptp_ts_tag_int; -wire qsfpdda_mac_8_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_8_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_8_tx_axis_tkeep_int; -wire qsfpdda_mac_8_tx_axis_tvalid_int; -wire qsfpdda_mac_8_tx_axis_tready_int; -wire qsfpdda_mac_8_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_8_tx_axis_tuser_int; - -wire qsfpdda_mac_8_tx_status_int; -wire qsfpdda_mac_8_tx_lfc_req_int; -wire [7:0] qsfpdda_mac_8_tx_pfc_req_int; - -wire qsfpdda_mac_8_rx_clk_int; -wire qsfpdda_mac_8_rx_rst_int; - -wire qsfpdda_mac_8_rx_ptp_clk_int; -wire qsfpdda_mac_8_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_8_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_8_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_8_rx_axis_tkeep_int; -wire qsfpdda_mac_8_rx_axis_tvalid_int; -wire qsfpdda_mac_8_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_8_rx_axis_tuser_int; - -wire qsfpdda_mac_8_rx_status_int; -wire qsfpdda_mac_8_rx_lfc_req_int; -wire [7:0] qsfpdda_mac_8_rx_pfc_req_int; - -eth_mac_dual_quad_wrapper #( - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .MAC_RSFEC(MAC_RSFEC) -) -qsfpdda_mac_inst ( - .ctrl_clk(clk_100mhz), - .ctrl_rst(rst_100mhz), - - .tx_serial_data_p({qsfpdda_tx_p[7], qsfpdda_tx_p[5], qsfpdda_tx_p[6], qsfpdda_tx_p[4], qsfpdda_tx_p[3], qsfpdda_tx_p[1], qsfpdda_tx_p[2], qsfpdda_tx_p[0]}), - .tx_serial_data_n({qsfpdda_tx_n[7], qsfpdda_tx_n[5], qsfpdda_tx_n[6], qsfpdda_tx_n[4], qsfpdda_tx_n[3], qsfpdda_tx_n[1], qsfpdda_tx_n[2], qsfpdda_tx_n[0]}), - .rx_serial_data_p({qsfpdda_rx_p[7], qsfpdda_rx_p[5], qsfpdda_rx_p[6], qsfpdda_rx_p[4], qsfpdda_rx_p[3], qsfpdda_rx_p[1], qsfpdda_rx_p[2], qsfpdda_rx_p[0]}), - .rx_serial_data_n({qsfpdda_rx_n[7], qsfpdda_rx_n[5], qsfpdda_rx_n[6], qsfpdda_rx_n[4], qsfpdda_rx_n[3], qsfpdda_rx_n[1], qsfpdda_rx_n[2], qsfpdda_rx_n[0]}), - .ref_clk(qsfpddb_refclk_p), - .ptp_sample_clk(etile_ptp_sample_clk), - - .mac_1_tx_clk(qsfpdda_mac_1_tx_clk_int), - .mac_1_tx_rst(qsfpdda_mac_1_tx_rst_int), - - .mac_1_tx_ptp_clk(qsfpdda_mac_1_tx_ptp_clk_int), - .mac_1_tx_ptp_rst(qsfpdda_mac_1_tx_ptp_rst_int), - .mac_1_tx_ptp_time(qsfpdda_mac_1_tx_ptp_time_int), - - .mac_1_tx_ptp_ts(qsfpdda_mac_1_tx_ptp_ts_int), - .mac_1_tx_ptp_ts_tag(qsfpdda_mac_1_tx_ptp_ts_tag_int), - .mac_1_tx_ptp_ts_valid(qsfpdda_mac_1_tx_ptp_ts_valid_int), - - .mac_1_tx_axis_tdata(qsfpdda_mac_1_tx_axis_tdata_int), - .mac_1_tx_axis_tkeep(qsfpdda_mac_1_tx_axis_tkeep_int), - .mac_1_tx_axis_tvalid(qsfpdda_mac_1_tx_axis_tvalid_int), - .mac_1_tx_axis_tready(qsfpdda_mac_1_tx_axis_tready_int), - .mac_1_tx_axis_tlast(qsfpdda_mac_1_tx_axis_tlast_int), - .mac_1_tx_axis_tuser(qsfpdda_mac_1_tx_axis_tuser_int), - - .mac_1_tx_status(qsfpdda_mac_1_tx_status_int), - .mac_1_tx_lfc_req(qsfpdda_mac_1_tx_lfc_req_int), - .mac_1_tx_pfc_req(qsfpdda_mac_1_tx_pfc_req_int), - - .mac_1_rx_clk(qsfpdda_mac_1_rx_clk_int), - .mac_1_rx_rst(qsfpdda_mac_1_rx_rst_int), - - .mac_1_rx_ptp_clk(qsfpdda_mac_1_rx_ptp_clk_int), - .mac_1_rx_ptp_rst(qsfpdda_mac_1_rx_ptp_rst_int), - .mac_1_rx_ptp_time(qsfpdda_mac_1_rx_ptp_time_int), - - .mac_1_rx_axis_tdata(qsfpdda_mac_1_rx_axis_tdata_int), - .mac_1_rx_axis_tkeep(qsfpdda_mac_1_rx_axis_tkeep_int), - .mac_1_rx_axis_tvalid(qsfpdda_mac_1_rx_axis_tvalid_int), - .mac_1_rx_axis_tlast(qsfpdda_mac_1_rx_axis_tlast_int), - .mac_1_rx_axis_tuser(qsfpdda_mac_1_rx_axis_tuser_int), - - .mac_1_rx_status(qsfpdda_mac_1_rx_status_int), - .mac_1_rx_lfc_req(qsfpdda_mac_1_rx_lfc_req_int), - .mac_1_rx_pfc_req(qsfpdda_mac_1_rx_pfc_req_int), - - .mac_2_tx_clk(qsfpdda_mac_3_tx_clk_int), - .mac_2_tx_rst(qsfpdda_mac_3_tx_rst_int), - - .mac_2_tx_ptp_clk(qsfpdda_mac_3_tx_ptp_clk_int), - .mac_2_tx_ptp_rst(qsfpdda_mac_3_tx_ptp_rst_int), - .mac_2_tx_ptp_time(qsfpdda_mac_3_tx_ptp_time_int), - - .mac_2_tx_ptp_ts(qsfpdda_mac_3_tx_ptp_ts_int), - .mac_2_tx_ptp_ts_tag(qsfpdda_mac_3_tx_ptp_ts_tag_int), - .mac_2_tx_ptp_ts_valid(qsfpdda_mac_3_tx_ptp_ts_valid_int), - - .mac_2_tx_axis_tdata(qsfpdda_mac_3_tx_axis_tdata_int), - .mac_2_tx_axis_tkeep(qsfpdda_mac_3_tx_axis_tkeep_int), - .mac_2_tx_axis_tvalid(qsfpdda_mac_3_tx_axis_tvalid_int), - .mac_2_tx_axis_tready(qsfpdda_mac_3_tx_axis_tready_int), - .mac_2_tx_axis_tlast(qsfpdda_mac_3_tx_axis_tlast_int), - .mac_2_tx_axis_tuser(qsfpdda_mac_3_tx_axis_tuser_int), - - .mac_2_tx_status(qsfpdda_mac_3_tx_status_int), - .mac_2_tx_lfc_req(qsfpdda_mac_3_tx_lfc_req_int), - .mac_2_tx_pfc_req(qsfpdda_mac_3_tx_pfc_req_int), - - .mac_2_rx_clk(qsfpdda_mac_3_rx_clk_int), - .mac_2_rx_rst(qsfpdda_mac_3_rx_rst_int), - - .mac_2_rx_ptp_clk(qsfpdda_mac_3_rx_ptp_clk_int), - .mac_2_rx_ptp_rst(qsfpdda_mac_3_rx_ptp_rst_int), - .mac_2_rx_ptp_time(qsfpdda_mac_3_rx_ptp_time_int), - - .mac_2_rx_axis_tdata(qsfpdda_mac_3_rx_axis_tdata_int), - .mac_2_rx_axis_tkeep(qsfpdda_mac_3_rx_axis_tkeep_int), - .mac_2_rx_axis_tvalid(qsfpdda_mac_3_rx_axis_tvalid_int), - .mac_2_rx_axis_tlast(qsfpdda_mac_3_rx_axis_tlast_int), - .mac_2_rx_axis_tuser(qsfpdda_mac_3_rx_axis_tuser_int), - - .mac_2_rx_status(qsfpdda_mac_3_rx_status_int), - .mac_2_rx_lfc_req(qsfpdda_mac_3_rx_lfc_req_int), - .mac_2_rx_pfc_req(qsfpdda_mac_3_rx_pfc_req_int), - - .mac_3_tx_clk(qsfpdda_mac_2_tx_clk_int), - .mac_3_tx_rst(qsfpdda_mac_2_tx_rst_int), - - .mac_3_tx_ptp_clk(qsfpdda_mac_2_tx_ptp_clk_int), - .mac_3_tx_ptp_rst(qsfpdda_mac_2_tx_ptp_rst_int), - .mac_3_tx_ptp_time(qsfpdda_mac_2_tx_ptp_time_int), - - .mac_3_tx_ptp_ts(qsfpdda_mac_2_tx_ptp_ts_int), - .mac_3_tx_ptp_ts_tag(qsfpdda_mac_2_tx_ptp_ts_tag_int), - .mac_3_tx_ptp_ts_valid(qsfpdda_mac_2_tx_ptp_ts_valid_int), - - .mac_3_tx_axis_tdata(qsfpdda_mac_2_tx_axis_tdata_int), - .mac_3_tx_axis_tkeep(qsfpdda_mac_2_tx_axis_tkeep_int), - .mac_3_tx_axis_tvalid(qsfpdda_mac_2_tx_axis_tvalid_int), - .mac_3_tx_axis_tready(qsfpdda_mac_2_tx_axis_tready_int), - .mac_3_tx_axis_tlast(qsfpdda_mac_2_tx_axis_tlast_int), - .mac_3_tx_axis_tuser(qsfpdda_mac_2_tx_axis_tuser_int), - - .mac_3_tx_status(qsfpdda_mac_2_tx_status_int), - .mac_3_tx_lfc_req(qsfpdda_mac_2_tx_lfc_req_int), - .mac_3_tx_pfc_req(qsfpdda_mac_2_tx_pfc_req_int), - - .mac_3_rx_clk(qsfpdda_mac_2_rx_clk_int), - .mac_3_rx_rst(qsfpdda_mac_2_rx_rst_int), - - .mac_3_rx_ptp_clk(qsfpdda_mac_2_rx_ptp_clk_int), - .mac_3_rx_ptp_rst(qsfpdda_mac_2_rx_ptp_rst_int), - .mac_3_rx_ptp_time(qsfpdda_mac_2_rx_ptp_time_int), - - .mac_3_rx_axis_tdata(qsfpdda_mac_2_rx_axis_tdata_int), - .mac_3_rx_axis_tkeep(qsfpdda_mac_2_rx_axis_tkeep_int), - .mac_3_rx_axis_tvalid(qsfpdda_mac_2_rx_axis_tvalid_int), - .mac_3_rx_axis_tlast(qsfpdda_mac_2_rx_axis_tlast_int), - .mac_3_rx_axis_tuser(qsfpdda_mac_2_rx_axis_tuser_int), - - .mac_3_rx_status(qsfpdda_mac_2_rx_status_int), - .mac_3_rx_lfc_req(qsfpdda_mac_2_rx_lfc_req_int), - .mac_3_rx_pfc_req(qsfpdda_mac_2_rx_pfc_req_int), - - .mac_4_tx_clk(qsfpdda_mac_4_tx_clk_int), - .mac_4_tx_rst(qsfpdda_mac_4_tx_rst_int), - - .mac_4_tx_ptp_clk(qsfpdda_mac_4_tx_ptp_clk_int), - .mac_4_tx_ptp_rst(qsfpdda_mac_4_tx_ptp_rst_int), - .mac_4_tx_ptp_time(qsfpdda_mac_4_tx_ptp_time_int), - - .mac_4_tx_ptp_ts(qsfpdda_mac_4_tx_ptp_ts_int), - .mac_4_tx_ptp_ts_tag(qsfpdda_mac_4_tx_ptp_ts_tag_int), - .mac_4_tx_ptp_ts_valid(qsfpdda_mac_4_tx_ptp_ts_valid_int), - - .mac_4_tx_axis_tdata(qsfpdda_mac_4_tx_axis_tdata_int), - .mac_4_tx_axis_tkeep(qsfpdda_mac_4_tx_axis_tkeep_int), - .mac_4_tx_axis_tvalid(qsfpdda_mac_4_tx_axis_tvalid_int), - .mac_4_tx_axis_tready(qsfpdda_mac_4_tx_axis_tready_int), - .mac_4_tx_axis_tlast(qsfpdda_mac_4_tx_axis_tlast_int), - .mac_4_tx_axis_tuser(qsfpdda_mac_4_tx_axis_tuser_int), - - .mac_4_tx_status(qsfpdda_mac_4_tx_status_int), - .mac_4_tx_lfc_req(qsfpdda_mac_4_tx_lfc_req_int), - .mac_4_tx_pfc_req(qsfpdda_mac_4_tx_pfc_req_int), - - .mac_4_rx_clk(qsfpdda_mac_4_rx_clk_int), - .mac_4_rx_rst(qsfpdda_mac_4_rx_rst_int), - - .mac_4_rx_ptp_clk(qsfpdda_mac_4_rx_ptp_clk_int), - .mac_4_rx_ptp_rst(qsfpdda_mac_4_rx_ptp_rst_int), - .mac_4_rx_ptp_time(qsfpdda_mac_4_rx_ptp_time_int), - - .mac_4_rx_axis_tdata(qsfpdda_mac_4_rx_axis_tdata_int), - .mac_4_rx_axis_tkeep(qsfpdda_mac_4_rx_axis_tkeep_int), - .mac_4_rx_axis_tvalid(qsfpdda_mac_4_rx_axis_tvalid_int), - .mac_4_rx_axis_tlast(qsfpdda_mac_4_rx_axis_tlast_int), - .mac_4_rx_axis_tuser(qsfpdda_mac_4_rx_axis_tuser_int), - - .mac_4_rx_status(qsfpdda_mac_4_rx_status_int), - .mac_4_rx_lfc_req(qsfpdda_mac_4_rx_lfc_req_int), - .mac_4_rx_pfc_req(qsfpdda_mac_4_rx_pfc_req_int), - - .mac_5_tx_clk(qsfpdda_mac_5_tx_clk_int), - .mac_5_tx_rst(qsfpdda_mac_5_tx_rst_int), - - .mac_5_tx_ptp_clk(qsfpdda_mac_5_tx_ptp_clk_int), - .mac_5_tx_ptp_rst(qsfpdda_mac_5_tx_ptp_rst_int), - .mac_5_tx_ptp_time(qsfpdda_mac_5_tx_ptp_time_int), - - .mac_5_tx_ptp_ts(qsfpdda_mac_5_tx_ptp_ts_int), - .mac_5_tx_ptp_ts_tag(qsfpdda_mac_5_tx_ptp_ts_tag_int), - .mac_5_tx_ptp_ts_valid(qsfpdda_mac_5_tx_ptp_ts_valid_int), - - .mac_5_tx_axis_tdata(qsfpdda_mac_5_tx_axis_tdata_int), - .mac_5_tx_axis_tkeep(qsfpdda_mac_5_tx_axis_tkeep_int), - .mac_5_tx_axis_tvalid(qsfpdda_mac_5_tx_axis_tvalid_int), - .mac_5_tx_axis_tready(qsfpdda_mac_5_tx_axis_tready_int), - .mac_5_tx_axis_tlast(qsfpdda_mac_5_tx_axis_tlast_int), - .mac_5_tx_axis_tuser(qsfpdda_mac_5_tx_axis_tuser_int), - - .mac_5_tx_status(qsfpdda_mac_5_tx_status_int), - .mac_5_tx_lfc_req(qsfpdda_mac_5_tx_lfc_req_int), - .mac_5_tx_pfc_req(qsfpdda_mac_5_tx_pfc_req_int), - - .mac_5_rx_clk(qsfpdda_mac_5_rx_clk_int), - .mac_5_rx_rst(qsfpdda_mac_5_rx_rst_int), - - .mac_5_rx_ptp_clk(qsfpdda_mac_5_rx_ptp_clk_int), - .mac_5_rx_ptp_rst(qsfpdda_mac_5_rx_ptp_rst_int), - .mac_5_rx_ptp_time(qsfpdda_mac_5_rx_ptp_time_int), - - .mac_5_rx_axis_tdata(qsfpdda_mac_5_rx_axis_tdata_int), - .mac_5_rx_axis_tkeep(qsfpdda_mac_5_rx_axis_tkeep_int), - .mac_5_rx_axis_tvalid(qsfpdda_mac_5_rx_axis_tvalid_int), - .mac_5_rx_axis_tlast(qsfpdda_mac_5_rx_axis_tlast_int), - .mac_5_rx_axis_tuser(qsfpdda_mac_5_rx_axis_tuser_int), - - .mac_5_rx_status(qsfpdda_mac_5_rx_status_int), - .mac_5_rx_lfc_req(qsfpdda_mac_5_rx_lfc_req_int), - .mac_5_rx_pfc_req(qsfpdda_mac_5_rx_pfc_req_int), - - .mac_6_tx_clk(qsfpdda_mac_7_tx_clk_int), - .mac_6_tx_rst(qsfpdda_mac_7_tx_rst_int), - - .mac_6_tx_ptp_clk(qsfpdda_mac_7_tx_ptp_clk_int), - .mac_6_tx_ptp_rst(qsfpdda_mac_7_tx_ptp_rst_int), - .mac_6_tx_ptp_time(qsfpdda_mac_7_tx_ptp_time_int), - - .mac_6_tx_ptp_ts(qsfpdda_mac_7_tx_ptp_ts_int), - .mac_6_tx_ptp_ts_tag(qsfpdda_mac_7_tx_ptp_ts_tag_int), - .mac_6_tx_ptp_ts_valid(qsfpdda_mac_7_tx_ptp_ts_valid_int), - - .mac_6_tx_axis_tdata(qsfpdda_mac_7_tx_axis_tdata_int), - .mac_6_tx_axis_tkeep(qsfpdda_mac_7_tx_axis_tkeep_int), - .mac_6_tx_axis_tvalid(qsfpdda_mac_7_tx_axis_tvalid_int), - .mac_6_tx_axis_tready(qsfpdda_mac_7_tx_axis_tready_int), - .mac_6_tx_axis_tlast(qsfpdda_mac_7_tx_axis_tlast_int), - .mac_6_tx_axis_tuser(qsfpdda_mac_7_tx_axis_tuser_int), - - .mac_6_tx_status(qsfpdda_mac_7_tx_status_int), - .mac_6_tx_lfc_req(qsfpdda_mac_7_tx_lfc_req_int), - .mac_6_tx_pfc_req(qsfpdda_mac_7_tx_pfc_req_int), - - .mac_6_rx_clk(qsfpdda_mac_7_rx_clk_int), - .mac_6_rx_rst(qsfpdda_mac_7_rx_rst_int), - - .mac_6_rx_ptp_clk(qsfpdda_mac_7_rx_ptp_clk_int), - .mac_6_rx_ptp_rst(qsfpdda_mac_7_rx_ptp_rst_int), - .mac_6_rx_ptp_time(qsfpdda_mac_7_rx_ptp_time_int), - - .mac_6_rx_axis_tdata(qsfpdda_mac_7_rx_axis_tdata_int), - .mac_6_rx_axis_tkeep(qsfpdda_mac_7_rx_axis_tkeep_int), - .mac_6_rx_axis_tvalid(qsfpdda_mac_7_rx_axis_tvalid_int), - .mac_6_rx_axis_tlast(qsfpdda_mac_7_rx_axis_tlast_int), - .mac_6_rx_axis_tuser(qsfpdda_mac_7_rx_axis_tuser_int), - - .mac_6_rx_status(qsfpdda_mac_7_rx_status_int), - .mac_6_rx_lfc_req(qsfpdda_mac_7_rx_lfc_req_int), - .mac_6_rx_pfc_req(qsfpdda_mac_7_rx_pfc_req_int), - - .mac_7_tx_clk(qsfpdda_mac_6_tx_clk_int), - .mac_7_tx_rst(qsfpdda_mac_6_tx_rst_int), - - .mac_7_tx_ptp_clk(qsfpdda_mac_6_tx_ptp_clk_int), - .mac_7_tx_ptp_rst(qsfpdda_mac_6_tx_ptp_rst_int), - .mac_7_tx_ptp_time(qsfpdda_mac_6_tx_ptp_time_int), - - .mac_7_tx_ptp_ts(qsfpdda_mac_6_tx_ptp_ts_int), - .mac_7_tx_ptp_ts_tag(qsfpdda_mac_6_tx_ptp_ts_tag_int), - .mac_7_tx_ptp_ts_valid(qsfpdda_mac_6_tx_ptp_ts_valid_int), - - .mac_7_tx_axis_tdata(qsfpdda_mac_6_tx_axis_tdata_int), - .mac_7_tx_axis_tkeep(qsfpdda_mac_6_tx_axis_tkeep_int), - .mac_7_tx_axis_tvalid(qsfpdda_mac_6_tx_axis_tvalid_int), - .mac_7_tx_axis_tready(qsfpdda_mac_6_tx_axis_tready_int), - .mac_7_tx_axis_tlast(qsfpdda_mac_6_tx_axis_tlast_int), - .mac_7_tx_axis_tuser(qsfpdda_mac_6_tx_axis_tuser_int), - - .mac_7_tx_status(qsfpdda_mac_6_tx_status_int), - .mac_7_tx_lfc_req(qsfpdda_mac_6_tx_lfc_req_int), - .mac_7_tx_pfc_req(qsfpdda_mac_6_tx_pfc_req_int), - - .mac_7_rx_clk(qsfpdda_mac_6_rx_clk_int), - .mac_7_rx_rst(qsfpdda_mac_6_rx_rst_int), - - .mac_7_rx_ptp_clk(qsfpdda_mac_6_rx_ptp_clk_int), - .mac_7_rx_ptp_rst(qsfpdda_mac_6_rx_ptp_rst_int), - .mac_7_rx_ptp_time(qsfpdda_mac_6_rx_ptp_time_int), - - .mac_7_rx_axis_tdata(qsfpdda_mac_6_rx_axis_tdata_int), - .mac_7_rx_axis_tkeep(qsfpdda_mac_6_rx_axis_tkeep_int), - .mac_7_rx_axis_tvalid(qsfpdda_mac_6_rx_axis_tvalid_int), - .mac_7_rx_axis_tlast(qsfpdda_mac_6_rx_axis_tlast_int), - .mac_7_rx_axis_tuser(qsfpdda_mac_6_rx_axis_tuser_int), - - .mac_7_rx_status(qsfpdda_mac_6_rx_status_int), - .mac_7_rx_lfc_req(qsfpdda_mac_6_rx_lfc_req_int), - .mac_7_rx_pfc_req(qsfpdda_mac_6_rx_pfc_req_int), - - .mac_8_tx_clk(qsfpdda_mac_8_tx_clk_int), - .mac_8_tx_rst(qsfpdda_mac_8_tx_rst_int), - - .mac_8_tx_ptp_clk(qsfpdda_mac_8_tx_ptp_clk_int), - .mac_8_tx_ptp_rst(qsfpdda_mac_8_tx_ptp_rst_int), - .mac_8_tx_ptp_time(qsfpdda_mac_8_tx_ptp_time_int), - - .mac_8_tx_ptp_ts(qsfpdda_mac_8_tx_ptp_ts_int), - .mac_8_tx_ptp_ts_tag(qsfpdda_mac_8_tx_ptp_ts_tag_int), - .mac_8_tx_ptp_ts_valid(qsfpdda_mac_8_tx_ptp_ts_valid_int), - - .mac_8_tx_axis_tdata(qsfpdda_mac_8_tx_axis_tdata_int), - .mac_8_tx_axis_tkeep(qsfpdda_mac_8_tx_axis_tkeep_int), - .mac_8_tx_axis_tvalid(qsfpdda_mac_8_tx_axis_tvalid_int), - .mac_8_tx_axis_tready(qsfpdda_mac_8_tx_axis_tready_int), - .mac_8_tx_axis_tlast(qsfpdda_mac_8_tx_axis_tlast_int), - .mac_8_tx_axis_tuser(qsfpdda_mac_8_tx_axis_tuser_int), - - .mac_8_tx_status(qsfpdda_mac_8_tx_status_int), - .mac_8_tx_lfc_req(qsfpdda_mac_8_tx_lfc_req_int), - .mac_8_tx_pfc_req(qsfpdda_mac_8_tx_pfc_req_int), - - .mac_8_rx_clk(qsfpdda_mac_8_rx_clk_int), - .mac_8_rx_rst(qsfpdda_mac_8_rx_rst_int), - - .mac_8_rx_ptp_clk(qsfpdda_mac_8_rx_ptp_clk_int), - .mac_8_rx_ptp_rst(qsfpdda_mac_8_rx_ptp_rst_int), - .mac_8_rx_ptp_time(qsfpdda_mac_8_rx_ptp_time_int), - - .mac_8_rx_axis_tdata(qsfpdda_mac_8_rx_axis_tdata_int), - .mac_8_rx_axis_tkeep(qsfpdda_mac_8_rx_axis_tkeep_int), - .mac_8_rx_axis_tvalid(qsfpdda_mac_8_rx_axis_tvalid_int), - .mac_8_rx_axis_tlast(qsfpdda_mac_8_rx_axis_tlast_int), - .mac_8_rx_axis_tuser(qsfpdda_mac_8_rx_axis_tuser_int), - - .mac_8_rx_status(qsfpdda_mac_8_rx_status_int), - .mac_8_rx_lfc_req(qsfpdda_mac_8_rx_lfc_req_int), - .mac_8_rx_pfc_req(qsfpdda_mac_8_rx_pfc_req_int) -); - -// QSFP-DD B -wire qsfpddb_mac_1_tx_clk_int; -wire qsfpddb_mac_1_tx_rst_int; - -wire qsfpddb_mac_1_tx_ptp_clk_int; -wire qsfpddb_mac_1_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_ts_tag_int; -wire qsfpddb_mac_1_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tkeep_int; -wire qsfpddb_mac_1_tx_axis_tvalid_int; -wire qsfpddb_mac_1_tx_axis_tready_int; -wire qsfpddb_mac_1_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tuser_int; - -wire qsfpddb_mac_1_tx_status_int; -wire qsfpddb_mac_1_tx_lfc_req_int; -wire [7:0] qsfpddb_mac_1_tx_pfc_req_int; - -wire qsfpddb_mac_1_rx_clk_int; -wire qsfpddb_mac_1_rx_rst_int; - -wire qsfpddb_mac_1_rx_ptp_clk_int; -wire qsfpddb_mac_1_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tkeep_int; -wire qsfpddb_mac_1_rx_axis_tvalid_int; -wire qsfpddb_mac_1_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tuser_int; - -wire qsfpddb_mac_1_rx_status_int; -wire qsfpddb_mac_1_rx_lfc_req_int; -wire [7:0] qsfpddb_mac_1_rx_pfc_req_int; - -wire qsfpddb_mac_2_tx_clk_int; -wire qsfpddb_mac_2_tx_rst_int; - -wire qsfpddb_mac_2_tx_ptp_clk_int; -wire qsfpddb_mac_2_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_ts_tag_int; -wire qsfpddb_mac_2_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tkeep_int; -wire qsfpddb_mac_2_tx_axis_tvalid_int; -wire qsfpddb_mac_2_tx_axis_tready_int; -wire qsfpddb_mac_2_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tuser_int; - -wire qsfpddb_mac_2_tx_status_int; -wire qsfpddb_mac_2_tx_lfc_req_int; -wire [7:0] qsfpddb_mac_2_tx_pfc_req_int; - -wire qsfpddb_mac_2_rx_clk_int; -wire qsfpddb_mac_2_rx_rst_int; - -wire qsfpddb_mac_2_rx_ptp_clk_int; -wire qsfpddb_mac_2_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tkeep_int; -wire qsfpddb_mac_2_rx_axis_tvalid_int; -wire qsfpddb_mac_2_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tuser_int; - -wire qsfpddb_mac_2_rx_status_int; -wire qsfpddb_mac_2_rx_lfc_req_int; -wire [7:0] qsfpddb_mac_2_rx_pfc_req_int; - -wire qsfpddb_mac_3_tx_clk_int; -wire qsfpddb_mac_3_tx_rst_int; - -wire qsfpddb_mac_3_tx_ptp_clk_int; -wire qsfpddb_mac_3_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_3_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_3_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_3_tx_ptp_ts_tag_int; -wire qsfpddb_mac_3_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_3_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_3_tx_axis_tkeep_int; -wire qsfpddb_mac_3_tx_axis_tvalid_int; -wire qsfpddb_mac_3_tx_axis_tready_int; -wire qsfpddb_mac_3_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_3_tx_axis_tuser_int; - -wire qsfpddb_mac_3_tx_status_int; -wire qsfpddb_mac_3_tx_lfc_req_int; -wire [7:0] qsfpddb_mac_3_tx_pfc_req_int; - -wire qsfpddb_mac_3_rx_clk_int; -wire qsfpddb_mac_3_rx_rst_int; - -wire qsfpddb_mac_3_rx_ptp_clk_int; -wire qsfpddb_mac_3_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_3_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_3_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_3_rx_axis_tkeep_int; -wire qsfpddb_mac_3_rx_axis_tvalid_int; -wire qsfpddb_mac_3_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_3_rx_axis_tuser_int; - -wire qsfpddb_mac_3_rx_status_int; -wire qsfpddb_mac_3_rx_lfc_req_int; -wire [7:0] qsfpddb_mac_3_rx_pfc_req_int; - -wire qsfpddb_mac_4_tx_clk_int; -wire qsfpddb_mac_4_tx_rst_int; - -wire qsfpddb_mac_4_tx_ptp_clk_int; -wire qsfpddb_mac_4_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_4_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_4_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_4_tx_ptp_ts_tag_int; -wire qsfpddb_mac_4_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_4_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_4_tx_axis_tkeep_int; -wire qsfpddb_mac_4_tx_axis_tvalid_int; -wire qsfpddb_mac_4_tx_axis_tready_int; -wire qsfpddb_mac_4_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_4_tx_axis_tuser_int; - -wire qsfpddb_mac_4_tx_status_int; -wire qsfpddb_mac_4_tx_lfc_req_int; -wire [7:0] qsfpddb_mac_4_tx_pfc_req_int; - -wire qsfpddb_mac_4_rx_clk_int; -wire qsfpddb_mac_4_rx_rst_int; - -wire qsfpddb_mac_4_rx_ptp_clk_int; -wire qsfpddb_mac_4_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_4_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_4_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_4_rx_axis_tkeep_int; -wire qsfpddb_mac_4_rx_axis_tvalid_int; -wire qsfpddb_mac_4_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_4_rx_axis_tuser_int; - -wire qsfpddb_mac_4_rx_status_int; -wire qsfpddb_mac_4_rx_lfc_req_int; -wire [7:0] qsfpddb_mac_4_rx_pfc_req_int; - -wire qsfpddb_mac_5_tx_clk_int; -wire qsfpddb_mac_5_tx_rst_int; - -wire qsfpddb_mac_5_tx_ptp_clk_int; -wire qsfpddb_mac_5_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_5_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_5_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_5_tx_ptp_ts_tag_int; -wire qsfpddb_mac_5_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_5_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_5_tx_axis_tkeep_int; -wire qsfpddb_mac_5_tx_axis_tvalid_int; -wire qsfpddb_mac_5_tx_axis_tready_int; -wire qsfpddb_mac_5_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_5_tx_axis_tuser_int; - -wire qsfpddb_mac_5_tx_status_int; -wire qsfpddb_mac_5_tx_lfc_req_int; -wire [7:0] qsfpddb_mac_5_tx_pfc_req_int; - -wire qsfpddb_mac_5_rx_clk_int; -wire qsfpddb_mac_5_rx_rst_int; - -wire qsfpddb_mac_5_rx_ptp_clk_int; -wire qsfpddb_mac_5_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_5_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_5_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_5_rx_axis_tkeep_int; -wire qsfpddb_mac_5_rx_axis_tvalid_int; -wire qsfpddb_mac_5_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_5_rx_axis_tuser_int; - -wire qsfpddb_mac_5_rx_status_int; -wire qsfpddb_mac_5_rx_lfc_req_int; -wire [7:0] qsfpddb_mac_5_rx_pfc_req_int; - -wire qsfpddb_mac_6_tx_clk_int; -wire qsfpddb_mac_6_tx_rst_int; - -wire qsfpddb_mac_6_tx_ptp_clk_int; -wire qsfpddb_mac_6_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_6_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_6_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_6_tx_ptp_ts_tag_int; -wire qsfpddb_mac_6_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_6_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_6_tx_axis_tkeep_int; -wire qsfpddb_mac_6_tx_axis_tvalid_int; -wire qsfpddb_mac_6_tx_axis_tready_int; -wire qsfpddb_mac_6_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_6_tx_axis_tuser_int; - -wire qsfpddb_mac_6_tx_status_int; -wire qsfpddb_mac_6_tx_lfc_req_int; -wire [7:0] qsfpddb_mac_6_tx_pfc_req_int; - -wire qsfpddb_mac_6_rx_clk_int; -wire qsfpddb_mac_6_rx_rst_int; - -wire qsfpddb_mac_6_rx_ptp_clk_int; -wire qsfpddb_mac_6_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_6_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_6_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_6_rx_axis_tkeep_int; -wire qsfpddb_mac_6_rx_axis_tvalid_int; -wire qsfpddb_mac_6_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_6_rx_axis_tuser_int; - -wire qsfpddb_mac_6_rx_status_int; -wire qsfpddb_mac_6_rx_lfc_req_int; -wire [7:0] qsfpddb_mac_6_rx_pfc_req_int; - -wire qsfpddb_mac_7_tx_clk_int; -wire qsfpddb_mac_7_tx_rst_int; - -wire qsfpddb_mac_7_tx_ptp_clk_int; -wire qsfpddb_mac_7_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_7_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_7_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_7_tx_ptp_ts_tag_int; -wire qsfpddb_mac_7_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_7_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_7_tx_axis_tkeep_int; -wire qsfpddb_mac_7_tx_axis_tvalid_int; -wire qsfpddb_mac_7_tx_axis_tready_int; -wire qsfpddb_mac_7_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_7_tx_axis_tuser_int; - -wire qsfpddb_mac_7_tx_status_int; -wire qsfpddb_mac_7_tx_lfc_req_int; -wire [7:0] qsfpddb_mac_7_tx_pfc_req_int; - -wire qsfpddb_mac_7_rx_clk_int; -wire qsfpddb_mac_7_rx_rst_int; - -wire qsfpddb_mac_7_rx_ptp_clk_int; -wire qsfpddb_mac_7_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_7_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_7_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_7_rx_axis_tkeep_int; -wire qsfpddb_mac_7_rx_axis_tvalid_int; -wire qsfpddb_mac_7_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_7_rx_axis_tuser_int; - -wire qsfpddb_mac_7_rx_status_int; -wire qsfpddb_mac_7_rx_lfc_req_int; -wire [7:0] qsfpddb_mac_7_rx_pfc_req_int; - -wire qsfpddb_mac_8_tx_clk_int; -wire qsfpddb_mac_8_tx_rst_int; - -wire qsfpddb_mac_8_tx_ptp_clk_int; -wire qsfpddb_mac_8_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_8_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_8_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_8_tx_ptp_ts_tag_int; -wire qsfpddb_mac_8_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_8_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_8_tx_axis_tkeep_int; -wire qsfpddb_mac_8_tx_axis_tvalid_int; -wire qsfpddb_mac_8_tx_axis_tready_int; -wire qsfpddb_mac_8_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_8_tx_axis_tuser_int; - -wire qsfpddb_mac_8_tx_status_int; -wire qsfpddb_mac_8_tx_lfc_req_int; -wire [7:0] qsfpddb_mac_8_tx_pfc_req_int; - -wire qsfpddb_mac_8_rx_clk_int; -wire qsfpddb_mac_8_rx_rst_int; - -wire qsfpddb_mac_8_rx_ptp_clk_int; -wire qsfpddb_mac_8_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_8_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_8_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_8_rx_axis_tkeep_int; -wire qsfpddb_mac_8_rx_axis_tvalid_int; -wire qsfpddb_mac_8_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_8_rx_axis_tuser_int; - -wire qsfpddb_mac_8_rx_status_int; -wire qsfpddb_mac_8_rx_lfc_req_int; -wire [7:0] qsfpddb_mac_8_rx_pfc_req_int; - -eth_mac_dual_quad_wrapper #( - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .MAC_RSFEC(MAC_RSFEC) -) -qsfpddb_mac_inst ( - .ctrl_clk(clk_100mhz), - .ctrl_rst(rst_100mhz), - - .tx_serial_data_p({qsfpddb_tx_p[7], qsfpddb_tx_p[5], qsfpddb_tx_p[6], qsfpddb_tx_p[4], qsfpddb_tx_p[3], qsfpddb_tx_p[1], qsfpddb_tx_p[2], qsfpddb_tx_p[0]}), - .tx_serial_data_n({qsfpddb_tx_n[7], qsfpddb_tx_n[5], qsfpddb_tx_n[6], qsfpddb_tx_n[4], qsfpddb_tx_n[3], qsfpddb_tx_n[1], qsfpddb_tx_n[2], qsfpddb_tx_n[0]}), - .rx_serial_data_p({qsfpddb_rx_p[7], qsfpddb_rx_p[5], qsfpddb_rx_p[6], qsfpddb_rx_p[4], qsfpddb_rx_p[3], qsfpddb_rx_p[1], qsfpddb_rx_p[2], qsfpddb_rx_p[0]}), - .rx_serial_data_n({qsfpddb_rx_n[7], qsfpddb_rx_n[5], qsfpddb_rx_n[6], qsfpddb_rx_n[4], qsfpddb_rx_n[3], qsfpddb_rx_n[1], qsfpddb_rx_n[2], qsfpddb_rx_n[0]}), - .ref_clk(qsfpddb_refclk_p), - .ptp_sample_clk(etile_ptp_sample_clk), - - .mac_1_tx_clk(qsfpddb_mac_1_tx_clk_int), - .mac_1_tx_rst(qsfpddb_mac_1_tx_rst_int), - - .mac_1_tx_ptp_clk(qsfpddb_mac_1_tx_ptp_clk_int), - .mac_1_tx_ptp_rst(qsfpddb_mac_1_tx_ptp_rst_int), - .mac_1_tx_ptp_time(qsfpddb_mac_1_tx_ptp_time_int), - - .mac_1_tx_ptp_ts(qsfpddb_mac_1_tx_ptp_ts_int), - .mac_1_tx_ptp_ts_tag(qsfpddb_mac_1_tx_ptp_ts_tag_int), - .mac_1_tx_ptp_ts_valid(qsfpddb_mac_1_tx_ptp_ts_valid_int), - - .mac_1_tx_axis_tdata(qsfpddb_mac_1_tx_axis_tdata_int), - .mac_1_tx_axis_tkeep(qsfpddb_mac_1_tx_axis_tkeep_int), - .mac_1_tx_axis_tvalid(qsfpddb_mac_1_tx_axis_tvalid_int), - .mac_1_tx_axis_tready(qsfpddb_mac_1_tx_axis_tready_int), - .mac_1_tx_axis_tlast(qsfpddb_mac_1_tx_axis_tlast_int), - .mac_1_tx_axis_tuser(qsfpddb_mac_1_tx_axis_tuser_int), - - .mac_1_tx_status(qsfpddb_mac_1_tx_status_int), - .mac_1_tx_lfc_req(qsfpddb_mac_1_tx_lfc_req_int), - .mac_1_tx_pfc_req(qsfpddb_mac_1_tx_pfc_req_int), - - .mac_1_rx_clk(qsfpddb_mac_1_rx_clk_int), - .mac_1_rx_rst(qsfpddb_mac_1_rx_rst_int), - - .mac_1_rx_ptp_clk(qsfpddb_mac_1_rx_ptp_clk_int), - .mac_1_rx_ptp_rst(qsfpddb_mac_1_rx_ptp_rst_int), - .mac_1_rx_ptp_time(qsfpddb_mac_1_rx_ptp_time_int), - - .mac_1_rx_axis_tdata(qsfpddb_mac_1_rx_axis_tdata_int), - .mac_1_rx_axis_tkeep(qsfpddb_mac_1_rx_axis_tkeep_int), - .mac_1_rx_axis_tvalid(qsfpddb_mac_1_rx_axis_tvalid_int), - .mac_1_rx_axis_tlast(qsfpddb_mac_1_rx_axis_tlast_int), - .mac_1_rx_axis_tuser(qsfpddb_mac_1_rx_axis_tuser_int), - - .mac_1_rx_status(qsfpddb_mac_1_rx_status_int), - .mac_1_rx_lfc_req(qsfpddb_mac_1_rx_lfc_req_int), - .mac_1_rx_pfc_req(qsfpddb_mac_1_rx_pfc_req_int), - - .mac_2_tx_clk(qsfpddb_mac_3_tx_clk_int), - .mac_2_tx_rst(qsfpddb_mac_3_tx_rst_int), - - .mac_2_tx_ptp_clk(qsfpddb_mac_3_tx_ptp_clk_int), - .mac_2_tx_ptp_rst(qsfpddb_mac_3_tx_ptp_rst_int), - .mac_2_tx_ptp_time(qsfpddb_mac_3_tx_ptp_time_int), - - .mac_2_tx_ptp_ts(qsfpddb_mac_3_tx_ptp_ts_int), - .mac_2_tx_ptp_ts_tag(qsfpddb_mac_3_tx_ptp_ts_tag_int), - .mac_2_tx_ptp_ts_valid(qsfpddb_mac_3_tx_ptp_ts_valid_int), - - .mac_2_tx_axis_tdata(qsfpddb_mac_3_tx_axis_tdata_int), - .mac_2_tx_axis_tkeep(qsfpddb_mac_3_tx_axis_tkeep_int), - .mac_2_tx_axis_tvalid(qsfpddb_mac_3_tx_axis_tvalid_int), - .mac_2_tx_axis_tready(qsfpddb_mac_3_tx_axis_tready_int), - .mac_2_tx_axis_tlast(qsfpddb_mac_3_tx_axis_tlast_int), - .mac_2_tx_axis_tuser(qsfpddb_mac_3_tx_axis_tuser_int), - - .mac_2_tx_status(qsfpddb_mac_3_tx_status_int), - .mac_2_tx_lfc_req(qsfpddb_mac_3_tx_lfc_req_int), - .mac_2_tx_pfc_req(qsfpddb_mac_3_tx_pfc_req_int), - - .mac_2_rx_clk(qsfpddb_mac_3_rx_clk_int), - .mac_2_rx_rst(qsfpddb_mac_3_rx_rst_int), - - .mac_2_rx_ptp_clk(qsfpddb_mac_3_rx_ptp_clk_int), - .mac_2_rx_ptp_rst(qsfpddb_mac_3_rx_ptp_rst_int), - .mac_2_rx_ptp_time(qsfpddb_mac_3_rx_ptp_time_int), - - .mac_2_rx_axis_tdata(qsfpddb_mac_3_rx_axis_tdata_int), - .mac_2_rx_axis_tkeep(qsfpddb_mac_3_rx_axis_tkeep_int), - .mac_2_rx_axis_tvalid(qsfpddb_mac_3_rx_axis_tvalid_int), - .mac_2_rx_axis_tlast(qsfpddb_mac_3_rx_axis_tlast_int), - .mac_2_rx_axis_tuser(qsfpddb_mac_3_rx_axis_tuser_int), - - .mac_2_rx_status(qsfpddb_mac_3_rx_status_int), - .mac_2_rx_lfc_req(qsfpddb_mac_3_rx_lfc_req_int), - .mac_2_rx_pfc_req(qsfpddb_mac_3_rx_pfc_req_int), - - .mac_3_tx_clk(qsfpddb_mac_2_tx_clk_int), - .mac_3_tx_rst(qsfpddb_mac_2_tx_rst_int), - - .mac_3_tx_ptp_clk(qsfpddb_mac_2_tx_ptp_clk_int), - .mac_3_tx_ptp_rst(qsfpddb_mac_2_tx_ptp_rst_int), - .mac_3_tx_ptp_time(qsfpddb_mac_2_tx_ptp_time_int), - - .mac_3_tx_ptp_ts(qsfpddb_mac_2_tx_ptp_ts_int), - .mac_3_tx_ptp_ts_tag(qsfpddb_mac_2_tx_ptp_ts_tag_int), - .mac_3_tx_ptp_ts_valid(qsfpddb_mac_2_tx_ptp_ts_valid_int), - - .mac_3_tx_axis_tdata(qsfpddb_mac_2_tx_axis_tdata_int), - .mac_3_tx_axis_tkeep(qsfpddb_mac_2_tx_axis_tkeep_int), - .mac_3_tx_axis_tvalid(qsfpddb_mac_2_tx_axis_tvalid_int), - .mac_3_tx_axis_tready(qsfpddb_mac_2_tx_axis_tready_int), - .mac_3_tx_axis_tlast(qsfpddb_mac_2_tx_axis_tlast_int), - .mac_3_tx_axis_tuser(qsfpddb_mac_2_tx_axis_tuser_int), - - .mac_3_tx_status(qsfpddb_mac_2_tx_status_int), - .mac_3_tx_lfc_req(qsfpddb_mac_2_tx_lfc_req_int), - .mac_3_tx_pfc_req(qsfpddb_mac_2_tx_pfc_req_int), - - .mac_3_rx_clk(qsfpddb_mac_2_rx_clk_int), - .mac_3_rx_rst(qsfpddb_mac_2_rx_rst_int), - - .mac_3_rx_ptp_clk(qsfpddb_mac_2_rx_ptp_clk_int), - .mac_3_rx_ptp_rst(qsfpddb_mac_2_rx_ptp_rst_int), - .mac_3_rx_ptp_time(qsfpddb_mac_2_rx_ptp_time_int), - - .mac_3_rx_axis_tdata(qsfpddb_mac_2_rx_axis_tdata_int), - .mac_3_rx_axis_tkeep(qsfpddb_mac_2_rx_axis_tkeep_int), - .mac_3_rx_axis_tvalid(qsfpddb_mac_2_rx_axis_tvalid_int), - .mac_3_rx_axis_tlast(qsfpddb_mac_2_rx_axis_tlast_int), - .mac_3_rx_axis_tuser(qsfpddb_mac_2_rx_axis_tuser_int), - - .mac_3_rx_status(qsfpddb_mac_2_rx_status_int), - .mac_3_rx_lfc_req(qsfpddb_mac_2_rx_lfc_req_int), - .mac_3_rx_pfc_req(qsfpddb_mac_2_rx_pfc_req_int), - - .mac_4_tx_clk(qsfpddb_mac_4_tx_clk_int), - .mac_4_tx_rst(qsfpddb_mac_4_tx_rst_int), - - .mac_4_tx_ptp_clk(qsfpddb_mac_4_tx_ptp_clk_int), - .mac_4_tx_ptp_rst(qsfpddb_mac_4_tx_ptp_rst_int), - .mac_4_tx_ptp_time(qsfpddb_mac_4_tx_ptp_time_int), - - .mac_4_tx_ptp_ts(qsfpddb_mac_4_tx_ptp_ts_int), - .mac_4_tx_ptp_ts_tag(qsfpddb_mac_4_tx_ptp_ts_tag_int), - .mac_4_tx_ptp_ts_valid(qsfpddb_mac_4_tx_ptp_ts_valid_int), - - .mac_4_tx_axis_tdata(qsfpddb_mac_4_tx_axis_tdata_int), - .mac_4_tx_axis_tkeep(qsfpddb_mac_4_tx_axis_tkeep_int), - .mac_4_tx_axis_tvalid(qsfpddb_mac_4_tx_axis_tvalid_int), - .mac_4_tx_axis_tready(qsfpddb_mac_4_tx_axis_tready_int), - .mac_4_tx_axis_tlast(qsfpddb_mac_4_tx_axis_tlast_int), - .mac_4_tx_axis_tuser(qsfpddb_mac_4_tx_axis_tuser_int), - - .mac_4_tx_status(qsfpddb_mac_4_tx_status_int), - .mac_4_tx_lfc_req(qsfpddb_mac_4_tx_lfc_req_int), - .mac_4_tx_pfc_req(qsfpddb_mac_4_tx_pfc_req_int), - - .mac_4_rx_clk(qsfpddb_mac_4_rx_clk_int), - .mac_4_rx_rst(qsfpddb_mac_4_rx_rst_int), - - .mac_4_rx_ptp_clk(qsfpddb_mac_4_rx_ptp_clk_int), - .mac_4_rx_ptp_rst(qsfpddb_mac_4_rx_ptp_rst_int), - .mac_4_rx_ptp_time(qsfpddb_mac_4_rx_ptp_time_int), - - .mac_4_rx_axis_tdata(qsfpddb_mac_4_rx_axis_tdata_int), - .mac_4_rx_axis_tkeep(qsfpddb_mac_4_rx_axis_tkeep_int), - .mac_4_rx_axis_tvalid(qsfpddb_mac_4_rx_axis_tvalid_int), - .mac_4_rx_axis_tlast(qsfpddb_mac_4_rx_axis_tlast_int), - .mac_4_rx_axis_tuser(qsfpddb_mac_4_rx_axis_tuser_int), - - .mac_4_rx_status(qsfpddb_mac_4_rx_status_int), - .mac_4_rx_lfc_req(qsfpddb_mac_4_rx_lfc_req_int), - .mac_4_rx_pfc_req(qsfpddb_mac_4_rx_pfc_req_int), - - .mac_5_tx_clk(qsfpddb_mac_5_tx_clk_int), - .mac_5_tx_rst(qsfpddb_mac_5_tx_rst_int), - - .mac_5_tx_ptp_clk(qsfpddb_mac_5_tx_ptp_clk_int), - .mac_5_tx_ptp_rst(qsfpddb_mac_5_tx_ptp_rst_int), - .mac_5_tx_ptp_time(qsfpddb_mac_5_tx_ptp_time_int), - - .mac_5_tx_ptp_ts(qsfpddb_mac_5_tx_ptp_ts_int), - .mac_5_tx_ptp_ts_tag(qsfpddb_mac_5_tx_ptp_ts_tag_int), - .mac_5_tx_ptp_ts_valid(qsfpddb_mac_5_tx_ptp_ts_valid_int), - - .mac_5_tx_axis_tdata(qsfpddb_mac_5_tx_axis_tdata_int), - .mac_5_tx_axis_tkeep(qsfpddb_mac_5_tx_axis_tkeep_int), - .mac_5_tx_axis_tvalid(qsfpddb_mac_5_tx_axis_tvalid_int), - .mac_5_tx_axis_tready(qsfpddb_mac_5_tx_axis_tready_int), - .mac_5_tx_axis_tlast(qsfpddb_mac_5_tx_axis_tlast_int), - .mac_5_tx_axis_tuser(qsfpddb_mac_5_tx_axis_tuser_int), - - .mac_5_tx_status(qsfpddb_mac_5_tx_status_int), - .mac_5_tx_lfc_req(qsfpddb_mac_5_tx_lfc_req_int), - .mac_5_tx_pfc_req(qsfpddb_mac_5_tx_pfc_req_int), - - .mac_5_rx_clk(qsfpddb_mac_5_rx_clk_int), - .mac_5_rx_rst(qsfpddb_mac_5_rx_rst_int), - - .mac_5_rx_ptp_clk(qsfpddb_mac_5_rx_ptp_clk_int), - .mac_5_rx_ptp_rst(qsfpddb_mac_5_rx_ptp_rst_int), - .mac_5_rx_ptp_time(qsfpddb_mac_5_rx_ptp_time_int), - - .mac_5_rx_axis_tdata(qsfpddb_mac_5_rx_axis_tdata_int), - .mac_5_rx_axis_tkeep(qsfpddb_mac_5_rx_axis_tkeep_int), - .mac_5_rx_axis_tvalid(qsfpddb_mac_5_rx_axis_tvalid_int), - .mac_5_rx_axis_tlast(qsfpddb_mac_5_rx_axis_tlast_int), - .mac_5_rx_axis_tuser(qsfpddb_mac_5_rx_axis_tuser_int), - - .mac_5_rx_status(qsfpddb_mac_5_rx_status_int), - .mac_5_rx_lfc_req(qsfpddb_mac_5_rx_lfc_req_int), - .mac_5_rx_pfc_req(qsfpddb_mac_5_rx_pfc_req_int), - - .mac_6_tx_clk(qsfpddb_mac_7_tx_clk_int), - .mac_6_tx_rst(qsfpddb_mac_7_tx_rst_int), - - .mac_6_tx_ptp_clk(qsfpddb_mac_7_tx_ptp_clk_int), - .mac_6_tx_ptp_rst(qsfpddb_mac_7_tx_ptp_rst_int), - .mac_6_tx_ptp_time(qsfpddb_mac_7_tx_ptp_time_int), - - .mac_6_tx_ptp_ts(qsfpddb_mac_7_tx_ptp_ts_int), - .mac_6_tx_ptp_ts_tag(qsfpddb_mac_7_tx_ptp_ts_tag_int), - .mac_6_tx_ptp_ts_valid(qsfpddb_mac_7_tx_ptp_ts_valid_int), - - .mac_6_tx_axis_tdata(qsfpddb_mac_7_tx_axis_tdata_int), - .mac_6_tx_axis_tkeep(qsfpddb_mac_7_tx_axis_tkeep_int), - .mac_6_tx_axis_tvalid(qsfpddb_mac_7_tx_axis_tvalid_int), - .mac_6_tx_axis_tready(qsfpddb_mac_7_tx_axis_tready_int), - .mac_6_tx_axis_tlast(qsfpddb_mac_7_tx_axis_tlast_int), - .mac_6_tx_axis_tuser(qsfpddb_mac_7_tx_axis_tuser_int), - - .mac_6_tx_status(qsfpddb_mac_7_tx_status_int), - .mac_6_tx_lfc_req(qsfpddb_mac_7_tx_lfc_req_int), - .mac_6_tx_pfc_req(qsfpddb_mac_7_tx_pfc_req_int), - - .mac_6_rx_clk(qsfpddb_mac_7_rx_clk_int), - .mac_6_rx_rst(qsfpddb_mac_7_rx_rst_int), - - .mac_6_rx_ptp_clk(qsfpddb_mac_7_rx_ptp_clk_int), - .mac_6_rx_ptp_rst(qsfpddb_mac_7_rx_ptp_rst_int), - .mac_6_rx_ptp_time(qsfpddb_mac_7_rx_ptp_time_int), - - .mac_6_rx_axis_tdata(qsfpddb_mac_7_rx_axis_tdata_int), - .mac_6_rx_axis_tkeep(qsfpddb_mac_7_rx_axis_tkeep_int), - .mac_6_rx_axis_tvalid(qsfpddb_mac_7_rx_axis_tvalid_int), - .mac_6_rx_axis_tlast(qsfpddb_mac_7_rx_axis_tlast_int), - .mac_6_rx_axis_tuser(qsfpddb_mac_7_rx_axis_tuser_int), - - .mac_6_rx_status(qsfpddb_mac_7_rx_status_int), - .mac_6_rx_lfc_req(qsfpddb_mac_7_rx_lfc_req_int), - .mac_6_rx_pfc_req(qsfpddb_mac_7_rx_pfc_req_int), - - .mac_7_tx_clk(qsfpddb_mac_6_tx_clk_int), - .mac_7_tx_rst(qsfpddb_mac_6_tx_rst_int), - - .mac_7_tx_ptp_clk(qsfpddb_mac_6_tx_ptp_clk_int), - .mac_7_tx_ptp_rst(qsfpddb_mac_6_tx_ptp_rst_int), - .mac_7_tx_ptp_time(qsfpddb_mac_6_tx_ptp_time_int), - - .mac_7_tx_ptp_ts(qsfpddb_mac_6_tx_ptp_ts_int), - .mac_7_tx_ptp_ts_tag(qsfpddb_mac_6_tx_ptp_ts_tag_int), - .mac_7_tx_ptp_ts_valid(qsfpddb_mac_6_tx_ptp_ts_valid_int), - - .mac_7_tx_axis_tdata(qsfpddb_mac_6_tx_axis_tdata_int), - .mac_7_tx_axis_tkeep(qsfpddb_mac_6_tx_axis_tkeep_int), - .mac_7_tx_axis_tvalid(qsfpddb_mac_6_tx_axis_tvalid_int), - .mac_7_tx_axis_tready(qsfpddb_mac_6_tx_axis_tready_int), - .mac_7_tx_axis_tlast(qsfpddb_mac_6_tx_axis_tlast_int), - .mac_7_tx_axis_tuser(qsfpddb_mac_6_tx_axis_tuser_int), - - .mac_7_tx_status(qsfpddb_mac_6_tx_status_int), - .mac_7_tx_lfc_req(qsfpddb_mac_6_tx_lfc_req_int), - .mac_7_tx_pfc_req(qsfpddb_mac_6_tx_pfc_req_int), - - .mac_7_rx_clk(qsfpddb_mac_6_rx_clk_int), - .mac_7_rx_rst(qsfpddb_mac_6_rx_rst_int), - - .mac_7_rx_ptp_clk(qsfpddb_mac_6_rx_ptp_clk_int), - .mac_7_rx_ptp_rst(qsfpddb_mac_6_rx_ptp_rst_int), - .mac_7_rx_ptp_time(qsfpddb_mac_6_rx_ptp_time_int), - - .mac_7_rx_axis_tdata(qsfpddb_mac_6_rx_axis_tdata_int), - .mac_7_rx_axis_tkeep(qsfpddb_mac_6_rx_axis_tkeep_int), - .mac_7_rx_axis_tvalid(qsfpddb_mac_6_rx_axis_tvalid_int), - .mac_7_rx_axis_tlast(qsfpddb_mac_6_rx_axis_tlast_int), - .mac_7_rx_axis_tuser(qsfpddb_mac_6_rx_axis_tuser_int), - - .mac_7_rx_status(qsfpddb_mac_6_rx_status_int), - .mac_7_rx_lfc_req(qsfpddb_mac_6_rx_lfc_req_int), - .mac_7_rx_pfc_req(qsfpddb_mac_6_rx_pfc_req_int), - - .mac_8_tx_clk(qsfpddb_mac_8_tx_clk_int), - .mac_8_tx_rst(qsfpddb_mac_8_tx_rst_int), - - .mac_8_tx_ptp_clk(qsfpddb_mac_8_tx_ptp_clk_int), - .mac_8_tx_ptp_rst(qsfpddb_mac_8_tx_ptp_rst_int), - .mac_8_tx_ptp_time(qsfpddb_mac_8_tx_ptp_time_int), - - .mac_8_tx_ptp_ts(qsfpddb_mac_8_tx_ptp_ts_int), - .mac_8_tx_ptp_ts_tag(qsfpddb_mac_8_tx_ptp_ts_tag_int), - .mac_8_tx_ptp_ts_valid(qsfpddb_mac_8_tx_ptp_ts_valid_int), - - .mac_8_tx_axis_tdata(qsfpddb_mac_8_tx_axis_tdata_int), - .mac_8_tx_axis_tkeep(qsfpddb_mac_8_tx_axis_tkeep_int), - .mac_8_tx_axis_tvalid(qsfpddb_mac_8_tx_axis_tvalid_int), - .mac_8_tx_axis_tready(qsfpddb_mac_8_tx_axis_tready_int), - .mac_8_tx_axis_tlast(qsfpddb_mac_8_tx_axis_tlast_int), - .mac_8_tx_axis_tuser(qsfpddb_mac_8_tx_axis_tuser_int), - - .mac_8_tx_status(qsfpddb_mac_8_tx_status_int), - .mac_8_tx_lfc_req(qsfpddb_mac_8_tx_lfc_req_int), - .mac_8_tx_pfc_req(qsfpddb_mac_8_tx_pfc_req_int), - - .mac_8_rx_clk(qsfpddb_mac_8_rx_clk_int), - .mac_8_rx_rst(qsfpddb_mac_8_rx_rst_int), - - .mac_8_rx_ptp_clk(qsfpddb_mac_8_rx_ptp_clk_int), - .mac_8_rx_ptp_rst(qsfpddb_mac_8_rx_ptp_rst_int), - .mac_8_rx_ptp_time(qsfpddb_mac_8_rx_ptp_time_int), - - .mac_8_rx_axis_tdata(qsfpddb_mac_8_rx_axis_tdata_int), - .mac_8_rx_axis_tkeep(qsfpddb_mac_8_rx_axis_tkeep_int), - .mac_8_rx_axis_tvalid(qsfpddb_mac_8_rx_axis_tvalid_int), - .mac_8_rx_axis_tlast(qsfpddb_mac_8_rx_axis_tlast_int), - .mac_8_rx_axis_tuser(qsfpddb_mac_8_rx_axis_tuser_int), - - .mac_8_rx_status(qsfpddb_mac_8_rx_status_int), - .mac_8_rx_lfc_req(qsfpddb_mac_8_rx_lfc_req_int), - .mac_8_rx_pfc_req(qsfpddb_mac_8_rx_pfc_req_int) -); - -wire ptp_clk; -wire ptp_rst; -wire ptp_sample_clk; - -assign ptp_sample_clk = clk_100mhz; - -assign ptp_clk = qsfpdda_mac_1_tx_clk_int; -assign ptp_rst = qsfpdda_mac_1_tx_rst_int; - -// ref_div ref_div_inst ( -// .inclk(etile_clk_402), -// .clock_div1x(), -// .clock_div2x(ptp_clk), -// .clock_div4x() -// ); - -// sync_reset #( -// .N(4) -// ) -// ptp_rst_reset_sync_inst ( -// .clk(ptp_clk), -// .rst(rst_100mhz), -// .out(ptp_rst) -// ); - -fpga_core #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - .PORT_MASK(PORT_MASK), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(1), - .PTP_SEPARATE_RX_CLOCK(1), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH), - .SEG_HDR_WIDTH(SEG_HDR_WIDTH), - .SEG_PRFX_WIDTH(SEG_PRFX_WIDTH), - .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - /* - * Clock: 250 MHz - * Synchronous reset - */ - .clk_250mhz(pcie_clk), - .rst_250mhz(pcie_rst), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - - /* - * GPIO - */ - .button(button), - .sw(sw), - .led(led), - .led_bracket(led_bracket), - - /* - * P-Tile interface - */ - .rx_st_data(rx_st_data), - .rx_st_empty(rx_st_empty), - .rx_st_sop(rx_st_sop), - .rx_st_eop(rx_st_eop), - .rx_st_valid(rx_st_valid), - .rx_st_ready(rx_st_ready), - .rx_st_hdr(rx_st_hdr), - .rx_st_tlp_prfx(rx_st_tlp_prfx), - .rx_st_vf_active(rx_st_vf_active), - .rx_st_func_num(rx_st_func_num), - .rx_st_vf_num(rx_st_vf_num), - .rx_st_bar_range(rx_st_bar_range), - .rx_st_tlp_abort(rx_st_tlp_abort), - - .tx_st_data(tx_st_data), - .tx_st_sop(tx_st_sop), - .tx_st_eop(tx_st_eop), - .tx_st_valid(tx_st_valid), - .tx_st_ready(tx_st_ready), - .tx_st_err(tx_st_err), - .tx_st_hdr(tx_st_hdr), - .tx_st_tlp_prfx(tx_st_tlp_prfx), - - .rx_buffer_limit(rx_buffer_limit), - .rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx), - - .tx_cdts_limit(tx_cdts_limit), - .tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx), - - .tl_cfg_ctl(tl_cfg_ctl), - .tl_cfg_add(tl_cfg_add), - .tl_cfg_func(tl_cfg_func), - - /* - * Ethernet: QSFP-DD - */ - .qsfpdda_mac_1_tx_clk(qsfpdda_mac_1_tx_clk_int), - .qsfpdda_mac_1_tx_rst(qsfpdda_mac_1_tx_rst_int), - - .qsfpdda_mac_1_tx_ptp_clk(qsfpdda_mac_1_tx_ptp_clk_int), - .qsfpdda_mac_1_tx_ptp_rst(qsfpdda_mac_1_tx_ptp_rst_int), - .qsfpdda_mac_1_tx_ptp_time(qsfpdda_mac_1_tx_ptp_time_int), - - .qsfpdda_mac_1_tx_ptp_ts(qsfpdda_mac_1_tx_ptp_ts_int), - .qsfpdda_mac_1_tx_ptp_ts_tag(qsfpdda_mac_1_tx_ptp_ts_tag_int), - .qsfpdda_mac_1_tx_ptp_ts_valid(qsfpdda_mac_1_tx_ptp_ts_valid_int), - - .qsfpdda_mac_1_tx_axis_tdata(qsfpdda_mac_1_tx_axis_tdata_int), - .qsfpdda_mac_1_tx_axis_tkeep(qsfpdda_mac_1_tx_axis_tkeep_int), - .qsfpdda_mac_1_tx_axis_tvalid(qsfpdda_mac_1_tx_axis_tvalid_int), - .qsfpdda_mac_1_tx_axis_tready(qsfpdda_mac_1_tx_axis_tready_int), - .qsfpdda_mac_1_tx_axis_tlast(qsfpdda_mac_1_tx_axis_tlast_int), - .qsfpdda_mac_1_tx_axis_tuser(qsfpdda_mac_1_tx_axis_tuser_int), - - .qsfpdda_mac_1_tx_status(qsfpdda_mac_1_tx_status_int), - .qsfpdda_mac_1_tx_lfc_req(qsfpdda_mac_1_tx_lfc_req_int), - .qsfpdda_mac_1_tx_pfc_req(qsfpdda_mac_1_tx_pfc_req_int), - - .qsfpdda_mac_1_rx_clk(qsfpdda_mac_1_rx_clk_int), - .qsfpdda_mac_1_rx_rst(qsfpdda_mac_1_rx_rst_int), - - .qsfpdda_mac_1_rx_ptp_clk(qsfpdda_mac_1_rx_ptp_clk_int), - .qsfpdda_mac_1_rx_ptp_rst(qsfpdda_mac_1_rx_ptp_rst_int), - .qsfpdda_mac_1_rx_ptp_time(qsfpdda_mac_1_rx_ptp_time_int), - - .qsfpdda_mac_1_rx_axis_tdata(qsfpdda_mac_1_rx_axis_tdata_int), - .qsfpdda_mac_1_rx_axis_tkeep(qsfpdda_mac_1_rx_axis_tkeep_int), - .qsfpdda_mac_1_rx_axis_tvalid(qsfpdda_mac_1_rx_axis_tvalid_int), - .qsfpdda_mac_1_rx_axis_tlast(qsfpdda_mac_1_rx_axis_tlast_int), - .qsfpdda_mac_1_rx_axis_tuser(qsfpdda_mac_1_rx_axis_tuser_int), - - .qsfpdda_mac_1_rx_status(qsfpdda_mac_1_rx_status_int), - .qsfpdda_mac_1_rx_lfc_req(qsfpdda_mac_1_rx_lfc_req_int), - .qsfpdda_mac_1_rx_pfc_req(qsfpdda_mac_1_rx_pfc_req_int), - - .qsfpdda_mac_2_tx_clk(qsfpdda_mac_2_tx_clk_int), - .qsfpdda_mac_2_tx_rst(qsfpdda_mac_2_tx_rst_int), - - .qsfpdda_mac_2_tx_ptp_clk(qsfpdda_mac_2_tx_ptp_clk_int), - .qsfpdda_mac_2_tx_ptp_rst(qsfpdda_mac_2_tx_ptp_rst_int), - .qsfpdda_mac_2_tx_ptp_time(qsfpdda_mac_2_tx_ptp_time_int), - - .qsfpdda_mac_2_tx_ptp_ts(qsfpdda_mac_2_tx_ptp_ts_int), - .qsfpdda_mac_2_tx_ptp_ts_tag(qsfpdda_mac_2_tx_ptp_ts_tag_int), - .qsfpdda_mac_2_tx_ptp_ts_valid(qsfpdda_mac_2_tx_ptp_ts_valid_int), - - .qsfpdda_mac_2_tx_axis_tdata(qsfpdda_mac_2_tx_axis_tdata_int), - .qsfpdda_mac_2_tx_axis_tkeep(qsfpdda_mac_2_tx_axis_tkeep_int), - .qsfpdda_mac_2_tx_axis_tvalid(qsfpdda_mac_2_tx_axis_tvalid_int), - .qsfpdda_mac_2_tx_axis_tready(qsfpdda_mac_2_tx_axis_tready_int), - .qsfpdda_mac_2_tx_axis_tlast(qsfpdda_mac_2_tx_axis_tlast_int), - .qsfpdda_mac_2_tx_axis_tuser(qsfpdda_mac_2_tx_axis_tuser_int), - - .qsfpdda_mac_2_tx_status(qsfpdda_mac_2_tx_status_int), - .qsfpdda_mac_2_tx_lfc_req(qsfpdda_mac_2_tx_lfc_req_int), - .qsfpdda_mac_2_tx_pfc_req(qsfpdda_mac_2_tx_pfc_req_int), - - .qsfpdda_mac_2_rx_clk(qsfpdda_mac_2_rx_clk_int), - .qsfpdda_mac_2_rx_rst(qsfpdda_mac_2_rx_rst_int), - - .qsfpdda_mac_2_rx_ptp_clk(qsfpdda_mac_2_rx_ptp_clk_int), - .qsfpdda_mac_2_rx_ptp_rst(qsfpdda_mac_2_rx_ptp_rst_int), - .qsfpdda_mac_2_rx_ptp_time(qsfpdda_mac_2_rx_ptp_time_int), - - .qsfpdda_mac_2_rx_axis_tdata(qsfpdda_mac_2_rx_axis_tdata_int), - .qsfpdda_mac_2_rx_axis_tkeep(qsfpdda_mac_2_rx_axis_tkeep_int), - .qsfpdda_mac_2_rx_axis_tvalid(qsfpdda_mac_2_rx_axis_tvalid_int), - .qsfpdda_mac_2_rx_axis_tlast(qsfpdda_mac_2_rx_axis_tlast_int), - .qsfpdda_mac_2_rx_axis_tuser(qsfpdda_mac_2_rx_axis_tuser_int), - - .qsfpdda_mac_2_rx_status(qsfpdda_mac_2_rx_status_int), - .qsfpdda_mac_2_rx_lfc_req(qsfpdda_mac_2_rx_lfc_req_int), - .qsfpdda_mac_2_rx_pfc_req(qsfpdda_mac_2_rx_pfc_req_int), - - .qsfpdda_mac_3_tx_clk(qsfpdda_mac_3_tx_clk_int), - .qsfpdda_mac_3_tx_rst(qsfpdda_mac_3_tx_rst_int), - - .qsfpdda_mac_3_tx_ptp_clk(qsfpdda_mac_3_tx_ptp_clk_int), - .qsfpdda_mac_3_tx_ptp_rst(qsfpdda_mac_3_tx_ptp_rst_int), - .qsfpdda_mac_3_tx_ptp_time(qsfpdda_mac_3_tx_ptp_time_int), - - .qsfpdda_mac_3_tx_ptp_ts(qsfpdda_mac_3_tx_ptp_ts_int), - .qsfpdda_mac_3_tx_ptp_ts_tag(qsfpdda_mac_3_tx_ptp_ts_tag_int), - .qsfpdda_mac_3_tx_ptp_ts_valid(qsfpdda_mac_3_tx_ptp_ts_valid_int), - - .qsfpdda_mac_3_tx_axis_tdata(qsfpdda_mac_3_tx_axis_tdata_int), - .qsfpdda_mac_3_tx_axis_tkeep(qsfpdda_mac_3_tx_axis_tkeep_int), - .qsfpdda_mac_3_tx_axis_tvalid(qsfpdda_mac_3_tx_axis_tvalid_int), - .qsfpdda_mac_3_tx_axis_tready(qsfpdda_mac_3_tx_axis_tready_int), - .qsfpdda_mac_3_tx_axis_tlast(qsfpdda_mac_3_tx_axis_tlast_int), - .qsfpdda_mac_3_tx_axis_tuser(qsfpdda_mac_3_tx_axis_tuser_int), - - .qsfpdda_mac_3_tx_status(qsfpdda_mac_3_tx_status_int), - .qsfpdda_mac_3_tx_lfc_req(qsfpdda_mac_3_tx_lfc_req_int), - .qsfpdda_mac_3_tx_pfc_req(qsfpdda_mac_3_tx_pfc_req_int), - - .qsfpdda_mac_3_rx_clk(qsfpdda_mac_3_rx_clk_int), - .qsfpdda_mac_3_rx_rst(qsfpdda_mac_3_rx_rst_int), - - .qsfpdda_mac_3_rx_ptp_clk(qsfpdda_mac_3_rx_ptp_clk_int), - .qsfpdda_mac_3_rx_ptp_rst(qsfpdda_mac_3_rx_ptp_rst_int), - .qsfpdda_mac_3_rx_ptp_time(qsfpdda_mac_3_rx_ptp_time_int), - - .qsfpdda_mac_3_rx_axis_tdata(qsfpdda_mac_3_rx_axis_tdata_int), - .qsfpdda_mac_3_rx_axis_tkeep(qsfpdda_mac_3_rx_axis_tkeep_int), - .qsfpdda_mac_3_rx_axis_tvalid(qsfpdda_mac_3_rx_axis_tvalid_int), - .qsfpdda_mac_3_rx_axis_tlast(qsfpdda_mac_3_rx_axis_tlast_int), - .qsfpdda_mac_3_rx_axis_tuser(qsfpdda_mac_3_rx_axis_tuser_int), - - .qsfpdda_mac_3_rx_status(qsfpdda_mac_3_rx_status_int), - .qsfpdda_mac_3_rx_lfc_req(qsfpdda_mac_3_rx_lfc_req_int), - .qsfpdda_mac_3_rx_pfc_req(qsfpdda_mac_3_rx_pfc_req_int), - - .qsfpdda_mac_4_tx_clk(qsfpdda_mac_4_tx_clk_int), - .qsfpdda_mac_4_tx_rst(qsfpdda_mac_4_tx_rst_int), - - .qsfpdda_mac_4_tx_ptp_clk(qsfpdda_mac_4_tx_ptp_clk_int), - .qsfpdda_mac_4_tx_ptp_rst(qsfpdda_mac_4_tx_ptp_rst_int), - .qsfpdda_mac_4_tx_ptp_time(qsfpdda_mac_4_tx_ptp_time_int), - - .qsfpdda_mac_4_tx_ptp_ts(qsfpdda_mac_4_tx_ptp_ts_int), - .qsfpdda_mac_4_tx_ptp_ts_tag(qsfpdda_mac_4_tx_ptp_ts_tag_int), - .qsfpdda_mac_4_tx_ptp_ts_valid(qsfpdda_mac_4_tx_ptp_ts_valid_int), - - .qsfpdda_mac_4_tx_axis_tdata(qsfpdda_mac_4_tx_axis_tdata_int), - .qsfpdda_mac_4_tx_axis_tkeep(qsfpdda_mac_4_tx_axis_tkeep_int), - .qsfpdda_mac_4_tx_axis_tvalid(qsfpdda_mac_4_tx_axis_tvalid_int), - .qsfpdda_mac_4_tx_axis_tready(qsfpdda_mac_4_tx_axis_tready_int), - .qsfpdda_mac_4_tx_axis_tlast(qsfpdda_mac_4_tx_axis_tlast_int), - .qsfpdda_mac_4_tx_axis_tuser(qsfpdda_mac_4_tx_axis_tuser_int), - - .qsfpdda_mac_4_tx_status(qsfpdda_mac_4_tx_status_int), - .qsfpdda_mac_4_tx_lfc_req(qsfpdda_mac_4_tx_lfc_req_int), - .qsfpdda_mac_4_tx_pfc_req(qsfpdda_mac_4_tx_pfc_req_int), - - .qsfpdda_mac_4_rx_clk(qsfpdda_mac_4_rx_clk_int), - .qsfpdda_mac_4_rx_rst(qsfpdda_mac_4_rx_rst_int), - - .qsfpdda_mac_4_rx_ptp_clk(qsfpdda_mac_4_rx_ptp_clk_int), - .qsfpdda_mac_4_rx_ptp_rst(qsfpdda_mac_4_rx_ptp_rst_int), - .qsfpdda_mac_4_rx_ptp_time(qsfpdda_mac_4_rx_ptp_time_int), - - .qsfpdda_mac_4_rx_axis_tdata(qsfpdda_mac_4_rx_axis_tdata_int), - .qsfpdda_mac_4_rx_axis_tkeep(qsfpdda_mac_4_rx_axis_tkeep_int), - .qsfpdda_mac_4_rx_axis_tvalid(qsfpdda_mac_4_rx_axis_tvalid_int), - .qsfpdda_mac_4_rx_axis_tlast(qsfpdda_mac_4_rx_axis_tlast_int), - .qsfpdda_mac_4_rx_axis_tuser(qsfpdda_mac_4_rx_axis_tuser_int), - - .qsfpdda_mac_4_rx_status(qsfpdda_mac_4_rx_status_int), - .qsfpdda_mac_4_rx_lfc_req(qsfpdda_mac_4_rx_lfc_req_int), - .qsfpdda_mac_4_rx_pfc_req(qsfpdda_mac_4_rx_pfc_req_int), - - .qsfpdda_mac_5_tx_clk(qsfpdda_mac_5_tx_clk_int), - .qsfpdda_mac_5_tx_rst(qsfpdda_mac_5_tx_rst_int), - - .qsfpdda_mac_5_tx_ptp_clk(qsfpdda_mac_5_tx_ptp_clk_int), - .qsfpdda_mac_5_tx_ptp_rst(qsfpdda_mac_5_tx_ptp_rst_int), - .qsfpdda_mac_5_tx_ptp_time(qsfpdda_mac_5_tx_ptp_time_int), - - .qsfpdda_mac_5_tx_ptp_ts(qsfpdda_mac_5_tx_ptp_ts_int), - .qsfpdda_mac_5_tx_ptp_ts_tag(qsfpdda_mac_5_tx_ptp_ts_tag_int), - .qsfpdda_mac_5_tx_ptp_ts_valid(qsfpdda_mac_5_tx_ptp_ts_valid_int), - - .qsfpdda_mac_5_tx_axis_tdata(qsfpdda_mac_5_tx_axis_tdata_int), - .qsfpdda_mac_5_tx_axis_tkeep(qsfpdda_mac_5_tx_axis_tkeep_int), - .qsfpdda_mac_5_tx_axis_tvalid(qsfpdda_mac_5_tx_axis_tvalid_int), - .qsfpdda_mac_5_tx_axis_tready(qsfpdda_mac_5_tx_axis_tready_int), - .qsfpdda_mac_5_tx_axis_tlast(qsfpdda_mac_5_tx_axis_tlast_int), - .qsfpdda_mac_5_tx_axis_tuser(qsfpdda_mac_5_tx_axis_tuser_int), - - .qsfpdda_mac_5_tx_status(qsfpdda_mac_5_tx_status_int), - .qsfpdda_mac_5_tx_lfc_req(qsfpdda_mac_5_tx_lfc_req_int), - .qsfpdda_mac_5_tx_pfc_req(qsfpdda_mac_5_tx_pfc_req_int), - - .qsfpdda_mac_5_rx_clk(qsfpdda_mac_5_rx_clk_int), - .qsfpdda_mac_5_rx_rst(qsfpdda_mac_5_rx_rst_int), - - .qsfpdda_mac_5_rx_ptp_clk(qsfpdda_mac_5_rx_ptp_clk_int), - .qsfpdda_mac_5_rx_ptp_rst(qsfpdda_mac_5_rx_ptp_rst_int), - .qsfpdda_mac_5_rx_ptp_time(qsfpdda_mac_5_rx_ptp_time_int), - - .qsfpdda_mac_5_rx_axis_tdata(qsfpdda_mac_5_rx_axis_tdata_int), - .qsfpdda_mac_5_rx_axis_tkeep(qsfpdda_mac_5_rx_axis_tkeep_int), - .qsfpdda_mac_5_rx_axis_tvalid(qsfpdda_mac_5_rx_axis_tvalid_int), - .qsfpdda_mac_5_rx_axis_tlast(qsfpdda_mac_5_rx_axis_tlast_int), - .qsfpdda_mac_5_rx_axis_tuser(qsfpdda_mac_5_rx_axis_tuser_int), - - .qsfpdda_mac_5_rx_status(qsfpdda_mac_5_rx_status_int), - .qsfpdda_mac_5_rx_lfc_req(qsfpdda_mac_5_rx_lfc_req_int), - .qsfpdda_mac_5_rx_pfc_req(qsfpdda_mac_5_rx_pfc_req_int), - - .qsfpdda_mac_6_tx_clk(qsfpdda_mac_6_tx_clk_int), - .qsfpdda_mac_6_tx_rst(qsfpdda_mac_6_tx_rst_int), - - .qsfpdda_mac_6_tx_ptp_clk(qsfpdda_mac_6_tx_ptp_clk_int), - .qsfpdda_mac_6_tx_ptp_rst(qsfpdda_mac_6_tx_ptp_rst_int), - .qsfpdda_mac_6_tx_ptp_time(qsfpdda_mac_6_tx_ptp_time_int), - - .qsfpdda_mac_6_tx_ptp_ts(qsfpdda_mac_6_tx_ptp_ts_int), - .qsfpdda_mac_6_tx_ptp_ts_tag(qsfpdda_mac_6_tx_ptp_ts_tag_int), - .qsfpdda_mac_6_tx_ptp_ts_valid(qsfpdda_mac_6_tx_ptp_ts_valid_int), - - .qsfpdda_mac_6_tx_axis_tdata(qsfpdda_mac_6_tx_axis_tdata_int), - .qsfpdda_mac_6_tx_axis_tkeep(qsfpdda_mac_6_tx_axis_tkeep_int), - .qsfpdda_mac_6_tx_axis_tvalid(qsfpdda_mac_6_tx_axis_tvalid_int), - .qsfpdda_mac_6_tx_axis_tready(qsfpdda_mac_6_tx_axis_tready_int), - .qsfpdda_mac_6_tx_axis_tlast(qsfpdda_mac_6_tx_axis_tlast_int), - .qsfpdda_mac_6_tx_axis_tuser(qsfpdda_mac_6_tx_axis_tuser_int), - - .qsfpdda_mac_6_tx_status(qsfpdda_mac_6_tx_status_int), - .qsfpdda_mac_6_tx_lfc_req(qsfpdda_mac_6_tx_lfc_req_int), - .qsfpdda_mac_6_tx_pfc_req(qsfpdda_mac_6_tx_pfc_req_int), - - .qsfpdda_mac_6_rx_clk(qsfpdda_mac_6_rx_clk_int), - .qsfpdda_mac_6_rx_rst(qsfpdda_mac_6_rx_rst_int), - - .qsfpdda_mac_6_rx_ptp_clk(qsfpdda_mac_6_rx_ptp_clk_int), - .qsfpdda_mac_6_rx_ptp_rst(qsfpdda_mac_6_rx_ptp_rst_int), - .qsfpdda_mac_6_rx_ptp_time(qsfpdda_mac_6_rx_ptp_time_int), - - .qsfpdda_mac_6_rx_axis_tdata(qsfpdda_mac_6_rx_axis_tdata_int), - .qsfpdda_mac_6_rx_axis_tkeep(qsfpdda_mac_6_rx_axis_tkeep_int), - .qsfpdda_mac_6_rx_axis_tvalid(qsfpdda_mac_6_rx_axis_tvalid_int), - .qsfpdda_mac_6_rx_axis_tlast(qsfpdda_mac_6_rx_axis_tlast_int), - .qsfpdda_mac_6_rx_axis_tuser(qsfpdda_mac_6_rx_axis_tuser_int), - - .qsfpdda_mac_6_rx_status(qsfpdda_mac_6_rx_status_int), - .qsfpdda_mac_6_rx_lfc_req(qsfpdda_mac_6_rx_lfc_req_int), - .qsfpdda_mac_6_rx_pfc_req(qsfpdda_mac_6_rx_pfc_req_int), - - .qsfpdda_mac_7_tx_clk(qsfpdda_mac_7_tx_clk_int), - .qsfpdda_mac_7_tx_rst(qsfpdda_mac_7_tx_rst_int), - - .qsfpdda_mac_7_tx_ptp_clk(qsfpdda_mac_7_tx_ptp_clk_int), - .qsfpdda_mac_7_tx_ptp_rst(qsfpdda_mac_7_tx_ptp_rst_int), - .qsfpdda_mac_7_tx_ptp_time(qsfpdda_mac_7_tx_ptp_time_int), - - .qsfpdda_mac_7_tx_ptp_ts(qsfpdda_mac_7_tx_ptp_ts_int), - .qsfpdda_mac_7_tx_ptp_ts_tag(qsfpdda_mac_7_tx_ptp_ts_tag_int), - .qsfpdda_mac_7_tx_ptp_ts_valid(qsfpdda_mac_7_tx_ptp_ts_valid_int), - - .qsfpdda_mac_7_tx_axis_tdata(qsfpdda_mac_7_tx_axis_tdata_int), - .qsfpdda_mac_7_tx_axis_tkeep(qsfpdda_mac_7_tx_axis_tkeep_int), - .qsfpdda_mac_7_tx_axis_tvalid(qsfpdda_mac_7_tx_axis_tvalid_int), - .qsfpdda_mac_7_tx_axis_tready(qsfpdda_mac_7_tx_axis_tready_int), - .qsfpdda_mac_7_tx_axis_tlast(qsfpdda_mac_7_tx_axis_tlast_int), - .qsfpdda_mac_7_tx_axis_tuser(qsfpdda_mac_7_tx_axis_tuser_int), - - .qsfpdda_mac_7_tx_status(qsfpdda_mac_7_tx_status_int), - .qsfpdda_mac_7_tx_lfc_req(qsfpdda_mac_7_tx_lfc_req_int), - .qsfpdda_mac_7_tx_pfc_req(qsfpdda_mac_7_tx_pfc_req_int), - - .qsfpdda_mac_7_rx_clk(qsfpdda_mac_7_rx_clk_int), - .qsfpdda_mac_7_rx_rst(qsfpdda_mac_7_rx_rst_int), - - .qsfpdda_mac_7_rx_ptp_clk(qsfpdda_mac_7_rx_ptp_clk_int), - .qsfpdda_mac_7_rx_ptp_rst(qsfpdda_mac_7_rx_ptp_rst_int), - .qsfpdda_mac_7_rx_ptp_time(qsfpdda_mac_7_rx_ptp_time_int), - - .qsfpdda_mac_7_rx_axis_tdata(qsfpdda_mac_7_rx_axis_tdata_int), - .qsfpdda_mac_7_rx_axis_tkeep(qsfpdda_mac_7_rx_axis_tkeep_int), - .qsfpdda_mac_7_rx_axis_tvalid(qsfpdda_mac_7_rx_axis_tvalid_int), - .qsfpdda_mac_7_rx_axis_tlast(qsfpdda_mac_7_rx_axis_tlast_int), - .qsfpdda_mac_7_rx_axis_tuser(qsfpdda_mac_7_rx_axis_tuser_int), - - .qsfpdda_mac_7_rx_status(qsfpdda_mac_7_rx_status_int), - .qsfpdda_mac_7_rx_lfc_req(qsfpdda_mac_7_rx_lfc_req_int), - .qsfpdda_mac_7_rx_pfc_req(qsfpdda_mac_7_rx_pfc_req_int), - - .qsfpdda_mac_8_tx_clk(qsfpdda_mac_8_tx_clk_int), - .qsfpdda_mac_8_tx_rst(qsfpdda_mac_8_tx_rst_int), - - .qsfpdda_mac_8_tx_ptp_clk(qsfpdda_mac_8_tx_ptp_clk_int), - .qsfpdda_mac_8_tx_ptp_rst(qsfpdda_mac_8_tx_ptp_rst_int), - .qsfpdda_mac_8_tx_ptp_time(qsfpdda_mac_8_tx_ptp_time_int), - - .qsfpdda_mac_8_tx_ptp_ts(qsfpdda_mac_8_tx_ptp_ts_int), - .qsfpdda_mac_8_tx_ptp_ts_tag(qsfpdda_mac_8_tx_ptp_ts_tag_int), - .qsfpdda_mac_8_tx_ptp_ts_valid(qsfpdda_mac_8_tx_ptp_ts_valid_int), - - .qsfpdda_mac_8_tx_axis_tdata(qsfpdda_mac_8_tx_axis_tdata_int), - .qsfpdda_mac_8_tx_axis_tkeep(qsfpdda_mac_8_tx_axis_tkeep_int), - .qsfpdda_mac_8_tx_axis_tvalid(qsfpdda_mac_8_tx_axis_tvalid_int), - .qsfpdda_mac_8_tx_axis_tready(qsfpdda_mac_8_tx_axis_tready_int), - .qsfpdda_mac_8_tx_axis_tlast(qsfpdda_mac_8_tx_axis_tlast_int), - .qsfpdda_mac_8_tx_axis_tuser(qsfpdda_mac_8_tx_axis_tuser_int), - - .qsfpdda_mac_8_tx_status(qsfpdda_mac_8_tx_status_int), - .qsfpdda_mac_8_tx_lfc_req(qsfpdda_mac_8_tx_lfc_req_int), - .qsfpdda_mac_8_tx_pfc_req(qsfpdda_mac_8_tx_pfc_req_int), - - .qsfpdda_mac_8_rx_clk(qsfpdda_mac_8_rx_clk_int), - .qsfpdda_mac_8_rx_rst(qsfpdda_mac_8_rx_rst_int), - - .qsfpdda_mac_8_rx_ptp_clk(qsfpdda_mac_8_rx_ptp_clk_int), - .qsfpdda_mac_8_rx_ptp_rst(qsfpdda_mac_8_rx_ptp_rst_int), - .qsfpdda_mac_8_rx_ptp_time(qsfpdda_mac_8_rx_ptp_time_int), - - .qsfpdda_mac_8_rx_axis_tdata(qsfpdda_mac_8_rx_axis_tdata_int), - .qsfpdda_mac_8_rx_axis_tkeep(qsfpdda_mac_8_rx_axis_tkeep_int), - .qsfpdda_mac_8_rx_axis_tvalid(qsfpdda_mac_8_rx_axis_tvalid_int), - .qsfpdda_mac_8_rx_axis_tlast(qsfpdda_mac_8_rx_axis_tlast_int), - .qsfpdda_mac_8_rx_axis_tuser(qsfpdda_mac_8_rx_axis_tuser_int), - - .qsfpdda_mac_8_rx_status(qsfpdda_mac_8_rx_status_int), - .qsfpdda_mac_8_rx_lfc_req(qsfpdda_mac_8_rx_lfc_req_int), - .qsfpdda_mac_8_rx_pfc_req(qsfpdda_mac_8_rx_pfc_req_int), - - .qsfpdda_initmode(qsfpdda_initmode), - .qsfpdda_interrupt_n(qsfpdda_interrupt_n_int), - .qsfpdda_mod_prs_n(qsfpdda_mod_prs_n_int), - .qsfpdda_mod_sel_n(qsfpdda_mod_sel_n), - .qsfpdda_rst_n(qsfpdda_rst_n), - .qsfpdda_scl_i(qsfpdda_scl_i), - .qsfpdda_scl_o(qsfpdda_scl_o), - .qsfpdda_scl_t(qsfpdda_scl_t), - .qsfpdda_sda_i(qsfpdda_sda_i), - .qsfpdda_sda_o(qsfpdda_sda_o), - .qsfpdda_sda_t(qsfpdda_sda_t), - - .qsfpddb_mac_1_tx_clk(qsfpddb_mac_1_tx_clk_int), - .qsfpddb_mac_1_tx_rst(qsfpddb_mac_1_tx_rst_int), - - .qsfpddb_mac_1_tx_ptp_clk(qsfpddb_mac_1_tx_ptp_clk_int), - .qsfpddb_mac_1_tx_ptp_rst(qsfpddb_mac_1_tx_ptp_rst_int), - .qsfpddb_mac_1_tx_ptp_time(qsfpddb_mac_1_tx_ptp_time_int), - - .qsfpddb_mac_1_tx_ptp_ts(qsfpddb_mac_1_tx_ptp_ts_int), - .qsfpddb_mac_1_tx_ptp_ts_tag(qsfpddb_mac_1_tx_ptp_ts_tag_int), - .qsfpddb_mac_1_tx_ptp_ts_valid(qsfpddb_mac_1_tx_ptp_ts_valid_int), - - .qsfpddb_mac_1_tx_axis_tdata(qsfpddb_mac_1_tx_axis_tdata_int), - .qsfpddb_mac_1_tx_axis_tkeep(qsfpddb_mac_1_tx_axis_tkeep_int), - .qsfpddb_mac_1_tx_axis_tvalid(qsfpddb_mac_1_tx_axis_tvalid_int), - .qsfpddb_mac_1_tx_axis_tready(qsfpddb_mac_1_tx_axis_tready_int), - .qsfpddb_mac_1_tx_axis_tlast(qsfpddb_mac_1_tx_axis_tlast_int), - .qsfpddb_mac_1_tx_axis_tuser(qsfpddb_mac_1_tx_axis_tuser_int), - - .qsfpddb_mac_1_tx_status(qsfpddb_mac_1_tx_status_int), - .qsfpddb_mac_1_tx_lfc_req(qsfpddb_mac_1_tx_lfc_req_int), - .qsfpddb_mac_1_tx_pfc_req(qsfpddb_mac_1_tx_pfc_req_int), - - .qsfpddb_mac_1_rx_clk(qsfpddb_mac_1_rx_clk_int), - .qsfpddb_mac_1_rx_rst(qsfpddb_mac_1_rx_rst_int), - - .qsfpddb_mac_1_rx_ptp_clk(qsfpddb_mac_1_rx_ptp_clk_int), - .qsfpddb_mac_1_rx_ptp_rst(qsfpddb_mac_1_rx_ptp_rst_int), - .qsfpddb_mac_1_rx_ptp_time(qsfpddb_mac_1_rx_ptp_time_int), - - .qsfpddb_mac_1_rx_axis_tdata(qsfpddb_mac_1_rx_axis_tdata_int), - .qsfpddb_mac_1_rx_axis_tkeep(qsfpddb_mac_1_rx_axis_tkeep_int), - .qsfpddb_mac_1_rx_axis_tvalid(qsfpddb_mac_1_rx_axis_tvalid_int), - .qsfpddb_mac_1_rx_axis_tlast(qsfpddb_mac_1_rx_axis_tlast_int), - .qsfpddb_mac_1_rx_axis_tuser(qsfpddb_mac_1_rx_axis_tuser_int), - - .qsfpddb_mac_1_rx_status(qsfpddb_mac_1_rx_status_int), - .qsfpddb_mac_1_rx_lfc_req(qsfpddb_mac_1_rx_lfc_req_int), - .qsfpddb_mac_1_rx_pfc_req(qsfpddb_mac_1_rx_pfc_req_int), - - .qsfpddb_mac_2_tx_clk(qsfpddb_mac_2_tx_clk_int), - .qsfpddb_mac_2_tx_rst(qsfpddb_mac_2_tx_rst_int), - - .qsfpddb_mac_2_tx_ptp_clk(qsfpddb_mac_2_tx_ptp_clk_int), - .qsfpddb_mac_2_tx_ptp_rst(qsfpddb_mac_2_tx_ptp_rst_int), - .qsfpddb_mac_2_tx_ptp_time(qsfpddb_mac_2_tx_ptp_time_int), - - .qsfpddb_mac_2_tx_ptp_ts(qsfpddb_mac_2_tx_ptp_ts_int), - .qsfpddb_mac_2_tx_ptp_ts_tag(qsfpddb_mac_2_tx_ptp_ts_tag_int), - .qsfpddb_mac_2_tx_ptp_ts_valid(qsfpddb_mac_2_tx_ptp_ts_valid_int), - - .qsfpddb_mac_2_tx_axis_tdata(qsfpddb_mac_2_tx_axis_tdata_int), - .qsfpddb_mac_2_tx_axis_tkeep(qsfpddb_mac_2_tx_axis_tkeep_int), - .qsfpddb_mac_2_tx_axis_tvalid(qsfpddb_mac_2_tx_axis_tvalid_int), - .qsfpddb_mac_2_tx_axis_tready(qsfpddb_mac_2_tx_axis_tready_int), - .qsfpddb_mac_2_tx_axis_tlast(qsfpddb_mac_2_tx_axis_tlast_int), - .qsfpddb_mac_2_tx_axis_tuser(qsfpddb_mac_2_tx_axis_tuser_int), - - .qsfpddb_mac_2_tx_status(qsfpddb_mac_2_tx_status_int), - .qsfpddb_mac_2_tx_lfc_req(qsfpddb_mac_2_tx_lfc_req_int), - .qsfpddb_mac_2_tx_pfc_req(qsfpddb_mac_2_tx_pfc_req_int), - - .qsfpddb_mac_2_rx_clk(qsfpddb_mac_2_rx_clk_int), - .qsfpddb_mac_2_rx_rst(qsfpddb_mac_2_rx_rst_int), - - .qsfpddb_mac_2_rx_ptp_clk(qsfpddb_mac_2_rx_ptp_clk_int), - .qsfpddb_mac_2_rx_ptp_rst(qsfpddb_mac_2_rx_ptp_rst_int), - .qsfpddb_mac_2_rx_ptp_time(qsfpddb_mac_2_rx_ptp_time_int), - - .qsfpddb_mac_2_rx_axis_tdata(qsfpddb_mac_2_rx_axis_tdata_int), - .qsfpddb_mac_2_rx_axis_tkeep(qsfpddb_mac_2_rx_axis_tkeep_int), - .qsfpddb_mac_2_rx_axis_tvalid(qsfpddb_mac_2_rx_axis_tvalid_int), - .qsfpddb_mac_2_rx_axis_tlast(qsfpddb_mac_2_rx_axis_tlast_int), - .qsfpddb_mac_2_rx_axis_tuser(qsfpddb_mac_2_rx_axis_tuser_int), - - .qsfpddb_mac_2_rx_status(qsfpddb_mac_2_rx_status_int), - .qsfpddb_mac_2_rx_lfc_req(qsfpddb_mac_2_rx_lfc_req_int), - .qsfpddb_mac_2_rx_pfc_req(qsfpddb_mac_2_rx_pfc_req_int), - - .qsfpddb_mac_3_tx_clk(qsfpddb_mac_3_tx_clk_int), - .qsfpddb_mac_3_tx_rst(qsfpddb_mac_3_tx_rst_int), - - .qsfpddb_mac_3_tx_ptp_clk(qsfpddb_mac_3_tx_ptp_clk_int), - .qsfpddb_mac_3_tx_ptp_rst(qsfpddb_mac_3_tx_ptp_rst_int), - .qsfpddb_mac_3_tx_ptp_time(qsfpddb_mac_3_tx_ptp_time_int), - - .qsfpddb_mac_3_tx_ptp_ts(qsfpddb_mac_3_tx_ptp_ts_int), - .qsfpddb_mac_3_tx_ptp_ts_tag(qsfpddb_mac_3_tx_ptp_ts_tag_int), - .qsfpddb_mac_3_tx_ptp_ts_valid(qsfpddb_mac_3_tx_ptp_ts_valid_int), - - .qsfpddb_mac_3_tx_axis_tdata(qsfpddb_mac_3_tx_axis_tdata_int), - .qsfpddb_mac_3_tx_axis_tkeep(qsfpddb_mac_3_tx_axis_tkeep_int), - .qsfpddb_mac_3_tx_axis_tvalid(qsfpddb_mac_3_tx_axis_tvalid_int), - .qsfpddb_mac_3_tx_axis_tready(qsfpddb_mac_3_tx_axis_tready_int), - .qsfpddb_mac_3_tx_axis_tlast(qsfpddb_mac_3_tx_axis_tlast_int), - .qsfpddb_mac_3_tx_axis_tuser(qsfpddb_mac_3_tx_axis_tuser_int), - - .qsfpddb_mac_3_tx_status(qsfpddb_mac_3_tx_status_int), - .qsfpddb_mac_3_tx_lfc_req(qsfpddb_mac_3_tx_lfc_req_int), - .qsfpddb_mac_3_tx_pfc_req(qsfpddb_mac_3_tx_pfc_req_int), - - .qsfpddb_mac_3_rx_clk(qsfpddb_mac_3_rx_clk_int), - .qsfpddb_mac_3_rx_rst(qsfpddb_mac_3_rx_rst_int), - - .qsfpddb_mac_3_rx_ptp_clk(qsfpddb_mac_3_rx_ptp_clk_int), - .qsfpddb_mac_3_rx_ptp_rst(qsfpddb_mac_3_rx_ptp_rst_int), - .qsfpddb_mac_3_rx_ptp_time(qsfpddb_mac_3_rx_ptp_time_int), - - .qsfpddb_mac_3_rx_axis_tdata(qsfpddb_mac_3_rx_axis_tdata_int), - .qsfpddb_mac_3_rx_axis_tkeep(qsfpddb_mac_3_rx_axis_tkeep_int), - .qsfpddb_mac_3_rx_axis_tvalid(qsfpddb_mac_3_rx_axis_tvalid_int), - .qsfpddb_mac_3_rx_axis_tlast(qsfpddb_mac_3_rx_axis_tlast_int), - .qsfpddb_mac_3_rx_axis_tuser(qsfpddb_mac_3_rx_axis_tuser_int), - - .qsfpddb_mac_3_rx_status(qsfpddb_mac_3_rx_status_int), - .qsfpddb_mac_3_rx_lfc_req(qsfpddb_mac_3_rx_lfc_req_int), - .qsfpddb_mac_3_rx_pfc_req(qsfpddb_mac_3_rx_pfc_req_int), - - .qsfpddb_mac_4_tx_clk(qsfpddb_mac_4_tx_clk_int), - .qsfpddb_mac_4_tx_rst(qsfpddb_mac_4_tx_rst_int), - - .qsfpddb_mac_4_tx_ptp_clk(qsfpddb_mac_4_tx_ptp_clk_int), - .qsfpddb_mac_4_tx_ptp_rst(qsfpddb_mac_4_tx_ptp_rst_int), - .qsfpddb_mac_4_tx_ptp_time(qsfpddb_mac_4_tx_ptp_time_int), - - .qsfpddb_mac_4_tx_ptp_ts(qsfpddb_mac_4_tx_ptp_ts_int), - .qsfpddb_mac_4_tx_ptp_ts_tag(qsfpddb_mac_4_tx_ptp_ts_tag_int), - .qsfpddb_mac_4_tx_ptp_ts_valid(qsfpddb_mac_4_tx_ptp_ts_valid_int), - - .qsfpddb_mac_4_tx_axis_tdata(qsfpddb_mac_4_tx_axis_tdata_int), - .qsfpddb_mac_4_tx_axis_tkeep(qsfpddb_mac_4_tx_axis_tkeep_int), - .qsfpddb_mac_4_tx_axis_tvalid(qsfpddb_mac_4_tx_axis_tvalid_int), - .qsfpddb_mac_4_tx_axis_tready(qsfpddb_mac_4_tx_axis_tready_int), - .qsfpddb_mac_4_tx_axis_tlast(qsfpddb_mac_4_tx_axis_tlast_int), - .qsfpddb_mac_4_tx_axis_tuser(qsfpddb_mac_4_tx_axis_tuser_int), - - .qsfpddb_mac_4_tx_status(qsfpddb_mac_4_tx_status_int), - .qsfpddb_mac_4_tx_lfc_req(qsfpddb_mac_4_tx_lfc_req_int), - .qsfpddb_mac_4_tx_pfc_req(qsfpddb_mac_4_tx_pfc_req_int), - - .qsfpddb_mac_4_rx_clk(qsfpddb_mac_4_rx_clk_int), - .qsfpddb_mac_4_rx_rst(qsfpddb_mac_4_rx_rst_int), - - .qsfpddb_mac_4_rx_ptp_clk(qsfpddb_mac_4_rx_ptp_clk_int), - .qsfpddb_mac_4_rx_ptp_rst(qsfpddb_mac_4_rx_ptp_rst_int), - .qsfpddb_mac_4_rx_ptp_time(qsfpddb_mac_4_rx_ptp_time_int), - - .qsfpddb_mac_4_rx_axis_tdata(qsfpddb_mac_4_rx_axis_tdata_int), - .qsfpddb_mac_4_rx_axis_tkeep(qsfpddb_mac_4_rx_axis_tkeep_int), - .qsfpddb_mac_4_rx_axis_tvalid(qsfpddb_mac_4_rx_axis_tvalid_int), - .qsfpddb_mac_4_rx_axis_tlast(qsfpddb_mac_4_rx_axis_tlast_int), - .qsfpddb_mac_4_rx_axis_tuser(qsfpddb_mac_4_rx_axis_tuser_int), - - .qsfpddb_mac_4_rx_status(qsfpddb_mac_4_rx_status_int), - .qsfpddb_mac_4_rx_lfc_req(qsfpddb_mac_4_rx_lfc_req_int), - .qsfpddb_mac_4_rx_pfc_req(qsfpddb_mac_4_rx_pfc_req_int), - - .qsfpddb_mac_5_tx_clk(qsfpddb_mac_5_tx_clk_int), - .qsfpddb_mac_5_tx_rst(qsfpddb_mac_5_tx_rst_int), - - .qsfpddb_mac_5_tx_ptp_clk(qsfpddb_mac_5_tx_ptp_clk_int), - .qsfpddb_mac_5_tx_ptp_rst(qsfpddb_mac_5_tx_ptp_rst_int), - .qsfpddb_mac_5_tx_ptp_time(qsfpddb_mac_5_tx_ptp_time_int), - - .qsfpddb_mac_5_tx_ptp_ts(qsfpddb_mac_5_tx_ptp_ts_int), - .qsfpddb_mac_5_tx_ptp_ts_tag(qsfpddb_mac_5_tx_ptp_ts_tag_int), - .qsfpddb_mac_5_tx_ptp_ts_valid(qsfpddb_mac_5_tx_ptp_ts_valid_int), - - .qsfpddb_mac_5_tx_axis_tdata(qsfpddb_mac_5_tx_axis_tdata_int), - .qsfpddb_mac_5_tx_axis_tkeep(qsfpddb_mac_5_tx_axis_tkeep_int), - .qsfpddb_mac_5_tx_axis_tvalid(qsfpddb_mac_5_tx_axis_tvalid_int), - .qsfpddb_mac_5_tx_axis_tready(qsfpddb_mac_5_tx_axis_tready_int), - .qsfpddb_mac_5_tx_axis_tlast(qsfpddb_mac_5_tx_axis_tlast_int), - .qsfpddb_mac_5_tx_axis_tuser(qsfpddb_mac_5_tx_axis_tuser_int), - - .qsfpddb_mac_5_tx_status(qsfpddb_mac_5_tx_status_int), - .qsfpddb_mac_5_tx_lfc_req(qsfpddb_mac_5_tx_lfc_req_int), - .qsfpddb_mac_5_tx_pfc_req(qsfpddb_mac_5_tx_pfc_req_int), - - .qsfpddb_mac_5_rx_clk(qsfpddb_mac_5_rx_clk_int), - .qsfpddb_mac_5_rx_rst(qsfpddb_mac_5_rx_rst_int), - - .qsfpddb_mac_5_rx_ptp_clk(qsfpddb_mac_5_rx_ptp_clk_int), - .qsfpddb_mac_5_rx_ptp_rst(qsfpddb_mac_5_rx_ptp_rst_int), - .qsfpddb_mac_5_rx_ptp_time(qsfpddb_mac_5_rx_ptp_time_int), - - .qsfpddb_mac_5_rx_axis_tdata(qsfpddb_mac_5_rx_axis_tdata_int), - .qsfpddb_mac_5_rx_axis_tkeep(qsfpddb_mac_5_rx_axis_tkeep_int), - .qsfpddb_mac_5_rx_axis_tvalid(qsfpddb_mac_5_rx_axis_tvalid_int), - .qsfpddb_mac_5_rx_axis_tlast(qsfpddb_mac_5_rx_axis_tlast_int), - .qsfpddb_mac_5_rx_axis_tuser(qsfpddb_mac_5_rx_axis_tuser_int), - - .qsfpddb_mac_5_rx_status(qsfpddb_mac_5_rx_status_int), - .qsfpddb_mac_5_rx_lfc_req(qsfpddb_mac_5_rx_lfc_req_int), - .qsfpddb_mac_5_rx_pfc_req(qsfpddb_mac_5_rx_pfc_req_int), - - .qsfpddb_mac_6_tx_clk(qsfpddb_mac_6_tx_clk_int), - .qsfpddb_mac_6_tx_rst(qsfpddb_mac_6_tx_rst_int), - - .qsfpddb_mac_6_tx_ptp_clk(qsfpddb_mac_6_tx_ptp_clk_int), - .qsfpddb_mac_6_tx_ptp_rst(qsfpddb_mac_6_tx_ptp_rst_int), - .qsfpddb_mac_6_tx_ptp_time(qsfpddb_mac_6_tx_ptp_time_int), - - .qsfpddb_mac_6_tx_ptp_ts(qsfpddb_mac_6_tx_ptp_ts_int), - .qsfpddb_mac_6_tx_ptp_ts_tag(qsfpddb_mac_6_tx_ptp_ts_tag_int), - .qsfpddb_mac_6_tx_ptp_ts_valid(qsfpddb_mac_6_tx_ptp_ts_valid_int), - - .qsfpddb_mac_6_tx_axis_tdata(qsfpddb_mac_6_tx_axis_tdata_int), - .qsfpddb_mac_6_tx_axis_tkeep(qsfpddb_mac_6_tx_axis_tkeep_int), - .qsfpddb_mac_6_tx_axis_tvalid(qsfpddb_mac_6_tx_axis_tvalid_int), - .qsfpddb_mac_6_tx_axis_tready(qsfpddb_mac_6_tx_axis_tready_int), - .qsfpddb_mac_6_tx_axis_tlast(qsfpddb_mac_6_tx_axis_tlast_int), - .qsfpddb_mac_6_tx_axis_tuser(qsfpddb_mac_6_tx_axis_tuser_int), - - .qsfpddb_mac_6_tx_status(qsfpddb_mac_6_tx_status_int), - .qsfpddb_mac_6_tx_lfc_req(qsfpddb_mac_6_tx_lfc_req_int), - .qsfpddb_mac_6_tx_pfc_req(qsfpddb_mac_6_tx_pfc_req_int), - - .qsfpddb_mac_6_rx_clk(qsfpddb_mac_6_rx_clk_int), - .qsfpddb_mac_6_rx_rst(qsfpddb_mac_6_rx_rst_int), - - .qsfpddb_mac_6_rx_ptp_clk(qsfpddb_mac_6_rx_ptp_clk_int), - .qsfpddb_mac_6_rx_ptp_rst(qsfpddb_mac_6_rx_ptp_rst_int), - .qsfpddb_mac_6_rx_ptp_time(qsfpddb_mac_6_rx_ptp_time_int), - - .qsfpddb_mac_6_rx_axis_tdata(qsfpddb_mac_6_rx_axis_tdata_int), - .qsfpddb_mac_6_rx_axis_tkeep(qsfpddb_mac_6_rx_axis_tkeep_int), - .qsfpddb_mac_6_rx_axis_tvalid(qsfpddb_mac_6_rx_axis_tvalid_int), - .qsfpddb_mac_6_rx_axis_tlast(qsfpddb_mac_6_rx_axis_tlast_int), - .qsfpddb_mac_6_rx_axis_tuser(qsfpddb_mac_6_rx_axis_tuser_int), - - .qsfpddb_mac_6_rx_status(qsfpddb_mac_6_rx_status_int), - .qsfpddb_mac_6_rx_lfc_req(qsfpddb_mac_6_rx_lfc_req_int), - .qsfpddb_mac_6_rx_pfc_req(qsfpddb_mac_6_rx_pfc_req_int), - - .qsfpddb_mac_7_tx_clk(qsfpddb_mac_7_tx_clk_int), - .qsfpddb_mac_7_tx_rst(qsfpddb_mac_7_tx_rst_int), - - .qsfpddb_mac_7_tx_ptp_clk(qsfpddb_mac_7_tx_ptp_clk_int), - .qsfpddb_mac_7_tx_ptp_rst(qsfpddb_mac_7_tx_ptp_rst_int), - .qsfpddb_mac_7_tx_ptp_time(qsfpddb_mac_7_tx_ptp_time_int), - - .qsfpddb_mac_7_tx_ptp_ts(qsfpddb_mac_7_tx_ptp_ts_int), - .qsfpddb_mac_7_tx_ptp_ts_tag(qsfpddb_mac_7_tx_ptp_ts_tag_int), - .qsfpddb_mac_7_tx_ptp_ts_valid(qsfpddb_mac_7_tx_ptp_ts_valid_int), - - .qsfpddb_mac_7_tx_axis_tdata(qsfpddb_mac_7_tx_axis_tdata_int), - .qsfpddb_mac_7_tx_axis_tkeep(qsfpddb_mac_7_tx_axis_tkeep_int), - .qsfpddb_mac_7_tx_axis_tvalid(qsfpddb_mac_7_tx_axis_tvalid_int), - .qsfpddb_mac_7_tx_axis_tready(qsfpddb_mac_7_tx_axis_tready_int), - .qsfpddb_mac_7_tx_axis_tlast(qsfpddb_mac_7_tx_axis_tlast_int), - .qsfpddb_mac_7_tx_axis_tuser(qsfpddb_mac_7_tx_axis_tuser_int), - - .qsfpddb_mac_7_tx_status(qsfpddb_mac_7_tx_status_int), - .qsfpddb_mac_7_tx_lfc_req(qsfpddb_mac_7_tx_lfc_req_int), - .qsfpddb_mac_7_tx_pfc_req(qsfpddb_mac_7_tx_pfc_req_int), - - .qsfpddb_mac_7_rx_clk(qsfpddb_mac_7_rx_clk_int), - .qsfpddb_mac_7_rx_rst(qsfpddb_mac_7_rx_rst_int), - - .qsfpddb_mac_7_rx_ptp_clk(qsfpddb_mac_7_rx_ptp_clk_int), - .qsfpddb_mac_7_rx_ptp_rst(qsfpddb_mac_7_rx_ptp_rst_int), - .qsfpddb_mac_7_rx_ptp_time(qsfpddb_mac_7_rx_ptp_time_int), - - .qsfpddb_mac_7_rx_axis_tdata(qsfpddb_mac_7_rx_axis_tdata_int), - .qsfpddb_mac_7_rx_axis_tkeep(qsfpddb_mac_7_rx_axis_tkeep_int), - .qsfpddb_mac_7_rx_axis_tvalid(qsfpddb_mac_7_rx_axis_tvalid_int), - .qsfpddb_mac_7_rx_axis_tlast(qsfpddb_mac_7_rx_axis_tlast_int), - .qsfpddb_mac_7_rx_axis_tuser(qsfpddb_mac_7_rx_axis_tuser_int), - - .qsfpddb_mac_7_rx_status(qsfpddb_mac_7_rx_status_int), - .qsfpddb_mac_7_rx_lfc_req(qsfpddb_mac_7_rx_lfc_req_int), - .qsfpddb_mac_7_rx_pfc_req(qsfpddb_mac_7_rx_pfc_req_int), - - .qsfpddb_mac_8_tx_clk(qsfpddb_mac_8_tx_clk_int), - .qsfpddb_mac_8_tx_rst(qsfpddb_mac_8_tx_rst_int), - - .qsfpddb_mac_8_tx_ptp_clk(qsfpddb_mac_8_tx_ptp_clk_int), - .qsfpddb_mac_8_tx_ptp_rst(qsfpddb_mac_8_tx_ptp_rst_int), - .qsfpddb_mac_8_tx_ptp_time(qsfpddb_mac_8_tx_ptp_time_int), - - .qsfpddb_mac_8_tx_ptp_ts(qsfpddb_mac_8_tx_ptp_ts_int), - .qsfpddb_mac_8_tx_ptp_ts_tag(qsfpddb_mac_8_tx_ptp_ts_tag_int), - .qsfpddb_mac_8_tx_ptp_ts_valid(qsfpddb_mac_8_tx_ptp_ts_valid_int), - - .qsfpddb_mac_8_tx_axis_tdata(qsfpddb_mac_8_tx_axis_tdata_int), - .qsfpddb_mac_8_tx_axis_tkeep(qsfpddb_mac_8_tx_axis_tkeep_int), - .qsfpddb_mac_8_tx_axis_tvalid(qsfpddb_mac_8_tx_axis_tvalid_int), - .qsfpddb_mac_8_tx_axis_tready(qsfpddb_mac_8_tx_axis_tready_int), - .qsfpddb_mac_8_tx_axis_tlast(qsfpddb_mac_8_tx_axis_tlast_int), - .qsfpddb_mac_8_tx_axis_tuser(qsfpddb_mac_8_tx_axis_tuser_int), - - .qsfpddb_mac_8_tx_status(qsfpddb_mac_8_tx_status_int), - .qsfpddb_mac_8_tx_lfc_req(qsfpddb_mac_8_tx_lfc_req_int), - .qsfpddb_mac_8_tx_pfc_req(qsfpddb_mac_8_tx_pfc_req_int), - - .qsfpddb_mac_8_rx_clk(qsfpddb_mac_8_rx_clk_int), - .qsfpddb_mac_8_rx_rst(qsfpddb_mac_8_rx_rst_int), - - .qsfpddb_mac_8_rx_ptp_clk(qsfpddb_mac_8_rx_ptp_clk_int), - .qsfpddb_mac_8_rx_ptp_rst(qsfpddb_mac_8_rx_ptp_rst_int), - .qsfpddb_mac_8_rx_ptp_time(qsfpddb_mac_8_rx_ptp_time_int), - - .qsfpddb_mac_8_rx_axis_tdata(qsfpddb_mac_8_rx_axis_tdata_int), - .qsfpddb_mac_8_rx_axis_tkeep(qsfpddb_mac_8_rx_axis_tkeep_int), - .qsfpddb_mac_8_rx_axis_tvalid(qsfpddb_mac_8_rx_axis_tvalid_int), - .qsfpddb_mac_8_rx_axis_tlast(qsfpddb_mac_8_rx_axis_tlast_int), - .qsfpddb_mac_8_rx_axis_tuser(qsfpddb_mac_8_rx_axis_tuser_int), - - .qsfpddb_mac_8_rx_status(qsfpddb_mac_8_rx_status_int), - .qsfpddb_mac_8_rx_lfc_req(qsfpddb_mac_8_rx_lfc_req_int), - .qsfpddb_mac_8_rx_pfc_req(qsfpddb_mac_8_rx_pfc_req_int), - - .qsfpddb_initmode(qsfpddb_initmode), - .qsfpddb_interrupt_n(qsfpddb_interrupt_n_int), - .qsfpddb_mod_prs_n(qsfpddb_mod_prs_n_int), - .qsfpddb_mod_sel_n(qsfpddb_mod_sel_n), - .qsfpddb_rst_n(qsfpddb_rst_n), - .qsfpddb_scl_i(qsfpddb_scl_i), - .qsfpddb_scl_o(qsfpddb_scl_o), - .qsfpddb_scl_t(qsfpddb_scl_t), - .qsfpddb_sda_i(qsfpddb_sda_i), - .qsfpddb_sda_o(qsfpddb_sda_o), - .qsfpddb_sda_t(qsfpddb_sda_t) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v deleted file mode 100644 index 7ec84e90a..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v +++ /dev/null @@ -1,1711 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2022-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'hC341A0DD, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h1172_B00A, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd1563227611, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLK_PERIOD_NS_NUM = 2048, - parameter PTP_CLK_PERIOD_NS_DENOM = 825, - parameter PTP_TS_WIDTH = 96, - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_TX_CLOCK = 1, - parameter PTP_SEPARATE_RX_CLOCK = 1, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 1, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_TAG_WIDTH = 8, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter SEG_COUNT = 2, - parameter SEG_DATA_WIDTH = 256, - parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32), - parameter SEG_HDR_WIDTH = 128, - parameter SEG_PRFX_WIDTH = 32, - parameter TX_SEQ_NUM_WIDTH = 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 256, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_DATA_WIDTH = 64, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, - parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 0, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, - parameter AXIS_ETH_TX_TS_PIPELINE = 0, - parameter AXIS_ETH_RX_PIPELINE = 0, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * PTP clock - */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, - - /* - * GPIO - */ - input wire [1:0] button, - input wire [1:0] sw, - output wire [3:0] led, - output wire [3:0] led_bracket, - - /* - * P-Tile interface - */ - input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data, - input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty, - input wire [SEG_COUNT-1:0] rx_st_sop, - input wire [SEG_COUNT-1:0] rx_st_eop, - input wire [SEG_COUNT-1:0] rx_st_valid, - output wire rx_st_ready, - input wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr, - input wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx, - input wire [SEG_COUNT-1:0] rx_st_vf_active, - input wire [SEG_COUNT*3-1:0] rx_st_func_num, - input wire [SEG_COUNT*11-1:0] rx_st_vf_num, - input wire [SEG_COUNT*3-1:0] rx_st_bar_range, - input wire [SEG_COUNT-1:0] rx_st_tlp_abort, - - output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data, - output wire [SEG_COUNT-1:0] tx_st_sop, - output wire [SEG_COUNT-1:0] tx_st_eop, - output wire [SEG_COUNT-1:0] tx_st_valid, - input wire tx_st_ready, - output wire [SEG_COUNT-1:0] tx_st_err, - output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr, - output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx, - - output wire [11:0] rx_buffer_limit, - output wire [1:0] rx_buffer_limit_tdm_idx, - - input wire [15:0] tx_cdts_limit, - input wire [2:0] tx_cdts_limit_tdm_idx, - - input wire [15:0] tl_cfg_ctl, - input wire [4:0] tl_cfg_add, - input wire [2:0] tl_cfg_func, - - /* - * Ethernet: QSFP-DD - */ - input wire qsfpdda_mac_1_tx_clk, - input wire qsfpdda_mac_1_tx_rst, - - input wire qsfpdda_mac_1_tx_ptp_clk, - input wire qsfpdda_mac_1_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_ts_tag, - input wire qsfpdda_mac_1_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tkeep, - output wire qsfpdda_mac_1_tx_axis_tvalid, - input wire qsfpdda_mac_1_tx_axis_tready, - output wire qsfpdda_mac_1_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tuser, - - input wire qsfpdda_mac_1_tx_status, - output wire qsfpdda_mac_1_tx_lfc_req, - output wire [7:0] qsfpdda_mac_1_tx_pfc_req, - - input wire qsfpdda_mac_1_rx_clk, - input wire qsfpdda_mac_1_rx_rst, - - input wire qsfpdda_mac_1_rx_ptp_clk, - input wire qsfpdda_mac_1_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tkeep, - input wire qsfpdda_mac_1_rx_axis_tvalid, - input wire qsfpdda_mac_1_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tuser, - - input wire qsfpdda_mac_1_rx_status, - input wire qsfpdda_mac_1_rx_lfc_req, - input wire [7:0] qsfpdda_mac_1_rx_pfc_req, - - input wire qsfpdda_mac_2_tx_clk, - input wire qsfpdda_mac_2_tx_rst, - - input wire qsfpdda_mac_2_tx_ptp_clk, - input wire qsfpdda_mac_2_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_ts_tag, - input wire qsfpdda_mac_2_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tkeep, - output wire qsfpdda_mac_2_tx_axis_tvalid, - input wire qsfpdda_mac_2_tx_axis_tready, - output wire qsfpdda_mac_2_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tuser, - - input wire qsfpdda_mac_2_tx_status, - output wire qsfpdda_mac_2_tx_lfc_req, - output wire [7:0] qsfpdda_mac_2_tx_pfc_req, - - input wire qsfpdda_mac_2_rx_clk, - input wire qsfpdda_mac_2_rx_rst, - - input wire qsfpdda_mac_2_rx_ptp_clk, - input wire qsfpdda_mac_2_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tkeep, - input wire qsfpdda_mac_2_rx_axis_tvalid, - input wire qsfpdda_mac_2_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tuser, - - input wire qsfpdda_mac_2_rx_status, - input wire qsfpdda_mac_2_rx_lfc_req, - input wire [7:0] qsfpdda_mac_2_rx_pfc_req, - - input wire qsfpdda_mac_3_tx_clk, - input wire qsfpdda_mac_3_tx_rst, - - input wire qsfpdda_mac_3_tx_ptp_clk, - input wire qsfpdda_mac_3_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_3_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_3_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_3_tx_ptp_ts_tag, - input wire qsfpdda_mac_3_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_3_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_3_tx_axis_tkeep, - output wire qsfpdda_mac_3_tx_axis_tvalid, - input wire qsfpdda_mac_3_tx_axis_tready, - output wire qsfpdda_mac_3_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_3_tx_axis_tuser, - - input wire qsfpdda_mac_3_tx_status, - output wire qsfpdda_mac_3_tx_lfc_req, - output wire [7:0] qsfpdda_mac_3_tx_pfc_req, - - input wire qsfpdda_mac_3_rx_clk, - input wire qsfpdda_mac_3_rx_rst, - - input wire qsfpdda_mac_3_rx_ptp_clk, - input wire qsfpdda_mac_3_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_3_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_3_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_3_rx_axis_tkeep, - input wire qsfpdda_mac_3_rx_axis_tvalid, - input wire qsfpdda_mac_3_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_3_rx_axis_tuser, - - input wire qsfpdda_mac_3_rx_status, - input wire qsfpdda_mac_3_rx_lfc_req, - input wire [7:0] qsfpdda_mac_3_rx_pfc_req, - - input wire qsfpdda_mac_4_tx_clk, - input wire qsfpdda_mac_4_tx_rst, - - input wire qsfpdda_mac_4_tx_ptp_clk, - input wire qsfpdda_mac_4_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_4_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_4_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_4_tx_ptp_ts_tag, - input wire qsfpdda_mac_4_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_4_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_4_tx_axis_tkeep, - output wire qsfpdda_mac_4_tx_axis_tvalid, - input wire qsfpdda_mac_4_tx_axis_tready, - output wire qsfpdda_mac_4_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_4_tx_axis_tuser, - - input wire qsfpdda_mac_4_tx_status, - output wire qsfpdda_mac_4_tx_lfc_req, - output wire [7:0] qsfpdda_mac_4_tx_pfc_req, - - input wire qsfpdda_mac_4_rx_clk, - input wire qsfpdda_mac_4_rx_rst, - - input wire qsfpdda_mac_4_rx_ptp_clk, - input wire qsfpdda_mac_4_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_4_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_4_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_4_rx_axis_tkeep, - input wire qsfpdda_mac_4_rx_axis_tvalid, - input wire qsfpdda_mac_4_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_4_rx_axis_tuser, - - input wire qsfpdda_mac_4_rx_status, - input wire qsfpdda_mac_4_rx_lfc_req, - input wire [7:0] qsfpdda_mac_4_rx_pfc_req, - - input wire qsfpdda_mac_5_tx_clk, - input wire qsfpdda_mac_5_tx_rst, - - input wire qsfpdda_mac_5_tx_ptp_clk, - input wire qsfpdda_mac_5_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_5_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_5_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_5_tx_ptp_ts_tag, - input wire qsfpdda_mac_5_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_5_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_5_tx_axis_tkeep, - output wire qsfpdda_mac_5_tx_axis_tvalid, - input wire qsfpdda_mac_5_tx_axis_tready, - output wire qsfpdda_mac_5_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_5_tx_axis_tuser, - - input wire qsfpdda_mac_5_tx_status, - output wire qsfpdda_mac_5_tx_lfc_req, - output wire [7:0] qsfpdda_mac_5_tx_pfc_req, - - input wire qsfpdda_mac_5_rx_clk, - input wire qsfpdda_mac_5_rx_rst, - - input wire qsfpdda_mac_5_rx_ptp_clk, - input wire qsfpdda_mac_5_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_5_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_5_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_5_rx_axis_tkeep, - input wire qsfpdda_mac_5_rx_axis_tvalid, - input wire qsfpdda_mac_5_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_5_rx_axis_tuser, - - input wire qsfpdda_mac_5_rx_status, - input wire qsfpdda_mac_5_rx_lfc_req, - input wire [7:0] qsfpdda_mac_5_rx_pfc_req, - - input wire qsfpdda_mac_6_tx_clk, - input wire qsfpdda_mac_6_tx_rst, - - input wire qsfpdda_mac_6_tx_ptp_clk, - input wire qsfpdda_mac_6_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_6_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_6_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_6_tx_ptp_ts_tag, - input wire qsfpdda_mac_6_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_6_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_6_tx_axis_tkeep, - output wire qsfpdda_mac_6_tx_axis_tvalid, - input wire qsfpdda_mac_6_tx_axis_tready, - output wire qsfpdda_mac_6_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_6_tx_axis_tuser, - - input wire qsfpdda_mac_6_tx_status, - output wire qsfpdda_mac_6_tx_lfc_req, - output wire [7:0] qsfpdda_mac_6_tx_pfc_req, - - input wire qsfpdda_mac_6_rx_clk, - input wire qsfpdda_mac_6_rx_rst, - - input wire qsfpdda_mac_6_rx_ptp_clk, - input wire qsfpdda_mac_6_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_6_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_6_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_6_rx_axis_tkeep, - input wire qsfpdda_mac_6_rx_axis_tvalid, - input wire qsfpdda_mac_6_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_6_rx_axis_tuser, - - input wire qsfpdda_mac_6_rx_status, - input wire qsfpdda_mac_6_rx_lfc_req, - input wire [7:0] qsfpdda_mac_6_rx_pfc_req, - - input wire qsfpdda_mac_7_tx_clk, - input wire qsfpdda_mac_7_tx_rst, - - input wire qsfpdda_mac_7_tx_ptp_clk, - input wire qsfpdda_mac_7_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_7_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_7_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_7_tx_ptp_ts_tag, - input wire qsfpdda_mac_7_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_7_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_7_tx_axis_tkeep, - output wire qsfpdda_mac_7_tx_axis_tvalid, - input wire qsfpdda_mac_7_tx_axis_tready, - output wire qsfpdda_mac_7_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_7_tx_axis_tuser, - - input wire qsfpdda_mac_7_tx_status, - output wire qsfpdda_mac_7_tx_lfc_req, - output wire [7:0] qsfpdda_mac_7_tx_pfc_req, - - input wire qsfpdda_mac_7_rx_clk, - input wire qsfpdda_mac_7_rx_rst, - - input wire qsfpdda_mac_7_rx_ptp_clk, - input wire qsfpdda_mac_7_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_7_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_7_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_7_rx_axis_tkeep, - input wire qsfpdda_mac_7_rx_axis_tvalid, - input wire qsfpdda_mac_7_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_7_rx_axis_tuser, - - input wire qsfpdda_mac_7_rx_status, - input wire qsfpdda_mac_7_rx_lfc_req, - input wire [7:0] qsfpdda_mac_7_rx_pfc_req, - - input wire qsfpdda_mac_8_tx_clk, - input wire qsfpdda_mac_8_tx_rst, - - input wire qsfpdda_mac_8_tx_ptp_clk, - input wire qsfpdda_mac_8_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_8_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_8_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_8_tx_ptp_ts_tag, - input wire qsfpdda_mac_8_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_8_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_8_tx_axis_tkeep, - output wire qsfpdda_mac_8_tx_axis_tvalid, - input wire qsfpdda_mac_8_tx_axis_tready, - output wire qsfpdda_mac_8_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_8_tx_axis_tuser, - - input wire qsfpdda_mac_8_tx_status, - output wire qsfpdda_mac_8_tx_lfc_req, - output wire [7:0] qsfpdda_mac_8_tx_pfc_req, - - input wire qsfpdda_mac_8_rx_clk, - input wire qsfpdda_mac_8_rx_rst, - - input wire qsfpdda_mac_8_rx_ptp_clk, - input wire qsfpdda_mac_8_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_8_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_8_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_8_rx_axis_tkeep, - input wire qsfpdda_mac_8_rx_axis_tvalid, - input wire qsfpdda_mac_8_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_8_rx_axis_tuser, - - input wire qsfpdda_mac_8_rx_status, - input wire qsfpdda_mac_8_rx_lfc_req, - input wire [7:0] qsfpdda_mac_8_rx_pfc_req, - - output wire qsfpdda_initmode, - input wire qsfpdda_interrupt_n, - input wire qsfpdda_mod_prs_n, - output wire qsfpdda_mod_sel_n, - output wire qsfpdda_rst_n, - input wire qsfpdda_scl_i, - output wire qsfpdda_scl_o, - output wire qsfpdda_scl_t, - input wire qsfpdda_sda_i, - output wire qsfpdda_sda_o, - output wire qsfpdda_sda_t, - - input wire qsfpddb_mac_1_tx_clk, - input wire qsfpddb_mac_1_tx_rst, - - input wire qsfpddb_mac_1_tx_ptp_clk, - input wire qsfpddb_mac_1_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_ts_tag, - input wire qsfpddb_mac_1_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tkeep, - output wire qsfpddb_mac_1_tx_axis_tvalid, - input wire qsfpddb_mac_1_tx_axis_tready, - output wire qsfpddb_mac_1_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tuser, - - input wire qsfpddb_mac_1_tx_status, - output wire qsfpddb_mac_1_tx_lfc_req, - output wire [7:0] qsfpddb_mac_1_tx_pfc_req, - - input wire qsfpddb_mac_1_rx_clk, - input wire qsfpddb_mac_1_rx_rst, - - input wire qsfpddb_mac_1_rx_ptp_clk, - input wire qsfpddb_mac_1_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tkeep, - input wire qsfpddb_mac_1_rx_axis_tvalid, - input wire qsfpddb_mac_1_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tuser, - - input wire qsfpddb_mac_1_rx_status, - input wire qsfpddb_mac_1_rx_lfc_req, - input wire [7:0] qsfpddb_mac_1_rx_pfc_req, - - input wire qsfpddb_mac_2_tx_clk, - input wire qsfpddb_mac_2_tx_rst, - - input wire qsfpddb_mac_2_tx_ptp_clk, - input wire qsfpddb_mac_2_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_ts_tag, - input wire qsfpddb_mac_2_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tkeep, - output wire qsfpddb_mac_2_tx_axis_tvalid, - input wire qsfpddb_mac_2_tx_axis_tready, - output wire qsfpddb_mac_2_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tuser, - - input wire qsfpddb_mac_2_tx_status, - output wire qsfpddb_mac_2_tx_lfc_req, - output wire [7:0] qsfpddb_mac_2_tx_pfc_req, - - input wire qsfpddb_mac_2_rx_clk, - input wire qsfpddb_mac_2_rx_rst, - - input wire qsfpddb_mac_2_rx_ptp_clk, - input wire qsfpddb_mac_2_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tkeep, - input wire qsfpddb_mac_2_rx_axis_tvalid, - input wire qsfpddb_mac_2_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tuser, - - input wire qsfpddb_mac_2_rx_status, - input wire qsfpddb_mac_2_rx_lfc_req, - input wire [7:0] qsfpddb_mac_2_rx_pfc_req, - - input wire qsfpddb_mac_3_tx_clk, - input wire qsfpddb_mac_3_tx_rst, - - input wire qsfpddb_mac_3_tx_ptp_clk, - input wire qsfpddb_mac_3_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_3_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_3_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_3_tx_ptp_ts_tag, - input wire qsfpddb_mac_3_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_3_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_3_tx_axis_tkeep, - output wire qsfpddb_mac_3_tx_axis_tvalid, - input wire qsfpddb_mac_3_tx_axis_tready, - output wire qsfpddb_mac_3_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_3_tx_axis_tuser, - - input wire qsfpddb_mac_3_tx_status, - output wire qsfpddb_mac_3_tx_lfc_req, - output wire [7:0] qsfpddb_mac_3_tx_pfc_req, - - input wire qsfpddb_mac_3_rx_clk, - input wire qsfpddb_mac_3_rx_rst, - - input wire qsfpddb_mac_3_rx_ptp_clk, - input wire qsfpddb_mac_3_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_3_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_3_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_3_rx_axis_tkeep, - input wire qsfpddb_mac_3_rx_axis_tvalid, - input wire qsfpddb_mac_3_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_3_rx_axis_tuser, - - input wire qsfpddb_mac_3_rx_status, - input wire qsfpddb_mac_3_rx_lfc_req, - input wire [7:0] qsfpddb_mac_3_rx_pfc_req, - - input wire qsfpddb_mac_4_tx_clk, - input wire qsfpddb_mac_4_tx_rst, - - input wire qsfpddb_mac_4_tx_ptp_clk, - input wire qsfpddb_mac_4_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_4_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_4_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_4_tx_ptp_ts_tag, - input wire qsfpddb_mac_4_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_4_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_4_tx_axis_tkeep, - output wire qsfpddb_mac_4_tx_axis_tvalid, - input wire qsfpddb_mac_4_tx_axis_tready, - output wire qsfpddb_mac_4_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_4_tx_axis_tuser, - - input wire qsfpddb_mac_4_tx_status, - output wire qsfpddb_mac_4_tx_lfc_req, - output wire [7:0] qsfpddb_mac_4_tx_pfc_req, - - input wire qsfpddb_mac_4_rx_clk, - input wire qsfpddb_mac_4_rx_rst, - - input wire qsfpddb_mac_4_rx_ptp_clk, - input wire qsfpddb_mac_4_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_4_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_4_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_4_rx_axis_tkeep, - input wire qsfpddb_mac_4_rx_axis_tvalid, - input wire qsfpddb_mac_4_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_4_rx_axis_tuser, - - input wire qsfpddb_mac_4_rx_status, - input wire qsfpddb_mac_4_rx_lfc_req, - input wire [7:0] qsfpddb_mac_4_rx_pfc_req, - - input wire qsfpddb_mac_5_tx_clk, - input wire qsfpddb_mac_5_tx_rst, - - input wire qsfpddb_mac_5_tx_ptp_clk, - input wire qsfpddb_mac_5_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_5_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_5_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_5_tx_ptp_ts_tag, - input wire qsfpddb_mac_5_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_5_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_5_tx_axis_tkeep, - output wire qsfpddb_mac_5_tx_axis_tvalid, - input wire qsfpddb_mac_5_tx_axis_tready, - output wire qsfpddb_mac_5_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_5_tx_axis_tuser, - - input wire qsfpddb_mac_5_tx_status, - output wire qsfpddb_mac_5_tx_lfc_req, - output wire [7:0] qsfpddb_mac_5_tx_pfc_req, - - input wire qsfpddb_mac_5_rx_clk, - input wire qsfpddb_mac_5_rx_rst, - - input wire qsfpddb_mac_5_rx_ptp_clk, - input wire qsfpddb_mac_5_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_5_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_5_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_5_rx_axis_tkeep, - input wire qsfpddb_mac_5_rx_axis_tvalid, - input wire qsfpddb_mac_5_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_5_rx_axis_tuser, - - input wire qsfpddb_mac_5_rx_status, - input wire qsfpddb_mac_5_rx_lfc_req, - input wire [7:0] qsfpddb_mac_5_rx_pfc_req, - - input wire qsfpddb_mac_6_tx_clk, - input wire qsfpddb_mac_6_tx_rst, - - input wire qsfpddb_mac_6_tx_ptp_clk, - input wire qsfpddb_mac_6_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_6_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_6_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_6_tx_ptp_ts_tag, - input wire qsfpddb_mac_6_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_6_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_6_tx_axis_tkeep, - output wire qsfpddb_mac_6_tx_axis_tvalid, - input wire qsfpddb_mac_6_tx_axis_tready, - output wire qsfpddb_mac_6_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_6_tx_axis_tuser, - - input wire qsfpddb_mac_6_tx_status, - output wire qsfpddb_mac_6_tx_lfc_req, - output wire [7:0] qsfpddb_mac_6_tx_pfc_req, - - input wire qsfpddb_mac_6_rx_clk, - input wire qsfpddb_mac_6_rx_rst, - - input wire qsfpddb_mac_6_rx_ptp_clk, - input wire qsfpddb_mac_6_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_6_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_6_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_6_rx_axis_tkeep, - input wire qsfpddb_mac_6_rx_axis_tvalid, - input wire qsfpddb_mac_6_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_6_rx_axis_tuser, - - input wire qsfpddb_mac_6_rx_status, - input wire qsfpddb_mac_6_rx_lfc_req, - input wire [7:0] qsfpddb_mac_6_rx_pfc_req, - - input wire qsfpddb_mac_7_tx_clk, - input wire qsfpddb_mac_7_tx_rst, - - input wire qsfpddb_mac_7_tx_ptp_clk, - input wire qsfpddb_mac_7_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_7_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_7_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_7_tx_ptp_ts_tag, - input wire qsfpddb_mac_7_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_7_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_7_tx_axis_tkeep, - output wire qsfpddb_mac_7_tx_axis_tvalid, - input wire qsfpddb_mac_7_tx_axis_tready, - output wire qsfpddb_mac_7_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_7_tx_axis_tuser, - - input wire qsfpddb_mac_7_tx_status, - output wire qsfpddb_mac_7_tx_lfc_req, - output wire [7:0] qsfpddb_mac_7_tx_pfc_req, - - input wire qsfpddb_mac_7_rx_clk, - input wire qsfpddb_mac_7_rx_rst, - - input wire qsfpddb_mac_7_rx_ptp_clk, - input wire qsfpddb_mac_7_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_7_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_7_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_7_rx_axis_tkeep, - input wire qsfpddb_mac_7_rx_axis_tvalid, - input wire qsfpddb_mac_7_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_7_rx_axis_tuser, - - input wire qsfpddb_mac_7_rx_status, - input wire qsfpddb_mac_7_rx_lfc_req, - input wire [7:0] qsfpddb_mac_7_rx_pfc_req, - - input wire qsfpddb_mac_8_tx_clk, - input wire qsfpddb_mac_8_tx_rst, - - input wire qsfpddb_mac_8_tx_ptp_clk, - input wire qsfpddb_mac_8_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_8_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_8_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_8_tx_ptp_ts_tag, - input wire qsfpddb_mac_8_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_8_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_8_tx_axis_tkeep, - output wire qsfpddb_mac_8_tx_axis_tvalid, - input wire qsfpddb_mac_8_tx_axis_tready, - output wire qsfpddb_mac_8_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_8_tx_axis_tuser, - - input wire qsfpddb_mac_8_tx_status, - output wire qsfpddb_mac_8_tx_lfc_req, - output wire [7:0] qsfpddb_mac_8_tx_pfc_req, - - input wire qsfpddb_mac_8_rx_clk, - input wire qsfpddb_mac_8_rx_rst, - - input wire qsfpddb_mac_8_rx_ptp_clk, - input wire qsfpddb_mac_8_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_8_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_8_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_8_rx_axis_tkeep, - input wire qsfpddb_mac_8_rx_axis_tvalid, - input wire qsfpddb_mac_8_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_8_rx_axis_tuser, - - input wire qsfpddb_mac_8_rx_status, - input wire qsfpddb_mac_8_rx_lfc_req, - input wire [7:0] qsfpddb_mac_8_rx_pfc_req, - - output wire qsfpddb_initmode, - input wire qsfpddb_interrupt_n, - input wire qsfpddb_mod_prs_n, - output wire qsfpddb_mod_sel_n, - output wire qsfpddb_rst_n, - input wire qsfpddb_scl_i, - output wire qsfpddb_scl_o, - output wire qsfpddb_scl_t, - input wire qsfpddb_sda_i, - output wire qsfpddb_sda_o, - output wire qsfpddb_sda_t -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -initial begin - if (PORT_COUNT > 16) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// AXI lite connections -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; -wire [2:0] axil_csr_awprot; -wire axil_csr_awvalid; -wire axil_csr_awready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; -wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; -wire axil_csr_wvalid; -wire axil_csr_wready; -wire [1:0] axil_csr_bresp; -wire axil_csr_bvalid; -wire axil_csr_bready; -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; -wire [2:0] axil_csr_arprot; -wire axil_csr_arvalid; -wire axil_csr_arready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; -wire [1:0] axil_csr_rresp; -wire axil_csr_rvalid; -wire axil_csr_rready; - -// PTP -wire ptp_td_sd; -wire ptp_pps; -wire ptp_pps_str; -wire ptp_sync_locked; -wire [63:0] ptp_sync_ts_rel; -wire ptp_sync_ts_rel_step; -wire [95:0] ptp_sync_ts_tod; -wire ptp_sync_ts_tod_step; -wire ptp_sync_pps; -wire ptp_sync_pps_str; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg qsfpdda_rst_reg = 1'b0; -reg qsfpdda_initmode_reg = 1'b0; -reg qsfpdda_scl_o_reg = 1'b1; -reg qsfpdda_sda_o_reg = 1'b1; - -reg qsfpddb_rst_reg = 1'b0; -reg qsfpddb_initmode_reg = 1'b0; -reg qsfpddb_scl_o_reg = 1'b1; -reg qsfpddb_sda_o_reg = 1'b1; - -// reg fpga_boot_reg = 1'b0; - -// reg qspi_clk_reg = 1'b0; -// reg qspi_cs_reg = 1'b1; -// reg [3:0] qspi_dq_o_reg = 4'd0; -// reg [3:0] qspi_dq_oe_reg = 4'd0; - -assign ctrl_reg_wr_wait = 1'b0; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg; -assign ctrl_reg_rd_wait = 1'b0; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg; - -assign qsfpdda_initmode = qsfpdda_initmode_reg; -assign qsfpdda_mod_sel_n = 1'b0; -assign qsfpdda_rst_n = !qsfpdda_rst_reg; -assign qsfpdda_scl_o = qsfpdda_scl_o_reg; -assign qsfpdda_scl_t = qsfpdda_scl_o_reg; -assign qsfpdda_sda_o = qsfpdda_sda_o_reg; -assign qsfpdda_sda_t = qsfpdda_sda_o_reg; - -assign qsfpddb_initmode = qsfpddb_initmode_reg; -assign qsfpddb_mod_sel_n = 1'b0; -assign qsfpddb_rst_n = !qsfpddb_rst_reg; -assign qsfpddb_scl_o = qsfpddb_scl_o_reg; -assign qsfpddb_scl_t = qsfpddb_scl_o_reg; -assign qsfpddb_sda_o = qsfpddb_sda_o_reg; -assign qsfpddb_sda_t = qsfpddb_sda_o_reg; - -// assign fpga_boot = fpga_boot_reg; - -// assign qspi_clk = qspi_clk_reg; -// assign qspi_cs = qspi_cs_reg; -// assign qspi_dq_o = qspi_dq_o_reg; -// assign qspi_dq_oe = qspi_dq_oe_reg; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h0C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - qsfpdda_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfpdda_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // I2C 1 - RBB+8'h1C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - qsfpddb_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfpddb_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // XCVR GPIO - RBB+8'h2C: begin - // XCVR GPIO: control 0123 - if (ctrl_reg_wr_strb[0]) begin - qsfpdda_initmode_reg <= ctrl_reg_wr_data[5]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfpddb_initmode_reg <= ctrl_reg_wr_data[13]; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header - RBB+8'h0C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= qsfpdda_scl_i; - ctrl_reg_rd_data_reg[1] <= qsfpdda_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= qsfpdda_sda_i; - ctrl_reg_rd_data_reg[9] <= qsfpdda_sda_o_reg; - end - // I2C 1 - RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // I2C ctrl: Next header - RBB+8'h1C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= qsfpddb_scl_i; - ctrl_reg_rd_data_reg[1] <= qsfpddb_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= qsfpddb_sda_i; - ctrl_reg_rd_data_reg[9] <= qsfpddb_sda_o_reg; - end - // XCVR GPIO - RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type - RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= 0; // XCVR GPIO: Next header - RBB+8'h2C: begin - // XCVR GPIO: control 0123 - ctrl_reg_rd_data_reg[0] <= !qsfpdda_mod_prs_n; - ctrl_reg_rd_data_reg[1] <= !qsfpdda_interrupt_n; - ctrl_reg_rd_data_reg[4] <= qsfpdda_rst_reg; - ctrl_reg_rd_data_reg[5] <= qsfpdda_initmode_reg; - ctrl_reg_rd_data_reg[8] <= !qsfpddb_mod_prs_n; - ctrl_reg_rd_data_reg[9] <= !qsfpddb_interrupt_n; - ctrl_reg_rd_data_reg[12] <= qsfpddb_rst_reg; - ctrl_reg_rd_data_reg[13] <= qsfpddb_initmode_reg; - end - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - qsfpdda_rst_reg <= 1'b0; - qsfpdda_initmode_reg <= 1'b0; - qsfpdda_scl_o_reg <= 1'b1; - qsfpdda_sda_o_reg <= 1'b1; - - qsfpddb_rst_reg <= 1'b0; - qsfpddb_initmode_reg <= 1'b0; - qsfpddb_scl_o_reg <= 1'b1; - qsfpddb_sda_o_reg <= 1'b1; - - // qspi_clk_reg <= 1'b0; - // qspi_cs_reg <= 1'b1; - // qspi_dq_o_reg <= 4'd0; - // qspi_dq_oe_reg <= 4'd0; - end -end - -assign led[0] = !qsfpdda_mac_1_rx_status; -assign led[1] = !qsfpddb_mac_1_rx_status; -assign led[2] = 1'b1; -assign led[3] = !ptp_pps_str; - -assign led_bracket[0] = !qsfpdda_mac_1_rx_status; -assign led_bracket[1] = !qsfpddb_mac_1_rx_status; -assign led_bracket[2] = 1'b1; -assign led_bracket[3] = !ptp_pps_str; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT-1:0] eth_tx_ptp_clk; -wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_tx_enable; -wire [PORT_COUNT-1:0] eth_tx_status; -wire [PORT_COUNT-1:0] eth_tx_lfc_en; -wire [PORT_COUNT-1:0] eth_tx_lfc_req; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT-1:0] eth_rx_ptp_clk; -wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] eth_rx_enable; -wire [PORT_COUNT-1:0] eth_rx_status; -wire [PORT_COUNT-1:0] eth_rx_lfc_en; -wire [PORT_COUNT-1:0] eth_rx_lfc_req; -wire [PORT_COUNT-1:0] eth_rx_lfc_ack; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; - -mqnic_port_map_mac_axis #( - .MAC_COUNT(16), - .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(8), - - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(TX_TAG_WIDTH), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) -) -mqnic_port_map_mac_axis_inst ( - // towards MAC - .mac_tx_clk({qsfpddb_mac_8_tx_clk, qsfpddb_mac_7_tx_clk, qsfpddb_mac_6_tx_clk, qsfpddb_mac_5_tx_clk, qsfpddb_mac_4_tx_clk, qsfpddb_mac_3_tx_clk, qsfpddb_mac_2_tx_clk, qsfpddb_mac_1_tx_clk, qsfpdda_mac_8_tx_clk, qsfpdda_mac_7_tx_clk, qsfpdda_mac_6_tx_clk, qsfpdda_mac_5_tx_clk, qsfpdda_mac_4_tx_clk, qsfpdda_mac_3_tx_clk, qsfpdda_mac_2_tx_clk, qsfpdda_mac_1_tx_clk}), - .mac_tx_rst({qsfpddb_mac_8_tx_rst, qsfpddb_mac_7_tx_rst, qsfpddb_mac_6_tx_rst, qsfpddb_mac_5_tx_rst, qsfpddb_mac_4_tx_rst, qsfpddb_mac_3_tx_rst, qsfpddb_mac_2_tx_rst, qsfpddb_mac_1_tx_rst, qsfpdda_mac_8_tx_rst, qsfpdda_mac_7_tx_rst, qsfpdda_mac_6_tx_rst, qsfpdda_mac_5_tx_rst, qsfpdda_mac_4_tx_rst, qsfpdda_mac_3_tx_rst, qsfpdda_mac_2_tx_rst, qsfpdda_mac_1_tx_rst}), - - .mac_tx_ptp_clk({qsfpddb_mac_8_tx_ptp_clk, qsfpddb_mac_7_tx_ptp_clk, qsfpddb_mac_6_tx_ptp_clk, qsfpddb_mac_5_tx_ptp_clk, qsfpddb_mac_4_tx_ptp_clk, qsfpddb_mac_3_tx_ptp_clk, qsfpddb_mac_2_tx_ptp_clk, qsfpddb_mac_1_tx_ptp_clk, qsfpdda_mac_8_tx_ptp_clk, qsfpdda_mac_7_tx_ptp_clk, qsfpdda_mac_6_tx_ptp_clk, qsfpdda_mac_5_tx_ptp_clk, qsfpdda_mac_4_tx_ptp_clk, qsfpdda_mac_3_tx_ptp_clk, qsfpdda_mac_2_tx_ptp_clk, qsfpdda_mac_1_tx_ptp_clk}), - .mac_tx_ptp_rst({qsfpddb_mac_8_tx_ptp_rst, qsfpddb_mac_7_tx_ptp_rst, qsfpddb_mac_6_tx_ptp_rst, qsfpddb_mac_5_tx_ptp_rst, qsfpddb_mac_4_tx_ptp_rst, qsfpddb_mac_3_tx_ptp_rst, qsfpddb_mac_2_tx_ptp_rst, qsfpddb_mac_1_tx_ptp_rst, qsfpdda_mac_8_tx_ptp_rst, qsfpdda_mac_7_tx_ptp_rst, qsfpdda_mac_6_tx_ptp_rst, qsfpdda_mac_5_tx_ptp_rst, qsfpdda_mac_4_tx_ptp_rst, qsfpdda_mac_3_tx_ptp_rst, qsfpdda_mac_2_tx_ptp_rst, qsfpdda_mac_1_tx_ptp_rst}), - .mac_tx_ptp_ts_96({qsfpddb_mac_8_tx_ptp_time, qsfpddb_mac_7_tx_ptp_time, qsfpddb_mac_6_tx_ptp_time, qsfpddb_mac_5_tx_ptp_time, qsfpddb_mac_4_tx_ptp_time, qsfpddb_mac_3_tx_ptp_time, qsfpddb_mac_2_tx_ptp_time, qsfpddb_mac_1_tx_ptp_time, qsfpdda_mac_8_tx_ptp_time, qsfpdda_mac_7_tx_ptp_time, qsfpdda_mac_6_tx_ptp_time, qsfpdda_mac_5_tx_ptp_time, qsfpdda_mac_4_tx_ptp_time, qsfpdda_mac_3_tx_ptp_time, qsfpdda_mac_2_tx_ptp_time, qsfpdda_mac_1_tx_ptp_time}), - .mac_tx_ptp_ts_step(), - - .m_axis_mac_tx_tdata({qsfpddb_mac_8_tx_axis_tdata, qsfpddb_mac_7_tx_axis_tdata, qsfpddb_mac_6_tx_axis_tdata, qsfpddb_mac_5_tx_axis_tdata, qsfpddb_mac_4_tx_axis_tdata, qsfpddb_mac_3_tx_axis_tdata, qsfpddb_mac_2_tx_axis_tdata, qsfpddb_mac_1_tx_axis_tdata, qsfpdda_mac_8_tx_axis_tdata, qsfpdda_mac_7_tx_axis_tdata, qsfpdda_mac_6_tx_axis_tdata, qsfpdda_mac_5_tx_axis_tdata, qsfpdda_mac_4_tx_axis_tdata, qsfpdda_mac_3_tx_axis_tdata, qsfpdda_mac_2_tx_axis_tdata, qsfpdda_mac_1_tx_axis_tdata}), - .m_axis_mac_tx_tkeep({qsfpddb_mac_8_tx_axis_tkeep, qsfpddb_mac_7_tx_axis_tkeep, qsfpddb_mac_6_tx_axis_tkeep, qsfpddb_mac_5_tx_axis_tkeep, qsfpddb_mac_4_tx_axis_tkeep, qsfpddb_mac_3_tx_axis_tkeep, qsfpddb_mac_2_tx_axis_tkeep, qsfpddb_mac_1_tx_axis_tkeep, qsfpdda_mac_8_tx_axis_tkeep, qsfpdda_mac_7_tx_axis_tkeep, qsfpdda_mac_6_tx_axis_tkeep, qsfpdda_mac_5_tx_axis_tkeep, qsfpdda_mac_4_tx_axis_tkeep, qsfpdda_mac_3_tx_axis_tkeep, qsfpdda_mac_2_tx_axis_tkeep, qsfpdda_mac_1_tx_axis_tkeep}), - .m_axis_mac_tx_tvalid({qsfpddb_mac_8_tx_axis_tvalid, qsfpddb_mac_7_tx_axis_tvalid, qsfpddb_mac_6_tx_axis_tvalid, qsfpddb_mac_5_tx_axis_tvalid, qsfpddb_mac_4_tx_axis_tvalid, qsfpddb_mac_3_tx_axis_tvalid, qsfpddb_mac_2_tx_axis_tvalid, qsfpddb_mac_1_tx_axis_tvalid, qsfpdda_mac_8_tx_axis_tvalid, qsfpdda_mac_7_tx_axis_tvalid, qsfpdda_mac_6_tx_axis_tvalid, qsfpdda_mac_5_tx_axis_tvalid, qsfpdda_mac_4_tx_axis_tvalid, qsfpdda_mac_3_tx_axis_tvalid, qsfpdda_mac_2_tx_axis_tvalid, qsfpdda_mac_1_tx_axis_tvalid}), - .m_axis_mac_tx_tready({qsfpddb_mac_8_tx_axis_tready, qsfpddb_mac_7_tx_axis_tready, qsfpddb_mac_6_tx_axis_tready, qsfpddb_mac_5_tx_axis_tready, qsfpddb_mac_4_tx_axis_tready, qsfpddb_mac_3_tx_axis_tready, qsfpddb_mac_2_tx_axis_tready, qsfpddb_mac_1_tx_axis_tready, qsfpdda_mac_8_tx_axis_tready, qsfpdda_mac_7_tx_axis_tready, qsfpdda_mac_6_tx_axis_tready, qsfpdda_mac_5_tx_axis_tready, qsfpdda_mac_4_tx_axis_tready, qsfpdda_mac_3_tx_axis_tready, qsfpdda_mac_2_tx_axis_tready, qsfpdda_mac_1_tx_axis_tready}), - .m_axis_mac_tx_tlast({qsfpddb_mac_8_tx_axis_tlast, qsfpddb_mac_7_tx_axis_tlast, qsfpddb_mac_6_tx_axis_tlast, qsfpddb_mac_5_tx_axis_tlast, qsfpddb_mac_4_tx_axis_tlast, qsfpddb_mac_3_tx_axis_tlast, qsfpddb_mac_2_tx_axis_tlast, qsfpddb_mac_1_tx_axis_tlast, qsfpdda_mac_8_tx_axis_tlast, qsfpdda_mac_7_tx_axis_tlast, qsfpdda_mac_6_tx_axis_tlast, qsfpdda_mac_5_tx_axis_tlast, qsfpdda_mac_4_tx_axis_tlast, qsfpdda_mac_3_tx_axis_tlast, qsfpdda_mac_2_tx_axis_tlast, qsfpdda_mac_1_tx_axis_tlast}), - .m_axis_mac_tx_tuser({qsfpddb_mac_8_tx_axis_tuser, qsfpddb_mac_7_tx_axis_tuser, qsfpddb_mac_6_tx_axis_tuser, qsfpddb_mac_5_tx_axis_tuser, qsfpddb_mac_4_tx_axis_tuser, qsfpddb_mac_3_tx_axis_tuser, qsfpddb_mac_2_tx_axis_tuser, qsfpddb_mac_1_tx_axis_tuser, qsfpdda_mac_8_tx_axis_tuser, qsfpdda_mac_7_tx_axis_tuser, qsfpdda_mac_6_tx_axis_tuser, qsfpdda_mac_5_tx_axis_tuser, qsfpdda_mac_4_tx_axis_tuser, qsfpdda_mac_3_tx_axis_tuser, qsfpdda_mac_2_tx_axis_tuser, qsfpdda_mac_1_tx_axis_tuser}), - - .s_axis_mac_tx_ptp_ts({qsfpddb_mac_8_tx_ptp_ts, qsfpddb_mac_7_tx_ptp_ts, qsfpddb_mac_6_tx_ptp_ts, qsfpddb_mac_5_tx_ptp_ts, qsfpddb_mac_4_tx_ptp_ts, qsfpddb_mac_3_tx_ptp_ts, qsfpddb_mac_2_tx_ptp_ts, qsfpddb_mac_1_tx_ptp_ts, qsfpdda_mac_8_tx_ptp_ts, qsfpdda_mac_7_tx_ptp_ts, qsfpdda_mac_6_tx_ptp_ts, qsfpdda_mac_5_tx_ptp_ts, qsfpdda_mac_4_tx_ptp_ts, qsfpdda_mac_3_tx_ptp_ts, qsfpdda_mac_2_tx_ptp_ts, qsfpdda_mac_1_tx_ptp_ts}), - .s_axis_mac_tx_ptp_ts_tag({qsfpddb_mac_8_tx_ptp_ts_tag, qsfpddb_mac_7_tx_ptp_ts_tag, qsfpddb_mac_6_tx_ptp_ts_tag, qsfpddb_mac_5_tx_ptp_ts_tag, qsfpddb_mac_4_tx_ptp_ts_tag, qsfpddb_mac_3_tx_ptp_ts_tag, qsfpddb_mac_2_tx_ptp_ts_tag, qsfpddb_mac_1_tx_ptp_ts_tag, qsfpdda_mac_8_tx_ptp_ts_tag, qsfpdda_mac_7_tx_ptp_ts_tag, qsfpdda_mac_6_tx_ptp_ts_tag, qsfpdda_mac_5_tx_ptp_ts_tag, qsfpdda_mac_4_tx_ptp_ts_tag, qsfpdda_mac_3_tx_ptp_ts_tag, qsfpdda_mac_2_tx_ptp_ts_tag, qsfpdda_mac_1_tx_ptp_ts_tag}), - .s_axis_mac_tx_ptp_ts_valid({qsfpddb_mac_8_tx_ptp_ts_valid, qsfpddb_mac_7_tx_ptp_ts_valid, qsfpddb_mac_6_tx_ptp_ts_valid, qsfpddb_mac_5_tx_ptp_ts_valid, qsfpddb_mac_4_tx_ptp_ts_valid, qsfpddb_mac_3_tx_ptp_ts_valid, qsfpddb_mac_2_tx_ptp_ts_valid, qsfpddb_mac_1_tx_ptp_ts_valid, qsfpdda_mac_8_tx_ptp_ts_valid, qsfpdda_mac_7_tx_ptp_ts_valid, qsfpdda_mac_6_tx_ptp_ts_valid, qsfpdda_mac_5_tx_ptp_ts_valid, qsfpdda_mac_4_tx_ptp_ts_valid, qsfpdda_mac_3_tx_ptp_ts_valid, qsfpdda_mac_2_tx_ptp_ts_valid, qsfpdda_mac_1_tx_ptp_ts_valid}), - .s_axis_mac_tx_ptp_ts_ready(), - - .mac_tx_enable(), - .mac_tx_status({qsfpddb_mac_8_tx_status, qsfpddb_mac_7_tx_status, qsfpddb_mac_6_tx_status, qsfpddb_mac_5_tx_status, qsfpddb_mac_4_tx_status, qsfpddb_mac_3_tx_status, qsfpddb_mac_2_tx_status, qsfpddb_mac_1_tx_status, qsfpdda_mac_8_tx_status, qsfpdda_mac_7_tx_status, qsfpdda_mac_6_tx_status, qsfpdda_mac_5_tx_status, qsfpdda_mac_4_tx_status, qsfpdda_mac_3_tx_status, qsfpdda_mac_2_tx_status, qsfpdda_mac_1_tx_status}), - .mac_tx_lfc_en(), - .mac_tx_lfc_req({qsfpddb_mac_8_tx_lfc_req, qsfpddb_mac_7_tx_lfc_req, qsfpddb_mac_6_tx_lfc_req, qsfpddb_mac_5_tx_lfc_req, qsfpddb_mac_4_tx_lfc_req, qsfpddb_mac_3_tx_lfc_req, qsfpddb_mac_2_tx_lfc_req, qsfpddb_mac_1_tx_lfc_req, qsfpdda_mac_8_tx_lfc_req, qsfpdda_mac_7_tx_lfc_req, qsfpdda_mac_6_tx_lfc_req, qsfpdda_mac_5_tx_lfc_req, qsfpdda_mac_4_tx_lfc_req, qsfpdda_mac_3_tx_lfc_req, qsfpdda_mac_2_tx_lfc_req, qsfpdda_mac_1_tx_lfc_req}), - .mac_tx_pfc_en(), - .mac_tx_pfc_req({qsfpddb_mac_8_tx_pfc_req, qsfpddb_mac_7_tx_pfc_req, qsfpddb_mac_6_tx_pfc_req, qsfpddb_mac_5_tx_pfc_req, qsfpddb_mac_4_tx_pfc_req, qsfpddb_mac_3_tx_pfc_req, qsfpddb_mac_2_tx_pfc_req, qsfpddb_mac_1_tx_pfc_req, qsfpdda_mac_8_tx_pfc_req, qsfpdda_mac_7_tx_pfc_req, qsfpdda_mac_6_tx_pfc_req, qsfpdda_mac_5_tx_pfc_req, qsfpdda_mac_4_tx_pfc_req, qsfpdda_mac_3_tx_pfc_req, qsfpdda_mac_2_tx_pfc_req, qsfpdda_mac_1_tx_pfc_req}), - - .mac_rx_clk({qsfpddb_mac_8_rx_clk, qsfpddb_mac_7_rx_clk, qsfpddb_mac_6_rx_clk, qsfpddb_mac_5_rx_clk, qsfpddb_mac_4_rx_clk, qsfpddb_mac_3_rx_clk, qsfpddb_mac_2_rx_clk, qsfpddb_mac_1_rx_clk, qsfpdda_mac_8_rx_clk, qsfpdda_mac_7_rx_clk, qsfpdda_mac_6_rx_clk, qsfpdda_mac_5_rx_clk, qsfpdda_mac_4_rx_clk, qsfpdda_mac_3_rx_clk, qsfpdda_mac_2_rx_clk, qsfpdda_mac_1_rx_clk}), - .mac_rx_rst({qsfpddb_mac_8_rx_rst, qsfpddb_mac_7_rx_rst, qsfpddb_mac_6_rx_rst, qsfpddb_mac_5_rx_rst, qsfpddb_mac_4_rx_rst, qsfpddb_mac_3_rx_rst, qsfpddb_mac_2_rx_rst, qsfpddb_mac_1_rx_rst, qsfpdda_mac_8_rx_rst, qsfpdda_mac_7_rx_rst, qsfpdda_mac_6_rx_rst, qsfpdda_mac_5_rx_rst, qsfpdda_mac_4_rx_rst, qsfpdda_mac_3_rx_rst, qsfpdda_mac_2_rx_rst, qsfpdda_mac_1_rx_rst}), - - .mac_rx_ptp_clk({qsfpddb_mac_8_rx_ptp_clk, qsfpddb_mac_7_rx_ptp_clk, qsfpddb_mac_6_rx_ptp_clk, qsfpddb_mac_5_rx_ptp_clk, qsfpddb_mac_4_rx_ptp_clk, qsfpddb_mac_3_rx_ptp_clk, qsfpddb_mac_2_rx_ptp_clk, qsfpddb_mac_1_rx_ptp_clk, qsfpdda_mac_8_rx_ptp_clk, qsfpdda_mac_7_rx_ptp_clk, qsfpdda_mac_6_rx_ptp_clk, qsfpdda_mac_5_rx_ptp_clk, qsfpdda_mac_4_rx_ptp_clk, qsfpdda_mac_3_rx_ptp_clk, qsfpdda_mac_2_rx_ptp_clk, qsfpdda_mac_1_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfpddb_mac_8_rx_ptp_rst, qsfpddb_mac_7_rx_ptp_rst, qsfpddb_mac_6_rx_ptp_rst, qsfpddb_mac_5_rx_ptp_rst, qsfpddb_mac_4_rx_ptp_rst, qsfpddb_mac_3_rx_ptp_rst, qsfpddb_mac_2_rx_ptp_rst, qsfpddb_mac_1_rx_ptp_rst, qsfpdda_mac_8_rx_ptp_rst, qsfpdda_mac_7_rx_ptp_rst, qsfpdda_mac_6_rx_ptp_rst, qsfpdda_mac_5_rx_ptp_rst, qsfpdda_mac_4_rx_ptp_rst, qsfpdda_mac_3_rx_ptp_rst, qsfpdda_mac_2_rx_ptp_rst, qsfpdda_mac_1_rx_ptp_rst}), - .mac_rx_ptp_ts_96({qsfpddb_mac_8_rx_ptp_time, qsfpddb_mac_7_rx_ptp_time, qsfpddb_mac_6_rx_ptp_time, qsfpddb_mac_5_rx_ptp_time, qsfpddb_mac_4_rx_ptp_time, qsfpddb_mac_3_rx_ptp_time, qsfpddb_mac_2_rx_ptp_time, qsfpddb_mac_1_rx_ptp_time, qsfpdda_mac_8_rx_ptp_time, qsfpdda_mac_7_rx_ptp_time, qsfpdda_mac_6_rx_ptp_time, qsfpdda_mac_5_rx_ptp_time, qsfpdda_mac_4_rx_ptp_time, qsfpdda_mac_3_rx_ptp_time, qsfpdda_mac_2_rx_ptp_time, qsfpdda_mac_1_rx_ptp_time}), - .mac_rx_ptp_ts_step(), - - .s_axis_mac_rx_tdata({qsfpddb_mac_8_rx_axis_tdata, qsfpddb_mac_7_rx_axis_tdata, qsfpddb_mac_6_rx_axis_tdata, qsfpddb_mac_5_rx_axis_tdata, qsfpddb_mac_4_rx_axis_tdata, qsfpddb_mac_3_rx_axis_tdata, qsfpddb_mac_2_rx_axis_tdata, qsfpddb_mac_1_rx_axis_tdata, qsfpdda_mac_8_rx_axis_tdata, qsfpdda_mac_7_rx_axis_tdata, qsfpdda_mac_6_rx_axis_tdata, qsfpdda_mac_5_rx_axis_tdata, qsfpdda_mac_4_rx_axis_tdata, qsfpdda_mac_3_rx_axis_tdata, qsfpdda_mac_2_rx_axis_tdata, qsfpdda_mac_1_rx_axis_tdata}), - .s_axis_mac_rx_tkeep({qsfpddb_mac_8_rx_axis_tkeep, qsfpddb_mac_7_rx_axis_tkeep, qsfpddb_mac_6_rx_axis_tkeep, qsfpddb_mac_5_rx_axis_tkeep, qsfpddb_mac_4_rx_axis_tkeep, qsfpddb_mac_3_rx_axis_tkeep, qsfpddb_mac_2_rx_axis_tkeep, qsfpddb_mac_1_rx_axis_tkeep, qsfpdda_mac_8_rx_axis_tkeep, qsfpdda_mac_7_rx_axis_tkeep, qsfpdda_mac_6_rx_axis_tkeep, qsfpdda_mac_5_rx_axis_tkeep, qsfpdda_mac_4_rx_axis_tkeep, qsfpdda_mac_3_rx_axis_tkeep, qsfpdda_mac_2_rx_axis_tkeep, qsfpdda_mac_1_rx_axis_tkeep}), - .s_axis_mac_rx_tvalid({qsfpddb_mac_8_rx_axis_tvalid, qsfpddb_mac_7_rx_axis_tvalid, qsfpddb_mac_6_rx_axis_tvalid, qsfpddb_mac_5_rx_axis_tvalid, qsfpddb_mac_4_rx_axis_tvalid, qsfpddb_mac_3_rx_axis_tvalid, qsfpddb_mac_2_rx_axis_tvalid, qsfpddb_mac_1_rx_axis_tvalid, qsfpdda_mac_8_rx_axis_tvalid, qsfpdda_mac_7_rx_axis_tvalid, qsfpdda_mac_6_rx_axis_tvalid, qsfpdda_mac_5_rx_axis_tvalid, qsfpdda_mac_4_rx_axis_tvalid, qsfpdda_mac_3_rx_axis_tvalid, qsfpdda_mac_2_rx_axis_tvalid, qsfpdda_mac_1_rx_axis_tvalid}), - .s_axis_mac_rx_tready(), - .s_axis_mac_rx_tlast({qsfpddb_mac_8_rx_axis_tlast, qsfpddb_mac_7_rx_axis_tlast, qsfpddb_mac_6_rx_axis_tlast, qsfpddb_mac_5_rx_axis_tlast, qsfpddb_mac_4_rx_axis_tlast, qsfpddb_mac_3_rx_axis_tlast, qsfpddb_mac_2_rx_axis_tlast, qsfpddb_mac_1_rx_axis_tlast, qsfpdda_mac_8_rx_axis_tlast, qsfpdda_mac_7_rx_axis_tlast, qsfpdda_mac_6_rx_axis_tlast, qsfpdda_mac_5_rx_axis_tlast, qsfpdda_mac_4_rx_axis_tlast, qsfpdda_mac_3_rx_axis_tlast, qsfpdda_mac_2_rx_axis_tlast, qsfpdda_mac_1_rx_axis_tlast}), - .s_axis_mac_rx_tuser({qsfpddb_mac_8_rx_axis_tuser, qsfpddb_mac_7_rx_axis_tuser, qsfpddb_mac_6_rx_axis_tuser, qsfpddb_mac_5_rx_axis_tuser, qsfpddb_mac_4_rx_axis_tuser, qsfpddb_mac_3_rx_axis_tuser, qsfpddb_mac_2_rx_axis_tuser, qsfpddb_mac_1_rx_axis_tuser, qsfpdda_mac_8_rx_axis_tuser, qsfpdda_mac_7_rx_axis_tuser, qsfpdda_mac_6_rx_axis_tuser, qsfpdda_mac_5_rx_axis_tuser, qsfpdda_mac_4_rx_axis_tuser, qsfpdda_mac_3_rx_axis_tuser, qsfpdda_mac_2_rx_axis_tuser, qsfpdda_mac_1_rx_axis_tuser}), - - .mac_rx_enable(), - .mac_rx_status({qsfpddb_mac_8_rx_status, qsfpddb_mac_7_rx_status, qsfpddb_mac_6_rx_status, qsfpddb_mac_5_rx_status, qsfpddb_mac_4_rx_status, qsfpddb_mac_3_rx_status, qsfpddb_mac_2_rx_status, qsfpddb_mac_1_rx_status, qsfpdda_mac_8_rx_status, qsfpdda_mac_7_rx_status, qsfpdda_mac_6_rx_status, qsfpdda_mac_5_rx_status, qsfpdda_mac_4_rx_status, qsfpdda_mac_3_rx_status, qsfpdda_mac_2_rx_status, qsfpdda_mac_1_rx_status}), - .mac_rx_lfc_en(), - .mac_rx_lfc_req({qsfpddb_mac_8_rx_lfc_req, qsfpddb_mac_7_rx_lfc_req, qsfpddb_mac_6_rx_lfc_req, qsfpddb_mac_5_rx_lfc_req, qsfpddb_mac_4_rx_lfc_req, qsfpddb_mac_3_rx_lfc_req, qsfpddb_mac_2_rx_lfc_req, qsfpddb_mac_1_rx_lfc_req, qsfpdda_mac_8_rx_lfc_req, qsfpdda_mac_7_rx_lfc_req, qsfpdda_mac_6_rx_lfc_req, qsfpdda_mac_5_rx_lfc_req, qsfpdda_mac_4_rx_lfc_req, qsfpdda_mac_3_rx_lfc_req, qsfpdda_mac_2_rx_lfc_req, qsfpdda_mac_1_rx_lfc_req}), - .mac_rx_lfc_ack(), - .mac_rx_pfc_en(), - .mac_rx_pfc_req({qsfpddb_mac_8_rx_pfc_req, qsfpddb_mac_7_rx_pfc_req, qsfpddb_mac_6_rx_pfc_req, qsfpddb_mac_5_rx_pfc_req, qsfpddb_mac_4_rx_pfc_req, qsfpddb_mac_3_rx_pfc_req, qsfpddb_mac_2_rx_pfc_req, qsfpddb_mac_1_rx_pfc_req, qsfpdda_mac_8_rx_pfc_req, qsfpdda_mac_7_rx_pfc_req, qsfpdda_mac_6_rx_pfc_req, qsfpdda_mac_5_rx_pfc_req, qsfpdda_mac_4_rx_pfc_req, qsfpdda_mac_3_rx_pfc_req, qsfpdda_mac_2_rx_pfc_req, qsfpdda_mac_1_rx_pfc_req}), - .mac_rx_pfc_ack(), - - // towards datapath - .tx_clk(eth_tx_clk), - .tx_rst(eth_tx_rst), - - .tx_ptp_clk(eth_tx_ptp_clk), - .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_tod), - .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), - - .s_axis_tx_tdata(axis_eth_tx_tdata), - .s_axis_tx_tkeep(axis_eth_tx_tkeep), - .s_axis_tx_tvalid(axis_eth_tx_tvalid), - .s_axis_tx_tready(axis_eth_tx_tready), - .s_axis_tx_tlast(axis_eth_tx_tlast), - .s_axis_tx_tuser(axis_eth_tx_tuser), - - .m_axis_tx_ptp_ts(axis_eth_tx_ptp_ts), - .m_axis_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag), - .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), - .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), - - .tx_enable(eth_tx_enable), - .tx_status(eth_tx_status), - .tx_lfc_en(eth_tx_lfc_en), - .tx_lfc_req(eth_tx_lfc_req), - .tx_pfc_en(eth_tx_pfc_en), - .tx_pfc_req(eth_tx_pfc_req), - - .rx_clk(eth_rx_clk), - .rx_rst(eth_rx_rst), - - .rx_ptp_clk(eth_rx_ptp_clk), - .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_tod), - .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), - - .m_axis_rx_tdata(axis_eth_rx_tdata), - .m_axis_rx_tkeep(axis_eth_rx_tkeep), - .m_axis_rx_tvalid(axis_eth_rx_tvalid), - .m_axis_rx_tready(axis_eth_rx_tready), - .m_axis_rx_tlast(axis_eth_rx_tlast), - .m_axis_rx_tuser(axis_eth_rx_tuser), - - .rx_enable(eth_rx_enable), - .rx_status(eth_rx_status), - .rx_lfc_en(eth_rx_lfc_en), - .rx_lfc_req(eth_rx_lfc_req), - .rx_lfc_ack(eth_rx_lfc_ack), - .rx_pfc_en(eth_rx_pfc_en), - .rx_pfc_req(eth_rx_pfc_req), - .rx_pfc_ack(eth_rx_pfc_ack) -); - -mqnic_core_pcie_ptile #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .MAC_CTRL_ENABLE(0), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_ENABLE(0), - .HBM_ENABLE(0), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH), - .SEG_HDR_WIDTH(SEG_HDR_WIDTH), - .SEG_PRFX_WIDTH(SEG_PRFX_WIDTH), - .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(0), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * P-Tile RX AVST interface - */ - .rx_st_data(rx_st_data), - .rx_st_empty(rx_st_empty), - .rx_st_sop(rx_st_sop), - .rx_st_eop(rx_st_eop), - .rx_st_valid(rx_st_valid), - .rx_st_ready(rx_st_ready), - .rx_st_hdr(rx_st_hdr), - .rx_st_tlp_prfx(rx_st_tlp_prfx), - .rx_st_vf_active(rx_st_vf_active), - .rx_st_func_num(rx_st_func_num), - .rx_st_vf_num(rx_st_vf_num), - .rx_st_bar_range(rx_st_bar_range), - .rx_st_tlp_abort(rx_st_tlp_abort), - - /* - * P-Tile TX AVST interface - */ - .tx_st_data(tx_st_data), - .tx_st_sop(tx_st_sop), - .tx_st_eop(tx_st_eop), - .tx_st_valid(tx_st_valid), - .tx_st_ready(tx_st_ready), - .tx_st_err(tx_st_err), - .tx_st_hdr(tx_st_hdr), - .tx_st_tlp_prfx(tx_st_tlp_prfx), - - /* - * P-Tile RX flow control - */ - .rx_buffer_limit(rx_buffer_limit), - .rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx), - - /* - * P-Tile TX flow control - */ - .tx_cdts_limit(tx_cdts_limit), - .tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx), - - /* - * P-Tile configuration interface - */ - .tl_cfg_ctl(tl_cfg_ctl), - .tl_cfg_add(tl_cfg_add), - .tl_cfg_func(tl_cfg_func), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(axil_csr_awaddr), - .m_axil_csr_awprot(axil_csr_awprot), - .m_axil_csr_awvalid(axil_csr_awvalid), - .m_axil_csr_awready(axil_csr_awready), - .m_axil_csr_wdata(axil_csr_wdata), - .m_axil_csr_wstrb(axil_csr_wstrb), - .m_axil_csr_wvalid(axil_csr_wvalid), - .m_axil_csr_wready(axil_csr_wready), - .m_axil_csr_bresp(axil_csr_bresp), - .m_axil_csr_bvalid(axil_csr_bvalid), - .m_axil_csr_bready(axil_csr_bready), - .m_axil_csr_araddr(axil_csr_araddr), - .m_axil_csr_arprot(axil_csr_arprot), - .m_axil_csr_arvalid(axil_csr_arvalid), - .m_axil_csr_arready(axil_csr_arready), - .m_axil_csr_rdata(axil_csr_rdata), - .m_axil_csr_rresp(axil_csr_rresp), - .m_axil_csr_rvalid(axil_csr_rvalid), - .m_axil_csr_rready(axil_csr_rready), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - .ptp_td_sd(ptp_td_sd), - .ptp_pps(ptp_pps), - .ptp_pps_str(ptp_pps_str), - .ptp_sync_locked(ptp_sync_locked), - .ptp_sync_ts_rel(ptp_sync_ts_rel), - .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), - .ptp_sync_ts_tod(ptp_sync_ts_tod), - .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), - .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_pps_str(ptp_sync_pps_str), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_clk(eth_tx_ptp_clk), - .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), - .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), - - .eth_tx_enable(eth_tx_enable), - .eth_tx_status(eth_tx_status), - .eth_tx_lfc_en(eth_tx_lfc_en), - .eth_tx_lfc_req(eth_tx_lfc_req), - .eth_tx_pfc_en(eth_tx_pfc_en), - .eth_tx_pfc_req(eth_tx_pfc_req), - .eth_tx_fc_quanta_clk_en(0), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(eth_rx_ptp_clk), - .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), - .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - .eth_rx_enable(eth_rx_enable), - .eth_rx_status(eth_rx_status), - .eth_rx_lfc_en(eth_rx_lfc_en), - .eth_rx_lfc_req(eth_rx_lfc_req), - .eth_rx_lfc_ack(eth_rx_lfc_ack), - .eth_rx_pfc_en(eth_rx_pfc_en), - .eth_rx_pfc_req(eth_rx_pfc_req), - .eth_rx_pfc_ack(eth_rx_pfc_ack), - .eth_rx_fc_quanta_clk_en(0), - - /* - * DDR - */ - .ddr_clk(0), - .ddr_rst(0), - - .m_axi_ddr_awid(), - .m_axi_ddr_awaddr(), - .m_axi_ddr_awlen(), - .m_axi_ddr_awsize(), - .m_axi_ddr_awburst(), - .m_axi_ddr_awlock(), - .m_axi_ddr_awcache(), - .m_axi_ddr_awprot(), - .m_axi_ddr_awqos(), - .m_axi_ddr_awuser(), - .m_axi_ddr_awvalid(), - .m_axi_ddr_awready(0), - .m_axi_ddr_wdata(), - .m_axi_ddr_wstrb(), - .m_axi_ddr_wlast(), - .m_axi_ddr_wuser(), - .m_axi_ddr_wvalid(), - .m_axi_ddr_wready(0), - .m_axi_ddr_bid(0), - .m_axi_ddr_bresp(0), - .m_axi_ddr_buser(0), - .m_axi_ddr_bvalid(0), - .m_axi_ddr_bready(), - .m_axi_ddr_arid(), - .m_axi_ddr_araddr(), - .m_axi_ddr_arlen(), - .m_axi_ddr_arsize(), - .m_axi_ddr_arburst(), - .m_axi_ddr_arlock(), - .m_axi_ddr_arcache(), - .m_axi_ddr_arprot(), - .m_axi_ddr_arqos(), - .m_axi_ddr_aruser(), - .m_axi_ddr_arvalid(), - .m_axi_ddr_arready(0), - .m_axi_ddr_rid(0), - .m_axi_ddr_rdata(0), - .m_axi_ddr_rresp(0), - .m_axi_ddr_rlast(0), - .m_axi_ddr_ruser(0), - .m_axi_ddr_rvalid(0), - .m_axi_ddr_rready(), - - .ddr_status(0), - - /* - * HBM - */ - .hbm_clk(0), - .hbm_rst(0), - - .m_axi_hbm_awid(), - .m_axi_hbm_awaddr(), - .m_axi_hbm_awlen(), - .m_axi_hbm_awsize(), - .m_axi_hbm_awburst(), - .m_axi_hbm_awlock(), - .m_axi_hbm_awcache(), - .m_axi_hbm_awprot(), - .m_axi_hbm_awqos(), - .m_axi_hbm_awuser(), - .m_axi_hbm_awvalid(), - .m_axi_hbm_awready(0), - .m_axi_hbm_wdata(), - .m_axi_hbm_wstrb(), - .m_axi_hbm_wlast(), - .m_axi_hbm_wuser(), - .m_axi_hbm_wvalid(), - .m_axi_hbm_wready(0), - .m_axi_hbm_bid(0), - .m_axi_hbm_bresp(0), - .m_axi_hbm_buser(0), - .m_axi_hbm_bvalid(0), - .m_axi_hbm_bready(), - .m_axi_hbm_arid(), - .m_axi_hbm_araddr(), - .m_axi_hbm_arlen(), - .m_axi_hbm_arsize(), - .m_axi_hbm_arburst(), - .m_axi_hbm_arlock(), - .m_axi_hbm_arcache(), - .m_axi_hbm_arprot(), - .m_axi_hbm_arqos(), - .m_axi_hbm_aruser(), - .m_axi_hbm_arvalid(), - .m_axi_hbm_arready(0), - .m_axi_hbm_rid(0), - .m_axi_hbm_rdata(0), - .m_axi_hbm_rresp(0), - .m_axi_hbm_rlast(0), - .m_axi_hbm_ruser(0), - .m_axi_hbm_rvalid(0), - .m_axi_hbm_rready(), - - .hbm_status(0), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/xcvr_ctrl.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/xcvr_ctrl.v deleted file mode 100644 index b1e52b02d..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/xcvr_ctrl.v +++ /dev/null @@ -1,268 +0,0 @@ -/* - -Copyright (c) 2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Transceiver control - */ -module xcvr_ctrl ( - input wire reconfig_clk, - input wire reconfig_rst, - - input wire pll_locked_in, - - output wire [18:0] xcvr_reconfig_address, - output wire xcvr_reconfig_read, - output wire xcvr_reconfig_write, - input wire [7:0] xcvr_reconfig_readdata, - output wire [7:0] xcvr_reconfig_writedata, - input wire xcvr_reconfig_waitrequest -); - -localparam [3:0] - STATE_IDLE = 4'd0, - STATE_LOAD_PMA_1 = 4'd1, - STATE_LOAD_PMA_2 = 4'd2, - STATE_INIT_ADAPT_1 = 4'd3, - STATE_INIT_ADAPT_2 = 4'd4, - STATE_INIT_ADAPT_3 = 4'd5, - STATE_INIT_ADAPT_4 = 4'd6, - STATE_CONT_ADAPT_1 = 4'd7, - STATE_CONT_ADAPT_2 = 4'd8, - STATE_CONT_ADAPT_3 = 4'd9, - STATE_CONT_ADAPT_4 = 4'd10, - STATE_DONE = 4'd11; - -reg [3:0] state_reg = STATE_IDLE, state_next; - -reg [18:0] xcvr_reconfig_address_reg = 19'd0, xcvr_reconfig_address_next; -reg xcvr_reconfig_read_reg = 1'b0, xcvr_reconfig_read_next; -reg xcvr_reconfig_write_reg = 1'b0, xcvr_reconfig_write_next; -reg [7:0] xcvr_reconfig_writedata_reg = 8'd0, xcvr_reconfig_writedata_next; - -reg [7:0] read_data_reg = 8'd0, read_data_next; -reg read_data_valid_reg = 1'b0, read_data_valid_next; - -reg [15:0] delay_count_reg = 0, delay_count_next; - -reg pll_locked_sync_1_reg = 0; -reg pll_locked_sync_2_reg = 0; -reg pll_locked_sync_3_reg = 0; - -assign xcvr_reconfig_address = xcvr_reconfig_address_reg; -assign xcvr_reconfig_read = xcvr_reconfig_read_reg; -assign xcvr_reconfig_write = xcvr_reconfig_write_reg; -assign xcvr_reconfig_writedata = xcvr_reconfig_writedata_reg; - -always @(posedge reconfig_clk) begin - pll_locked_sync_1_reg <= pll_locked_in; - pll_locked_sync_2_reg <= pll_locked_sync_1_reg; - pll_locked_sync_3_reg <= pll_locked_sync_2_reg; -end - -always @* begin - state_next = STATE_IDLE; - - xcvr_reconfig_address_next = xcvr_reconfig_address_reg; - xcvr_reconfig_read_next = 1'b0; - xcvr_reconfig_write_next = 1'b0; - xcvr_reconfig_writedata_next = xcvr_reconfig_writedata_reg; - - read_data_next = read_data_reg; - read_data_valid_next = read_data_valid_reg; - - delay_count_next = delay_count_reg; - - if (xcvr_reconfig_read_reg || xcvr_reconfig_write_reg) begin - // operation in progress - if (xcvr_reconfig_waitrequest) begin - // wait state, hold command - xcvr_reconfig_read_next = xcvr_reconfig_read_reg; - xcvr_reconfig_write_next = xcvr_reconfig_write_reg; - end else begin - // release command - xcvr_reconfig_read_next = 1'b0; - xcvr_reconfig_write_next = 1'b0; - - if (xcvr_reconfig_read_reg) begin - // latch read data - read_data_next = xcvr_reconfig_readdata; - read_data_valid_next = 1'b1; - end - end - state_next = state_reg; - end else if (delay_count_reg != 0) begin - // stall for delay - delay_count_next = delay_count_reg - 1; - state_next = state_reg; - end else begin - read_data_valid_next = 1'b0; - - case (state_reg) - STATE_IDLE: begin - // wait for PLL to lock - if (pll_locked_sync_3_reg) begin - delay_count_next = 16'hffff; - state_next = STATE_LOAD_PMA_1; - end else begin - state_next = STATE_IDLE; - end - end - STATE_LOAD_PMA_1: begin - // load PMA config - xcvr_reconfig_address_next = 19'h40143; - xcvr_reconfig_writedata_next = 8'h80; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_LOAD_PMA_2; - end - STATE_LOAD_PMA_2: begin - // check status - if (read_data_valid_reg && read_data_reg[0]) begin - // start initial adaptation - xcvr_reconfig_address_next = 19'h200; - xcvr_reconfig_writedata_next = 8'hD2; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_INIT_ADAPT_1; - end else begin - // read status - xcvr_reconfig_address_next = 19'h40144; - xcvr_reconfig_read_next = 1'b1; - state_next = STATE_LOAD_PMA_2; - end - end - STATE_INIT_ADAPT_1: begin - // start initial adaptation - xcvr_reconfig_address_next = 19'h201; - xcvr_reconfig_writedata_next = 8'h02; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_INIT_ADAPT_2; - end - STATE_INIT_ADAPT_2: begin - // start initial adaptation - xcvr_reconfig_address_next = 19'h202; - xcvr_reconfig_writedata_next = 8'h01; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_INIT_ADAPT_3; - end - STATE_INIT_ADAPT_3: begin - // start initial adaptation - xcvr_reconfig_address_next = 19'h203; - xcvr_reconfig_writedata_next = 8'h96; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_INIT_ADAPT_4; - end - STATE_INIT_ADAPT_4: begin - // check status - if (read_data_valid_reg && read_data_reg == 8'h80) begin - // start continuous adaptation - xcvr_reconfig_address_next = 19'h200; - xcvr_reconfig_writedata_next = 8'hF6; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_CONT_ADAPT_1; - end else begin - // read status - xcvr_reconfig_address_next = 19'h207; - xcvr_reconfig_read_next = 1'b1; - state_next = STATE_INIT_ADAPT_4; - end - end - STATE_CONT_ADAPT_1: begin - // start continuous adaptation - xcvr_reconfig_address_next = 19'h201; - xcvr_reconfig_writedata_next = 8'h01; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_CONT_ADAPT_2; - end - STATE_CONT_ADAPT_2: begin - // start continuous adaptation - xcvr_reconfig_address_next = 19'h202; - xcvr_reconfig_writedata_next = 8'h03; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_CONT_ADAPT_3; - end - STATE_CONT_ADAPT_3: begin - // start continuous adaptation - xcvr_reconfig_address_next = 19'h203; - xcvr_reconfig_writedata_next = 8'h96; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_CONT_ADAPT_4; - end - STATE_CONT_ADAPT_4: begin - // check status - if (read_data_valid_reg && read_data_reg == 8'h80) begin - // done - state_next = STATE_DONE; - end else begin - // read status - xcvr_reconfig_address_next = 19'h207; - xcvr_reconfig_read_next = 1'b1; - state_next = STATE_CONT_ADAPT_4; - end - end - STATE_DONE: begin - // done with operation - state_next = STATE_DONE; - end - endcase - end - - if (!pll_locked_sync_3_reg) begin - // go back to idle if PLL is unlocked - state_next = STATE_IDLE; - end -end - -always @(posedge reconfig_clk) begin - state_reg <= state_next; - - xcvr_reconfig_address_reg <= xcvr_reconfig_address_next; - xcvr_reconfig_read_reg <= xcvr_reconfig_read_next; - xcvr_reconfig_write_reg <= xcvr_reconfig_write_next; - xcvr_reconfig_writedata_reg <= xcvr_reconfig_writedata_next; - - read_data_reg <= read_data_next; - read_data_valid_reg <= read_data_valid_next; - - delay_count_reg <= delay_count_next; - - if (reconfig_rst) begin - state_reg <= STATE_IDLE; - - xcvr_reconfig_read_reg <= 1'b0; - xcvr_reconfig_write_reg <= 1'b0; - - read_data_valid_reg <= 1'b0; - - delay_count_reg <= 0; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile deleted file mode 100644 index 01b04245f..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile +++ /dev/null @@ -1,259 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_ptile.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fc_count.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v -VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_rx.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_tx.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_fc_counter.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT := 2 -export PARAM_PORTS_PER_IF := 1 -export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) -export PARAM_PORT_MASK := 0 - -# Clock configuration -export PARAM_CLK_PERIOD_NS_NUM := 4 -export PARAM_CLK_PERIOD_NS_DENOM := 1 - -# PTP configuration -export PARAM_PTP_CLK_PERIOD_NS_NUM := 2048 -export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825 -export PARAM_PTP_CLOCK_PIPELINE := 0 -export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_TX_CLOCK := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 -export PARAM_PTP_PORT_CDC_PIPELINE := 0 -export PARAM_PTP_PEROUT_ENABLE := 1 -export PARAM_PTP_PEROUT_COUNT := 1 - -# Queue manager configuration -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_CQ_OP_TABLE_SIZE := 32 -export PARAM_EQN_WIDTH := 6 -export PARAM_TX_QUEUE_INDEX_WIDTH := 13 -export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") -export PARAM_EQ_PIPELINE := 3 -export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") - -# TX and RX engine configuration -export PARAM_TX_DESC_TABLE_SIZE := 32 -export PARAM_RX_DESC_TABLE_SIZE := 32 -export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") - -# Scheduler configuration -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH := 6 - -# Interface configuration -export PARAM_PTP_TS_ENABLE := 1 -export PARAM_TX_CPL_FIFO_DEPTH := 32 -export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_HASH_ENABLE := 1 -export PARAM_RX_CHECKSUM_ENABLE := 1 -export PARAM_LFC_ENABLE := 1 -export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) -export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 -export PARAM_MAX_TX_SIZE := 9214 -export PARAM_MAX_RX_SIZE := 9214 -export PARAM_TX_RAM_SIZE := 32768 -export PARAM_RX_RAM_SIZE := 32768 - -# Application block configuration -export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) -export PARAM_APP_ENABLE := 0 -export PARAM_APP_CTRL_ENABLE := 1 -export PARAM_APP_DMA_ENABLE := 1 -export PARAM_APP_AXIS_DIRECT_ENABLE := 1 -export PARAM_APP_AXIS_SYNC_ENABLE := 1 -export PARAM_APP_AXIS_IF_ENABLE := 1 -export PARAM_APP_STAT_ENABLE := 1 - -# DMA interface configuration -export PARAM_DMA_IMM_ENABLE := 0 -export PARAM_DMA_IMM_WIDTH := 32 -export PARAM_DMA_LEN_WIDTH := 16 -export PARAM_DMA_TAG_WIDTH := 16 -export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE := 2 - -# PCIe interface configuration -export PARAM_SEG_COUNT := 2 -export PARAM_SEG_DATA_WIDTH := 256 -export PARAM_PF_COUNT := 1 -export PARAM_VF_COUNT := 0 - -# Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH := 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE := 0 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 2 -export PARAM_AXIS_ETH_TX_TS_PIPELINE := 0 -export PARAM_AXIS_ETH_RX_PIPELINE := 0 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 2 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE := 1 -export PARAM_STAT_DMA_ENABLE := 1 -export PARAM_STAT_PCIE_ENABLE := 1 -export PARAM_STAT_INC_WIDTH := 24 -export PARAM_STAT_ID_WIDTH := 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 3f394f9ae..000000000 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,764 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -import logging -import os -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus -from cocotbext.eth import EthMac -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.intel.ptile import PTilePcieDevice, PTileRxBus, PTileTxBus - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut, msix_count=32): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = PTilePcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=16, - pld_clk_frequency=250e6, - pf_count=1, - max_payload_size=512, - enable_extended_tag=True, - - pf0_msi_enable=False, - pf0_msi_count=1, - pf1_msi_enable=False, - pf1_msi_count=1, - pf2_msi_enable=False, - pf2_msi_count=1, - pf3_msi_enable=False, - pf3_msi_count=1, - pf0_msix_enable=True, - pf0_msix_table_size=msix_count-1, - pf0_msix_table_bir=0, - pf0_msix_table_offset=0x00010000, - pf0_msix_pba_bir=0, - pf0_msix_pba_offset=0x00018000, - pf1_msix_enable=False, - pf1_msix_table_size=0, - pf1_msix_table_bir=0, - pf1_msix_table_offset=0x00000000, - pf1_msix_pba_bir=0, - pf1_msix_pba_offset=0x00000000, - pf2_msix_enable=False, - pf2_msix_table_size=0, - pf2_msix_table_bir=0, - pf2_msix_table_offset=0x00000000, - pf2_msix_pba_bir=0, - pf2_msix_pba_offset=0x00000000, - pf3_msix_enable=False, - pf3_msix_table_size=0, - pf3_msix_table_bir=0, - pf3_msix_table_offset=0x00000000, - pf3_msix_pba_bir=0, - pf3_msix_pba_offset=0x00000000, - - # signals - # Clock and reset - reset_status=dut.rst_250mhz, - # reset_status_n=dut.reset_status_n, - coreclkout_hip=dut.clk_250mhz, - # refclk0=dut.refclk0, - # refclk1=dut.refclk1, - # pin_perst_n=dut.pin_perst_n, - - # RX interface - rx_bus=PTileRxBus.from_prefix(dut, "rx_st"), - # rx_par_err=dut.rx_par_err, - - # TX interface - tx_bus=PTileTxBus.from_prefix(dut, "tx_st"), - # tx_par_err=dut.tx_par_err, - - # RX flow control - rx_buffer_limit=dut.rx_buffer_limit, - rx_buffer_limit_tdm_idx=dut.rx_buffer_limit_tdm_idx, - - # TX flow control - tx_cdts_limit=dut.tx_cdts_limit, - tx_cdts_limit_tdm_idx=dut.tx_cdts_limit_tdm_idx, - - # Power management and hard IP status interface - # link_up=dut.link_up, - # dl_up=dut.dl_up, - # surprise_down_err=dut.surprise_down_err, - # ltssm_state=dut.ltssm_state, - # pm_state=dut.pm_state, - # pm_dstate=dut.pm_dstate, - # apps_pm_xmt_pme=dut.apps_pm_xmt_pme, - # app_req_retry_en=dut.app_req_retry_en, - - # Interrupt interface - # app_int=dut.app_int, - # msi_pnd_func=dut.msi_pnd_func, - # msi_pnd_byte=dut.msi_pnd_byte, - # msi_pnd_addr=dut.msi_pnd_addr, - - # Error interface - # serr_out=dut.serr_out, - # hip_enter_err_mode=dut.hip_enter_err_mode, - # app_err_valid=dut.app_err_valid, - # app_err_hdr=dut.app_err_hdr, - # app_err_info=dut.app_err_info, - # app_err_func_num=dut.app_err_func_num, - - # Completion timeout interface - # cpl_timeout=dut.cpl_timeout, - # cpl_timeout_avmm_clk=dut.cpl_timeout_avmm_clk, - # cpl_timeout_avmm_address=dut.cpl_timeout_avmm_address, - # cpl_timeout_avmm_read=dut.cpl_timeout_avmm_read, - # cpl_timeout_avmm_readdata=dut.cpl_timeout_avmm_readdata, - # cpl_timeout_avmm_readdatavalid=dut.cpl_timeout_avmm_readdatavalid, - # cpl_timeout_avmm_write=dut.cpl_timeout_avmm_write, - # cpl_timeout_avmm_writedata=dut.cpl_timeout_avmm_writedata, - # cpl_timeout_avmm_waitrequest=dut.cpl_timeout_avmm_waitrequest, - - # Configuration output - tl_cfg_func=dut.tl_cfg_func, - tl_cfg_add=dut.tl_cfg_add, - tl_cfg_ctl=dut.tl_cfg_ctl, - # dl_timer_update=dut.dl_timer_update, - - # Configuration intercept interface - # cii_req=dut.cii_req, - # cii_hdr_poisoned=dut.cii_hdr_poisoned, - # cii_hdr_first_be=dut.cii_hdr_first_be, - # cii_func_num=dut.cii_func_num, - # cii_wr_vf_active=dut.cii_wr_vf_active, - # cii_vf_num=dut.cii_vf_num, - # cii_wr=dut.cii_wr, - # cii_addr=dut.cii_addr, - # cii_dout=dut.cii_dout, - # cii_override_en=dut.cii_override_en, - # cii_override_din=dut.cii_override_din, - # cii_halt=dut.cii_halt, - - # Hard IP reconfiguration interface - # hip_reconfig_clk=dut.hip_reconfig_clk, - # hip_reconfig_address=dut.hip_reconfig_address, - # hip_reconfig_read=dut.hip_reconfig_read, - # hip_reconfig_readdata=dut.hip_reconfig_readdata, - # hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid, - # hip_reconfig_write=dut.hip_reconfig_write, - # hip_reconfig_writedata=dut.hip_reconfig_writedata, - # hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest, - - # Page request service - # prs_event_valid=dut.prs_event_valid, - # prs_event_func=dut.prs_event_func, - # prs_event=dut.prs_event, - - # SR-IOV (VF error) - # vf_err_ur_posted_s0=dut.vf_err_ur_posted_s0, - # vf_err_ur_posted_s1=dut.vf_err_ur_posted_s1, - # vf_err_ur_posted_s2=dut.vf_err_ur_posted_s2, - # vf_err_ur_posted_s3=dut.vf_err_ur_posted_s3, - # vf_err_func_num_s0=dut.vf_err_func_num_s0, - # vf_err_func_num_s1=dut.vf_err_func_num_s1, - # vf_err_func_num_s2=dut.vf_err_func_num_s2, - # vf_err_func_num_s3=dut.vf_err_func_num_s3, - # vf_err_ca_postedreq_s0=dut.vf_err_ca_postedreq_s0, - # vf_err_ca_postedreq_s1=dut.vf_err_ca_postedreq_s1, - # vf_err_ca_postedreq_s2=dut.vf_err_ca_postedreq_s2, - # vf_err_ca_postedreq_s3=dut.vf_err_ca_postedreq_s3, - # vf_err_vf_num_s0=dut.vf_err_vf_num_s0, - # vf_err_vf_num_s1=dut.vf_err_vf_num_s1, - # vf_err_vf_num_s2=dut.vf_err_vf_num_s2, - # vf_err_vf_num_s3=dut.vf_err_vf_num_s3, - # vf_err_poisonedwrreq_s0=dut.vf_err_poisonedwrreq_s0, - # vf_err_poisonedwrreq_s1=dut.vf_err_poisonedwrreq_s1, - # vf_err_poisonedwrreq_s2=dut.vf_err_poisonedwrreq_s2, - # vf_err_poisonedwrreq_s3=dut.vf_err_poisonedwrreq_s3, - # vf_err_poisonedcompl_s0=dut.vf_err_poisonedcompl_s0, - # vf_err_poisonedcompl_s1=dut.vf_err_poisonedcompl_s1, - # vf_err_poisonedcompl_s2=dut.vf_err_poisonedcompl_s2, - # vf_err_poisonedcompl_s3=dut.vf_err_poisonedcompl_s3, - # user_vfnonfatalmsg_func_num=dut.user_vfnonfatalmsg_func_num, - # user_vfnonfatalmsg_vfnum=dut.user_vfnonfatalmsg_vfnum, - # user_sent_vfnonfatalmsg=dut.user_sent_vfnonfatalmsg, - # vf_err_overflow=dut.vf_err_overflow, - - # FLR - # flr_rcvd_pf=dut.flr_rcvd_pf, - # flr_rcvd_vf=dut.flr_rcvd_vf, - # flr_rcvd_pf_num=dut.flr_rcvd_pf_num, - # flr_rcvd_vf_num=dut.flr_rcvd_vf_num, - # flr_completed_pf=dut.flr_completed_pf, - # flr_completed_vf=dut.flr_completed_vf, - # flr_completed_pf_num=dut.flr_completed_pf_num, - # flr_completed_vf_num=dut.flr_completed_vf_num, - - # VirtIO - # virtio_pcicfg_vfaccess=dut.virtio_pcicfg_vfaccess, - # virtio_pcicfg_vfnum=dut.virtio_pcicfg_vfnum, - # virtio_pcicfg_pfnum=dut.virtio_pcicfg_pfnum, - # virtio_pcicfg_bar=dut.virtio_pcicfg_bar, - # virtio_pcicfg_length=dut.virtio_pcicfg_length, - # virtio_pcicfg_baroffset=dut.virtio_pcicfg_baroffset, - # virtio_pcicfg_cfgdata=dut.virtio_pcicfg_cfgdata, - # virtio_pcicfg_cfgwr=dut.virtio_pcicfg_cfgwr, - # virtio_pcicfg_cfgrd=dut.virtio_pcicfg_cfgrd, - # virtio_pcicfg_appvfnum=dut.virtio_pcicfg_appvfnum, - # virtio_pcicfg_apppfnum=dut.virtio_pcicfg_apppfnum, - # virtio_pcicfg_rdack=dut.virtio_pcicfg_rdack, - # virtio_pcicfg_rdbe=dut.virtio_pcicfg_rdbe, - # virtio_pcicfg_data=dut.virtio_pcicfg_data, - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - cocotb.start_soon(Clock(dut.ptp_clk, 2.482, units="ns").start()) - dut.ptp_rst.setimmediatevalue(0) - cocotb.start_soon(Clock(dut.ptp_sample_clk, 10, units="ns").start()) - - # Ethernet - self.qsfpdd_mac = [] - - for x in "ab": - macs = [] - for y in range(1, 9): - cocotb.start_soon(Clock(getattr(dut, f"qsfpdd{x}_mac_{y}_rx_clk"), 2.482, units="ns").start()) - cocotb.start_soon(Clock(getattr(dut, f"qsfpdd{x}_mac_{y}_tx_clk"), 2.482, units="ns").start()) - - mac = EthMac( - tx_clk=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_clk"), - tx_rst=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_rst"), - tx_bus=AxiStreamBus.from_prefix(dut, f"qsfpdd{x}_mac_{y}_tx_axis"), - tx_ptp_time=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_time"), - tx_ptp_ts=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts"), - tx_ptp_ts_tag=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts_tag"), - tx_ptp_ts_valid=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts_valid"), - rx_clk=getattr(dut, f"qsfpdd{x}_mac_{y}_rx_clk"), - rx_rst=getattr(dut, f"qsfpdd{x}_mac_{y}_rx_rst"), - rx_bus=AxiStreamBus.from_prefix(dut, f"qsfpdd{x}_mac_{y}_rx_axis"), - rx_ptp_time=getattr(dut, f"qsfpdd{x}_mac_{y}_rx_ptp_time"), - ifg=12, speed=25e9 - ) - - macs.append(mac) - - getattr(dut, f"qsfpdd{x}_mac_{y}_rx_status").setimmediatevalue(1) - getattr(dut, f"qsfpdd{x}_mac_{y}_rx_lfc_req").setimmediatevalue(0) - getattr(dut, f"qsfpdd{x}_mac_{y}_rx_pfc_req").setimmediatevalue(0) - - self.qsfpdd_mac.append(macs) - - getattr(dut, f"qsfpdd{x}_interrupt_n").setimmediatevalue(1) - getattr(dut, f"qsfpdd{x}_mod_prs_n").setimmediatevalue(0) - getattr(dut, f"qsfpdd{x}_scl_i").setimmediatevalue(1) - getattr(dut, f"qsfpdd{x}_sda_i").setimmediatevalue(1) - - dut.button.setimmediatevalue(0) - dut.sw.setimmediatevalue(0) - - # dut.qspi_dq_i.setimmediatevalue(0) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.ptp_rst.setimmediatevalue(0) - for x in "ab": - for y in range(1, 9): - getattr(self.dut, f"qsfpdd{x}_mac_{y}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfpdd{x}_mac_{y}_tx_rst").setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(1) - for x in "ab": - for y in range(1, 9): - getattr(self.dut, f"qsfpdd{x}_mac_{y}_rx_rst").setimmediatevalue(1) - getattr(self.dut, f"qsfpdd{x}_mac_{y}_tx_rst").setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(0) - for x in "ab": - for y in range(1, 9): - getattr(self.dut, f"qsfpdd{x}_mac_{y}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfpdd{x}_mac_{y}_tx_rst").setimmediatevalue(0) - - await self.rc.enumerate() - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - for macs in self.qsfpdd_mac: - for mac in macs: - if not mac.tx.empty(): - await mac.rx.send(await mac.tx.recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) - await tb.driver.interfaces[0].open() - # await tb.driver.interfaces[1].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(len(tb.driver.interfaces[0].txq)): - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.qsfpdd_mac[0][0].tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfpdd_mac[0][0].rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - # await tb.driver.interfaces[1].start_xmit(data, 0) - - # pkt = await tb.qsfpdd_mac[1][0].tx.recv() - # tb.log.info("Packet: %s", pkt) - - # await tb.qsfpdd_mac[1][0].rx.send(pkt) - - # pkt = await tb.driver.interfaces[1].recv() - - # tb.log.info("Packet: %s", pkt) - # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.qsfpdd_mac[0][0].tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfpdd_mac[0][0].rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Queue mapping offset test") - - data = bytearray([x % 256 for x in range(1024)]) - - tb.loopback_enable = True - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert pkt.queue == k - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) - - tb.log.info("Queue mapping RSS mask test") - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) - - tb.loopback_enable = True - - queues = set() - - for k in range(64): - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=k+0) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - for k in range(64): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - queues.add(pkt.queue) - - assert len(queues) == 4 - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_ptile.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), - os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), - os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "tdma_scheduler.v"), - os.path.join(rtl_dir, "common", "tdma_ber.v"), - os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_td_phc.v"), - os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fc_count.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_msix.v"), - os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_if.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_if_rx.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_if_tx.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_cfg.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_fc_counter.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 2 - parameters['PORTS_PER_IF'] = 1 - parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] - parameters['PORT_MASK'] = 0 - - # Clock configuration - parameters['CLK_PERIOD_NS_NUM'] = 4 - parameters['CLK_PERIOD_NS_DENOM'] = 1 - - # PTP configuration - parameters['PTP_CLK_PERIOD_NS_NUM'] = 2048 - parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 - parameters['PTP_CLOCK_PIPELINE'] = 0 - parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_TX_CLOCK'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 - parameters['PTP_PORT_CDC_PIPELINE'] = 0 - parameters['PTP_PEROUT_ENABLE'] = 1 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['CQ_OP_TABLE_SIZE'] = 32 - parameters['EQN_WIDTH'] = 6 - parameters['TX_QUEUE_INDEX_WIDTH'] = 13 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 - parameters['EQ_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) - - # TX and RX engine configuration - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) - - # Scheduler configuration - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Interface configuration - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_CPL_FIFO_DEPTH'] = 32 - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['LFC_ENABLE'] = 1 - parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 32768 - - # Application block configuration - parameters['APP_ID'] = 0x00000000 - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_IMM_ENABLE'] = 0 - parameters['DMA_IMM_WIDTH'] = 32 - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['SEG_COUNT'] = 2 - parameters['SEG_DATA_WIDTH'] = 256 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - - # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 0 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0 - parameters['AXIS_ETH_RX_PIPELINE'] = 0 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - )