From 009560f583ee35ad4cdfccfe0ce8bc47b7ce200c Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 7 Nov 2023 12:18:46 -0800 Subject: [PATCH] Use latest version of cocotbext-eth Signed-off-by: Alex Forencich --- tb/axis_baser_rx_64/test_axis_baser_rx_64.py | 2 +- tb/axis_baser_tx_64/test_axis_baser_tx_64.py | 2 +- tb/axis_gmii_rx/test_axis_gmii_rx.py | 2 +- tb/axis_gmii_tx/test_axis_gmii_tx.py | 2 +- tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py | 2 +- tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py | 2 +- tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py | 2 +- tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py | 2 +- tb/eth_mac_10g/test_eth_mac_10g.py | 4 ++-- tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py | 2 +- tb/eth_mac_1g/test_eth_mac_1g.py | 4 ++-- tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py | 4 ++-- tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py | 2 +- tb/ptp_clock_cdc/test_ptp_clock_cdc.py | 4 ++-- tb/ptp_perout/test_ptp_perout.py | 2 +- tox.ini | 2 +- 16 files changed, 20 insertions(+), 20 deletions(-) diff --git a/tb/axis_baser_rx_64/test_axis_baser_rx_64.py b/tb/axis_baser_rx_64/test_axis_baser_rx_64.py index 8d6330ade..94e3537e3 100644 --- a/tb/axis_baser_rx_64/test_axis_baser_rx_64.py +++ b/tb/axis_baser_rx_64/test_axis_baser_rx_64.py @@ -62,7 +62,7 @@ class TB: self.source = BaseRSerdesSource(dut.encoded_rx_data, dut.encoded_rx_hdr, dut.clk, scramble=False) self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) dut.cfg_rx_enable.setimmediatevalue(0) diff --git a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py index 1c11aa066..696e62a10 100644 --- a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py +++ b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py @@ -70,7 +70,7 @@ class TB: self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst) self.sink = BaseRSerdesSink(dut.encoded_tx_data, dut.encoded_tx_hdr, dut.clk, scramble=False) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) dut.cfg_ifg.setimmediatevalue(0) diff --git a/tb/axis_gmii_rx/test_axis_gmii_rx.py b/tb/axis_gmii_rx/test_axis_gmii_rx.py index ed2c381c4..8d38c2609 100644 --- a/tb/axis_gmii_rx/test_axis_gmii_rx.py +++ b/tb/axis_gmii_rx/test_axis_gmii_rx.py @@ -55,7 +55,7 @@ class TB: dut.clk, dut.rst, dut.clk_enable, dut.mii_select) self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) dut.clk_enable.setimmediatevalue(1) dut.mii_select.setimmediatevalue(0) diff --git a/tb/axis_gmii_tx/test_axis_gmii_tx.py b/tb/axis_gmii_tx/test_axis_gmii_tx.py index 0fb466c59..9072cc571 100644 --- a/tb/axis_gmii_tx/test_axis_gmii_tx.py +++ b/tb/axis_gmii_tx/test_axis_gmii_tx.py @@ -62,7 +62,7 @@ class TB: self.sink = GmiiSink(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en, dut.clk, dut.rst, dut.clk_enable, dut.mii_select) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) dut.clk_enable.setimmediatevalue(1) diff --git a/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py b/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py index b50138b02..5f7b8bb1c 100644 --- a/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py +++ b/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py @@ -51,7 +51,7 @@ class TB: self.source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.clk, dut.rst) self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) dut.cfg_rx_enable.setimmediatevalue(0) diff --git a/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py b/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py index b5b29735d..2d3dcb9dc 100644 --- a/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py +++ b/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py @@ -51,7 +51,7 @@ class TB: self.source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.clk, dut.rst) self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) dut.cfg_rx_enable.setimmediatevalue(0) diff --git a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py index 6ce0161d7..a4f7db0f0 100644 --- a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py +++ b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py @@ -59,7 +59,7 @@ class TB: self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst) self.sink = XgmiiSink(dut.xgmii_txd, dut.xgmii_txc, dut.clk, dut.rst) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) dut.cfg_ifg.setimmediatevalue(0) diff --git a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py index 54cbf3ed9..711a235cc 100644 --- a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py +++ b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py @@ -59,7 +59,7 @@ class TB: self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst) self.sink = XgmiiSink(dut.xgmii_txd, dut.xgmii_txc, dut.clk, dut.rst) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) dut.cfg_ifg.setimmediatevalue(0) diff --git a/tb/eth_mac_10g/test_eth_mac_10g.py b/tb/eth_mac_10g/test_eth_mac_10g.py index a4c19be2a..5e017569b 100644 --- a/tb/eth_mac_10g/test_eth_mac_10g.py +++ b/tb/eth_mac_10g/test_eth_mac_10g.py @@ -71,8 +71,8 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) - self.rx_ptp_clock = PtpClockSimTime(ts_64=dut.rx_ptp_ts, clock=dut.rx_clk) - self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk) + self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk) + self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) dut.tx_lfc_req.setimmediatevalue(0) diff --git a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py index 3ba0a2655..cf98b4fdb 100644 --- a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py +++ b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py @@ -70,7 +70,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts_96, clock=dut.logic_clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts_96, clock=dut.logic_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) dut.ptp_ts_step.setimmediatevalue(0) diff --git a/tb/eth_mac_1g/test_eth_mac_1g.py b/tb/eth_mac_1g/test_eth_mac_1g.py index af2173d52..ba047d1b9 100644 --- a/tb/eth_mac_1g/test_eth_mac_1g.py +++ b/tb/eth_mac_1g/test_eth_mac_1g.py @@ -73,8 +73,8 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) - self.rx_ptp_clock = PtpClockSimTime(ts_64=dut.rx_ptp_ts, clock=dut.rx_clk) - self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk) + self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk) + self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) dut.tx_lfc_req.setimmediatevalue(0) diff --git a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py index 13f8f51d5..436d98a67 100644 --- a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py +++ b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py @@ -79,8 +79,8 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) - self.rx_ptp_clock = PtpClockSimTime(ts_64=dut.rx_ptp_ts, clock=dut.rx_clk) - self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk) + self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk) + self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) dut.cfg_ifg.setimmediatevalue(0) diff --git a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py index 43a6269b7..1afeb148c 100644 --- a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py +++ b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py @@ -81,7 +81,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) - self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts_96, clock=dut.logic_clk) + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts_96, clock=dut.logic_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) dut.ptp_ts_step.setimmediatevalue(0) diff --git a/tb/ptp_clock_cdc/test_ptp_clock_cdc.py b/tb/ptp_clock_cdc/test_ptp_clock_cdc.py index 52ff65455..fd8222b9e 100644 --- a/tb/ptp_clock_cdc/test_ptp_clock_cdc.py +++ b/tb/ptp_clock_cdc/test_ptp_clock_cdc.py @@ -49,7 +49,7 @@ class TB: if len(dut.input_ts) == 64: self.ptp_clock = PtpClock( - ts_64=dut.input_ts, + ts_rel=dut.input_ts, ts_step=dut.input_ts_step, clock=dut.input_clk, reset=dut.input_rst, @@ -57,7 +57,7 @@ class TB: ) else: self.ptp_clock = PtpClock( - ts_96=dut.input_ts, + ts_tod=dut.input_ts, ts_step=dut.input_ts_step, clock=dut.input_clk, reset=dut.input_rst, diff --git a/tb/ptp_perout/test_ptp_perout.py b/tb/ptp_perout/test_ptp_perout.py index 326989072..fec20a9b2 100644 --- a/tb/ptp_perout/test_ptp_perout.py +++ b/tb/ptp_perout/test_ptp_perout.py @@ -45,7 +45,7 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) self.ptp_clock = PtpClock( - ts_96=dut.input_ts_96, + ts_tod=dut.input_ts_96, ts_step=dut.input_ts_step, clock=dut.clk, reset=dut.rst, diff --git a/tox.ini b/tox.ini index 476b0951b..363d24a5b 100644 --- a/tox.ini +++ b/tox.ini @@ -18,7 +18,7 @@ deps = cocotb-bus == 0.2.1 cocotb-test == 0.2.4 cocotbext-axi == 0.1.20 - cocotbext-eth == 0.1.20 + cocotbext-eth == 0.1.22 scapy == 2.5.0 jinja2 == 3.1.2