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Remove recursively-expanded macros for module parameters in makefiles

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-02-17 16:18:44 -08:00
parent de3ec216a0
commit 00c200f881
20 changed files with 215 additions and 215 deletions
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38
tb/axi_adapter/Makefile
View File

@ -34,25 +34,25 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
# module parameters
export PARAM_ADDR_WIDTH ?= 32
export PARAM_S_DATA_WIDTH ?= 32
export PARAM_S_STRB_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
export PARAM_M_DATA_WIDTH ?= 32
export PARAM_M_STRB_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH ?= 8
export PARAM_AWUSER_ENABLE ?= 0
export PARAM_AWUSER_WIDTH ?= 1
export PARAM_WUSER_ENABLE ?= 0
export PARAM_WUSER_WIDTH ?= 1
export PARAM_BUSER_ENABLE ?= 0
export PARAM_BUSER_WIDTH ?= 1
export PARAM_ARUSER_ENABLE ?= 0
export PARAM_ARUSER_WIDTH ?= 1
export PARAM_RUSER_ENABLE ?= 0
export PARAM_RUSER_WIDTH ?= 1
export PARAM_CONVERT_BURST ?= 1
export PARAM_CONVERT_NARROW_BURST ?= 1
export PARAM_FORWARD_ID ?= 1
export PARAM_ADDR_WIDTH := 32
export PARAM_S_DATA_WIDTH := 32
export PARAM_S_STRB_WIDTH := $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
export PARAM_M_DATA_WIDTH := 32
export PARAM_M_STRB_WIDTH := $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH := 8
export PARAM_AWUSER_ENABLE := 0
export PARAM_AWUSER_WIDTH := 1
export PARAM_WUSER_ENABLE := 0
export PARAM_WUSER_WIDTH := 1
export PARAM_BUSER_ENABLE := 0
export PARAM_BUSER_WIDTH := 1
export PARAM_ARUSER_ENABLE := 0
export PARAM_ARUSER_WIDTH := 1
export PARAM_RUSER_ENABLE := 0
export PARAM_RUSER_WIDTH := 1
export PARAM_CONVERT_BURST := 1
export PARAM_CONVERT_NARROW_BURST := 1
export PARAM_FORWARD_ID := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

16
tb/axi_axil_adapter/Makefile
View File

@ -34,14 +34,14 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
# module parameters
export PARAM_ADDR_WIDTH ?= 32
export PARAM_AXI_DATA_WIDTH ?= 32
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8
export PARAM_AXIL_DATA_WIDTH ?= 32
export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
export PARAM_CONVERT_BURST ?= 1
export PARAM_CONVERT_NARROW_BURST ?= 1
export PARAM_ADDR_WIDTH := 32
export PARAM_AXI_DATA_WIDTH := 32
export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXIL_DATA_WIDTH := 32
export PARAM_AXIL_STRB_WIDTH := $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
export PARAM_CONVERT_BURST := 1
export PARAM_CONVERT_NARROW_BURST := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

16
tb/axi_cdma/Makefile
View File

@ -32,14 +32,14 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_AXI_DATA_WIDTH = 32
export PARAM_AXI_ADDR_WIDTH = 16
export PARAM_AXI_STRB_WIDTH = $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH = 8
export PARAM_AXI_MAX_BURST_LEN = 16
export PARAM_LEN_WIDTH = 20
export PARAM_TAG_WIDTH = 8
export PARAM_ENABLE_UNALIGNED = 0
export PARAM_AXI_DATA_WIDTH := 32
export PARAM_AXI_ADDR_WIDTH := 16
export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN := 16
export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH := 8
export PARAM_ENABLE_UNALIGNED := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

36
tb/axi_crossbar/Makefile
View File

@ -26,8 +26,8 @@ WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
export PARAM_S_COUNT ?= 4
export PARAM_M_COUNT ?= 4
export PARAM_S_COUNT := 4
export PARAM_M_COUNT := 4
DUT = axi_crossbar
WRAPPER = $(DUT)_wrap_$(PARAM_S_COUNT)x$(PARAM_M_COUNT)
@ -44,22 +44,22 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 32
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_S_ID_WIDTH ?= 8
export PARAM_M_ID_WIDTH ?= $(shell expr $(PARAM_S_ID_WIDTH) + 2 )
export PARAM_AWUSER_ENABLE ?= 0
export PARAM_AWUSER_WIDTH ?= 1
export PARAM_WUSER_ENABLE ?= 0
export PARAM_WUSER_WIDTH ?= 1
export PARAM_BUSER_ENABLE ?= 0
export PARAM_BUSER_WIDTH ?= 1
export PARAM_ARUSER_ENABLE ?= 0
export PARAM_ARUSER_WIDTH ?= 1
export PARAM_RUSER_ENABLE ?= 0
export PARAM_RUSER_WIDTH ?= 1
export PARAM_M_REGIONS ?= 1
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 32
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_S_ID_WIDTH := 8
export PARAM_M_ID_WIDTH := $(shell expr $(PARAM_S_ID_WIDTH) + 2 )
export PARAM_AWUSER_ENABLE := 0
export PARAM_AWUSER_WIDTH := 1
export PARAM_WUSER_ENABLE := 0
export PARAM_WUSER_WIDTH := 1
export PARAM_BUSER_ENABLE := 0
export PARAM_BUSER_WIDTH := 1
export PARAM_ARUSER_ENABLE := 0
export PARAM_ARUSER_WIDTH := 1
export PARAM_RUSER_ENABLE := 0
export PARAM_RUSER_WIDTH := 1
export PARAM_M_REGIONS := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

38
tb/axi_dma/Makefile
View File

@ -34,25 +34,25 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
# module parameters
export PARAM_AXI_DATA_WIDTH = 32
export PARAM_AXI_ADDR_WIDTH = 16
export PARAM_AXI_STRB_WIDTH = $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH = 8
export PARAM_AXI_MAX_BURST_LEN = 16
export PARAM_AXIS_DATA_WIDTH = $(PARAM_AXI_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE = $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH = $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_AXIS_LAST_ENABLE = 1
export PARAM_AXIS_ID_ENABLE = 1
export PARAM_AXIS_ID_WIDTH = 8
export PARAM_AXIS_DEST_ENABLE = 0
export PARAM_AXIS_DEST_WIDTH = 8
export PARAM_AXIS_USER_ENABLE = 1
export PARAM_AXIS_USER_WIDTH = 1
export PARAM_LEN_WIDTH = 20
export PARAM_TAG_WIDTH = 8
export PARAM_ENABLE_SG = 0
export PARAM_ENABLE_UNALIGNED = 0
export PARAM_AXI_DATA_WIDTH := 32
export PARAM_AXI_ADDR_WIDTH := 16
export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN := 16
export PARAM_AXIS_DATA_WIDTH := $(PARAM_AXI_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_AXIS_LAST_ENABLE := 1
export PARAM_AXIS_ID_ENABLE := 1
export PARAM_AXIS_ID_WIDTH := 8
export PARAM_AXIS_DEST_ENABLE := 0
export PARAM_AXIS_DEST_WIDTH := 8
export PARAM_AXIS_USER_ENABLE := 1
export PARAM_AXIS_USER_WIDTH := 1
export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH := 8
export PARAM_ENABLE_SG := 0
export PARAM_ENABLE_UNALIGNED := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

38
tb/axi_dma_rd/Makefile
View File

@ -32,25 +32,25 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_AXI_DATA_WIDTH = 32
export PARAM_AXI_ADDR_WIDTH = 16
export PARAM_AXI_STRB_WIDTH = $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH = 8
export PARAM_AXI_MAX_BURST_LEN = 16
export PARAM_AXIS_DATA_WIDTH = $(PARAM_AXI_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE = $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH = $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_AXIS_LAST_ENABLE = 1
export PARAM_AXIS_ID_ENABLE = 1
export PARAM_AXIS_ID_WIDTH = 8
export PARAM_AXIS_DEST_ENABLE = 0
export PARAM_AXIS_DEST_WIDTH = 8
export PARAM_AXIS_USER_ENABLE = 1
export PARAM_AXIS_USER_WIDTH = 1
export PARAM_LEN_WIDTH = 20
export PARAM_TAG_WIDTH = 8
export PARAM_ENABLE_SG = 0
export PARAM_ENABLE_UNALIGNED = 0
export PARAM_AXI_DATA_WIDTH := 32
export PARAM_AXI_ADDR_WIDTH := 16
export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN := 16
export PARAM_AXIS_DATA_WIDTH := $(PARAM_AXI_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_AXIS_LAST_ENABLE := 1
export PARAM_AXIS_ID_ENABLE := 1
export PARAM_AXIS_ID_WIDTH := 8
export PARAM_AXIS_DEST_ENABLE := 0
export PARAM_AXIS_DEST_WIDTH := 8
export PARAM_AXIS_USER_ENABLE := 1
export PARAM_AXIS_USER_WIDTH := 1
export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH := 8
export PARAM_ENABLE_SG := 0
export PARAM_ENABLE_UNALIGNED := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

38
tb/axi_dma_wr/Makefile
View File

@ -32,25 +32,25 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_AXI_DATA_WIDTH = 32
export PARAM_AXI_ADDR_WIDTH = 16
export PARAM_AXI_STRB_WIDTH = $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH = 8
export PARAM_AXI_MAX_BURST_LEN = 16
export PARAM_AXIS_DATA_WIDTH = $(PARAM_AXI_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE = $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH = $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_AXIS_LAST_ENABLE = 1
export PARAM_AXIS_ID_ENABLE = 1
export PARAM_AXIS_ID_WIDTH = 8
export PARAM_AXIS_DEST_ENABLE = 0
export PARAM_AXIS_DEST_WIDTH = 8
export PARAM_AXIS_USER_ENABLE = 1
export PARAM_AXIS_USER_WIDTH = 1
export PARAM_LEN_WIDTH = 20
export PARAM_TAG_WIDTH = 8
export PARAM_ENABLE_SG = 0
export PARAM_ENABLE_UNALIGNED = 0
export PARAM_AXI_DATA_WIDTH := 32
export PARAM_AXI_ADDR_WIDTH := 16
export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN := 16
export PARAM_AXIS_DATA_WIDTH := $(PARAM_AXI_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_AXIS_LAST_ENABLE := 1
export PARAM_AXIS_ID_ENABLE := 1
export PARAM_AXIS_ID_WIDTH := 8
export PARAM_AXIS_DEST_ENABLE := 0
export PARAM_AXIS_DEST_WIDTH := 8
export PARAM_AXIS_USER_ENABLE := 1
export PARAM_AXIS_USER_WIDTH := 1
export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH := 8
export PARAM_ENABLE_SG := 0
export PARAM_ENABLE_UNALIGNED := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

10
tb/axi_dp_ram/Makefile
View File

@ -35,11 +35,11 @@ VERILOG_SOURCES += ../../rtl/axi_ram_wr_if.v
VERILOG_SOURCES += ../../rtl/axi_ram_rd_if.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 16
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH ?= 8
export PARAM_PIPELINE_OUTPUT ?= 0
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 16
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH := 8
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

36
tb/axi_fifo/Makefile
View File

@ -34,24 +34,24 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 32
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH ?= 8
export PARAM_AWUSER_ENABLE ?= 0
export PARAM_AWUSER_WIDTH ?= 1
export PARAM_WUSER_ENABLE ?= 0
export PARAM_WUSER_WIDTH ?= 1
export PARAM_BUSER_ENABLE ?= 0
export PARAM_BUSER_WIDTH ?= 1
export PARAM_ARUSER_ENABLE ?= 0
export PARAM_ARUSER_WIDTH ?= 1
export PARAM_RUSER_ENABLE ?= 0
export PARAM_RUSER_WIDTH ?= 1
export PARAM_WRITE_FIFO_DEPTH ?= 32
export PARAM_READ_FIFO_DEPTH ?= 32
export PARAM_WRITE_FIFO_DELAY ?= 0
export PARAM_READ_FIFO_DELAY ?= 0
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 32
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH := 8
export PARAM_AWUSER_ENABLE := 0
export PARAM_AWUSER_WIDTH := 1
export PARAM_WUSER_ENABLE := 0
export PARAM_WUSER_WIDTH := 1
export PARAM_BUSER_ENABLE := 0
export PARAM_BUSER_WIDTH := 1
export PARAM_ARUSER_ENABLE := 0
export PARAM_ARUSER_WIDTH := 1
export PARAM_RUSER_ENABLE := 0
export PARAM_RUSER_WIDTH := 1
export PARAM_WRITE_FIFO_DEPTH := 32
export PARAM_READ_FIFO_DEPTH := 32
export PARAM_WRITE_FIFO_DELAY := 0
export PARAM_READ_FIFO_DELAY := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

36
tb/axi_interconnect/Makefile
View File

@ -26,8 +26,8 @@ WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
export PARAM_S_COUNT ?= 4
export PARAM_M_COUNT ?= 4
export PARAM_S_COUNT := 4
export PARAM_M_COUNT := 4
DUT = axi_interconnect
WRAPPER = $(DUT)_wrap_$(PARAM_S_COUNT)x$(PARAM_M_COUNT)
@ -39,22 +39,22 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 32
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH ?= 8
export PARAM_AWUSER_ENABLE ?= 0
export PARAM_AWUSER_WIDTH ?= 1
export PARAM_WUSER_ENABLE ?= 0
export PARAM_WUSER_WIDTH ?= 1
export PARAM_BUSER_ENABLE ?= 0
export PARAM_BUSER_WIDTH ?= 1
export PARAM_ARUSER_ENABLE ?= 0
export PARAM_ARUSER_WIDTH ?= 1
export PARAM_RUSER_ENABLE ?= 0
export PARAM_RUSER_WIDTH ?= 1
export PARAM_FORWARD_ID ?= 1
export PARAM_M_REGIONS ?= 1
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 32
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH := 8
export PARAM_AWUSER_ENABLE := 0
export PARAM_AWUSER_WIDTH := 1
export PARAM_WUSER_ENABLE := 0
export PARAM_WUSER_WIDTH := 1
export PARAM_BUSER_ENABLE := 0
export PARAM_BUSER_WIDTH := 1
export PARAM_ARUSER_ENABLE := 0
export PARAM_ARUSER_WIDTH := 1
export PARAM_RUSER_ENABLE := 0
export PARAM_RUSER_WIDTH := 1
export PARAM_FORWARD_ID := 1
export PARAM_M_REGIONS := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

10
tb/axi_ram/Makefile
View File

@ -32,11 +32,11 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 16
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH ?= 8
export PARAM_PIPELINE_OUTPUT ?= 0
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 16
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH := 8
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

38
tb/axi_register/Makefile
View File

@ -36,25 +36,25 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
REG_TYPE ?= 2
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 32
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH ?= 8
export PARAM_AWUSER_ENABLE ?= 0
export PARAM_AWUSER_WIDTH ?= 1
export PARAM_WUSER_ENABLE ?= 0
export PARAM_WUSER_WIDTH ?= 1
export PARAM_BUSER_ENABLE ?= 0
export PARAM_BUSER_WIDTH ?= 1
export PARAM_ARUSER_ENABLE ?= 0
export PARAM_ARUSER_WIDTH ?= 1
export PARAM_RUSER_ENABLE ?= 0
export PARAM_RUSER_WIDTH ?= 1
export PARAM_AW_REG_TYPE ?= $(REG_TYPE)
export PARAM_W_REG_TYPE ?= $(REG_TYPE)
export PARAM_B_REG_TYPE ?= $(REG_TYPE)
export PARAM_AR_REG_TYPE ?= $(REG_TYPE)
export PARAM_R_REG_TYPE ?= $(REG_TYPE)
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 32
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ID_WIDTH := 8
export PARAM_AWUSER_ENABLE := 0
export PARAM_AWUSER_WIDTH := 1
export PARAM_WUSER_ENABLE := 0
export PARAM_WUSER_WIDTH := 1
export PARAM_BUSER_ENABLE := 0
export PARAM_BUSER_WIDTH := 1
export PARAM_ARUSER_ENABLE := 0
export PARAM_ARUSER_WIDTH := 1
export PARAM_RUSER_ENABLE := 0
export PARAM_RUSER_WIDTH := 1
export PARAM_AW_REG_TYPE := $(REG_TYPE)
export PARAM_W_REG_TYPE := $(REG_TYPE)
export PARAM_B_REG_TYPE := $(REG_TYPE)
export PARAM_AR_REG_TYPE := $(REG_TYPE)
export PARAM_R_REG_TYPE := $(REG_TYPE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst

10
tb/axil_adapter/Makefile
View File

@ -34,11 +34,11 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
# module parameters
export PARAM_ADDR_WIDTH ?= 32
export PARAM_S_DATA_WIDTH ?= 32
export PARAM_S_STRB_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
export PARAM_M_DATA_WIDTH ?= 32
export PARAM_M_STRB_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
export PARAM_ADDR_WIDTH := 32
export PARAM_S_DATA_WIDTH := 32
export PARAM_S_STRB_WIDTH := $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
export PARAM_M_DATA_WIDTH := 32
export PARAM_M_STRB_WIDTH := $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst

6
tb/axil_cdc/Makefile
View File

@ -34,9 +34,9 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 32
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 32
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst

12
tb/axil_crossbar/Makefile
View File

@ -26,8 +26,8 @@ WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
export PARAM_S_COUNT ?= 4
export PARAM_M_COUNT ?= 4
export PARAM_S_COUNT := 4
export PARAM_M_COUNT := 4
DUT = axil_crossbar
WRAPPER = $(DUT)_wrap_$(PARAM_S_COUNT)x$(PARAM_M_COUNT)
@ -44,10 +44,10 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 32
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_M_REGIONS ?= 1
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 32
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_M_REGIONS := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

8
tb/axil_dp_ram/Makefile
View File

@ -32,10 +32,10 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 16
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_PIPELINE_OUTPUT ?= 0
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 16
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

12
tb/axil_interconnect/Makefile
View File

@ -26,8 +26,8 @@ WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
export PARAM_S_COUNT ?= 4
export PARAM_M_COUNT ?= 4
export PARAM_S_COUNT := 4
export PARAM_M_COUNT := 4
DUT = axil_interconnect
WRAPPER = $(DUT)_wrap_$(PARAM_S_COUNT)x$(PARAM_M_COUNT)
@ -39,10 +39,10 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 32
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_M_REGIONS ?= 1
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 32
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_M_REGIONS := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

8
tb/axil_ram/Makefile
View File

@ -32,10 +32,10 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 16
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_PIPELINE_OUTPUT ?= 0
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 16
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

8
tb/axil_reg_if/Makefile
View File

@ -35,10 +35,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 16
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_TIMEOUT ?= 4
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 16
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_TIMEOUT := 4
ifeq ($(SIM), icarus)
PLUSARGS += -fst

16
tb/axil_register/Makefile
View File

@ -36,14 +36,14 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
REG_TYPE ?= 1
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 32
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_AW_REG_TYPE ?= $(REG_TYPE)
export PARAM_W_REG_TYPE ?= $(REG_TYPE)
export PARAM_B_REG_TYPE ?= $(REG_TYPE)
export PARAM_AR_REG_TYPE ?= $(REG_TYPE)
export PARAM_R_REG_TYPE ?= $(REG_TYPE)
export PARAM_DATA_WIDTH := 32
export PARAM_ADDR_WIDTH := 32
export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_AW_REG_TYPE := $(REG_TYPE)
export PARAM_W_REG_TYPE := $(REG_TYPE)
export PARAM_B_REG_TYPE := $(REG_TYPE)
export PARAM_AR_REG_TYPE := $(REG_TYPE)
export PARAM_R_REG_TYPE := $(REG_TYPE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst