diff --git a/example/DE5-Net/fpga/fpga/Makefile b/example/DE5-Net/fpga/fpga/Makefile
index 61d619cc7..fba61fa3a 100644
--- a/example/DE5-Net/fpga/fpga/Makefile
+++ b/example/DE5-Net/fpga/fpga/Makefile
@@ -14,8 +14,8 @@ SYN_FILES += rtl/i2c_master.v
 SYN_FILES += rtl/si570_i2c_init.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_tx.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
 SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
diff --git a/example/DE5-Net/fpga/tb/test_fpga_core.py b/example/DE5-Net/fpga/tb/test_fpga_core.py
index 56ded4c0f..0fd1a8b1b 100755
--- a/example/DE5-Net/fpga/tb/test_fpga_core.py
+++ b/example/DE5-Net/fpga/tb/test_fpga_core.py
@@ -39,8 +39,8 @@ srcs = []
 srcs.append("../rtl/%s.v" % module)
 srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
 srcs.append("../lib/eth/rtl/eth_mac_10g.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_tx.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
 srcs.append("../lib/eth/rtl/lfsr.v")
 srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
 srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
diff --git a/example/HXT100G/fpga/fpga/Makefile b/example/HXT100G/fpga/fpga/Makefile
index 60e3ea71f..06c1a6e4a 100644
--- a/example/HXT100G/fpga/fpga/Makefile
+++ b/example/HXT100G/fpga/fpga/Makefile
@@ -19,8 +19,8 @@ SYN_FILES += rtl/gth_i2c_init.v
 SYN_FILES += rtl/eth_gth_phy_quad.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_tx.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
 SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
diff --git a/example/HXT100G/fpga/tb/test_fpga_core.py b/example/HXT100G/fpga/tb/test_fpga_core.py
index 024c6957b..baf1c7b17 100755
--- a/example/HXT100G/fpga/tb/test_fpga_core.py
+++ b/example/HXT100G/fpga/tb/test_fpga_core.py
@@ -39,8 +39,8 @@ srcs = []
 srcs.append("../rtl/%s.v" % module)
 srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
 srcs.append("../lib/eth/rtl/eth_mac_10g.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_tx.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
 srcs.append("../lib/eth/rtl/lfsr.v")
 srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
 srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
diff --git a/example/HXT100G/fpga_cxpt16/fpga/Makefile b/example/HXT100G/fpga_cxpt16/fpga/Makefile
index e152f17a4..721af3e0e 100644
--- a/example/HXT100G/fpga_cxpt16/fpga/Makefile
+++ b/example/HXT100G/fpga_cxpt16/fpga/Makefile
@@ -20,8 +20,8 @@ SYN_FILES += rtl/eth_gth_phy_quad.v
 SYN_FILES += rtl/axis_crosspoint_16x16.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_tx.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
 SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
diff --git a/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py b/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py
index b2a1cd1a8..b2ac78167 100755
--- a/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py
+++ b/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py
@@ -38,8 +38,8 @@ srcs.append("../rtl/%s.v" % module)
 srcs.append("../rtl/axis_crosspoint_16x16.v")
 srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
 srcs.append("../lib/eth/rtl/eth_mac_10g.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_tx.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
 srcs.append("../lib/eth/rtl/lfsr.v")
 srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
 srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
diff --git a/example/VCU108/fpga_10g/fpga/Makefile b/example/VCU108/fpga_10g/fpga/Makefile
index fd4c7c93b..8715ba573 100644
--- a/example/VCU108/fpga_10g/fpga/Makefile
+++ b/example/VCU108/fpga_10g/fpga/Makefile
@@ -18,8 +18,8 @@ SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
 SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_tx.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
 SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
diff --git a/example/VCU108/fpga_10g/tb/test_fpga_core.py b/example/VCU108/fpga_10g/tb/test_fpga_core.py
index f16c8cb44..b1dc4cfef 100755
--- a/example/VCU108/fpga_10g/tb/test_fpga_core.py
+++ b/example/VCU108/fpga_10g/tb/test_fpga_core.py
@@ -44,8 +44,8 @@ srcs.append("../lib/eth/rtl/axis_gmii_rx.v")
 srcs.append("../lib/eth/rtl/axis_gmii_tx.v")
 srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
 srcs.append("../lib/eth/rtl/eth_mac_10g.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_tx.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
 srcs.append("../lib/eth/rtl/lfsr.v")
 srcs.append("../lib/eth/rtl/eth_axis_rx.v")
 srcs.append("../lib/eth/rtl/eth_axis_tx.v")
diff --git a/example/VCU118/fpga_10g/fpga/Makefile b/example/VCU118/fpga_10g/fpga/Makefile
index 3f273da63..ffd94c3b9 100644
--- a/example/VCU118/fpga_10g/fpga/Makefile
+++ b/example/VCU118/fpga_10g/fpga/Makefile
@@ -17,8 +17,8 @@ SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
 SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v
-SYN_FILES += lib/eth/rtl/eth_mac_10g_tx.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
 SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
diff --git a/example/VCU118/fpga_10g/tb/test_fpga_core.py b/example/VCU118/fpga_10g/tb/test_fpga_core.py
index 8226bb74e..87f8c3db5 100755
--- a/example/VCU118/fpga_10g/tb/test_fpga_core.py
+++ b/example/VCU118/fpga_10g/tb/test_fpga_core.py
@@ -44,8 +44,8 @@ srcs.append("../lib/eth/rtl/axis_gmii_rx.v")
 srcs.append("../lib/eth/rtl/axis_gmii_tx.v")
 srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
 srcs.append("../lib/eth/rtl/eth_mac_10g.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v")
-srcs.append("../lib/eth/rtl/eth_mac_10g_tx.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
 srcs.append("../lib/eth/rtl/lfsr.v")
 srcs.append("../lib/eth/rtl/eth_axis_rx.v")
 srcs.append("../lib/eth/rtl/eth_axis_tx.v")