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https://github.com/corundum/corundum.git
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Testbench updates
This commit is contained in:
parent
4d3036b9d0
commit
013e88253e
@ -358,12 +358,14 @@ def bench():
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yield clk.posedge
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while s_eth_payload_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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yield sink.wait()
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rx_frame = sink.recv()
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@ -361,12 +361,14 @@ def bench():
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yield clk.posedge
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while s_eth_payload_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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yield sink.wait()
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rx_frame = sink.recv()
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@ -144,12 +144,14 @@ def bench():
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def wait_pause_source():
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while s_axis_tvalid or m_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_axis_tvalid or m_axis_tvalid:
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@ -150,12 +150,14 @@ def bench():
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def wait_pause_source():
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while s_axis_tvalid or m_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_axis_tvalid or m_axis_tvalid:
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@ -136,12 +136,14 @@ def bench():
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def wait_pause_source():
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while s_axis_tvalid or m_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_axis_tvalid or m_axis_tvalid:
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@ -142,12 +142,14 @@ def bench():
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def wait_pause_source():
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while s_axis_tvalid or m_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_axis_tvalid or m_axis_tvalid:
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@ -142,12 +142,14 @@ def bench():
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def wait_pause_source():
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while s_axis_tvalid or m_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_axis_tvalid or m_axis_tvalid:
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@ -136,12 +136,14 @@ def bench():
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def wait_pause_source():
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while s_axis_tvalid or m_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_axis_tvalid or m_axis_tvalid:
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@ -335,19 +335,18 @@ def bench():
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yield clk.posedge
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while s_eth_payload_axis_tvalid:
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source_pause_list[0].next = True
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source_pause_list[1].next = True
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source_pause_list[2].next = True
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source_pause_list[3].next = True
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yield clk.posedge
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield clk.posedge
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source_pause_list[0].next = False
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source_pause_list[1].next = False
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source_pause_list[2].next = False
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source_pause_list[3].next = False
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for k in range(S_COUNT):
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source_pause_list[k].next = True
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield sink.wait()
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rx_frame = sink.recv()
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@ -335,19 +335,18 @@ def bench():
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yield clk.posedge
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while s_eth_payload_axis_tvalid:
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source_pause_list[0].next = True
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source_pause_list[1].next = True
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source_pause_list[2].next = True
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source_pause_list[3].next = True
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yield clk.posedge
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield clk.posedge
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source_pause_list[0].next = False
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source_pause_list[1].next = False
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source_pause_list[2].next = False
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source_pause_list[3].next = False
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for k in range(S_COUNT):
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source_pause_list[k].next = True
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield sink.wait()
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rx_frame = sink.recv()
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@ -153,12 +153,14 @@ def bench():
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def wait_pause_source():
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while s_axis_tvalid or m_eth_payload_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_axis_tvalid or m_eth_payload_axis_tvalid:
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@ -159,12 +159,14 @@ def bench():
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def wait_pause_source():
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while s_axis_tvalid or m_eth_payload_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_axis_tvalid or m_eth_payload_axis_tvalid:
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@ -144,12 +144,14 @@ def bench():
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def wait_pause_source():
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while s_eth_payload_axis_tvalid or m_axis_tvalid or s_eth_hdr_valid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_eth_payload_axis_tvalid or m_axis_tvalid or s_eth_hdr_valid:
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@ -150,12 +150,14 @@ def bench():
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def wait_pause_source():
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while s_eth_payload_axis_tvalid or m_axis_tvalid or s_eth_hdr_valid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_eth_payload_axis_tvalid or m_axis_tvalid or s_eth_hdr_valid:
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@ -354,14 +354,16 @@ def bench():
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yield clk.posedge
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while s_eth_payload_axis_tvalid or s_eth_hdr_valid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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select.next = 2
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source_pause.next = False
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yield sink_list[1].wait()
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rx_frame = sink_list[1].recv()
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@ -396,17 +398,13 @@ def bench():
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yield clk.posedge
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while s_eth_payload_axis_tvalid or s_eth_hdr_valid:
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sink_pause_list[0].next = True
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sink_pause_list[1].next = True
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sink_pause_list[2].next = True
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sink_pause_list[3].next = True
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for k in range(M_COUNT):
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sink_pause_list[k].next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause_list[0].next = False
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sink_pause_list[1].next = False
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sink_pause_list[2].next = False
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sink_pause_list[3].next = False
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for k in range(M_COUNT):
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sink_pause_list[k].next = False
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yield clk.posedge
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select.next = 2
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@ -396,17 +396,13 @@ def bench():
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yield clk.posedge
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while s_eth_payload_axis_tvalid or s_eth_hdr_valid:
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sink_pause_list[0].next = True
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sink_pause_list[1].next = True
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sink_pause_list[2].next = True
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sink_pause_list[3].next = True
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for k in range(M_COUNT):
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sink_pause_list[k].next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause_list[0].next = False
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sink_pause_list[1].next = False
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sink_pause_list[2].next = False
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sink_pause_list[3].next = False
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for k in range(M_COUNT):
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sink_pause_list[k].next = False
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yield clk.posedge
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select.next = 2
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@ -354,20 +354,19 @@ def bench():
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yield clk.posedge
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while s_eth_payload_axis_tvalid:
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source_pause_list[0].next = True
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source_pause_list[1].next = True
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source_pause_list[2].next = True
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source_pause_list[3].next = True
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yield clk.posedge
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield clk.posedge
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source_pause_list[0].next = False
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source_pause_list[1].next = False
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source_pause_list[2].next = False
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source_pause_list[3].next = False
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for k in range(S_COUNT):
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source_pause_list[k].next = True
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yield clk.posedge
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select.next = 2
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield sink.wait()
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rx_frame = sink.recv()
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@ -354,20 +354,19 @@ def bench():
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yield clk.posedge
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while s_eth_payload_axis_tvalid:
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source_pause_list[0].next = True
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source_pause_list[1].next = True
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source_pause_list[2].next = True
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source_pause_list[3].next = True
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yield clk.posedge
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield clk.posedge
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source_pause_list[0].next = False
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source_pause_list[1].next = False
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source_pause_list[2].next = False
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source_pause_list[3].next = False
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for k in range(S_COUNT):
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source_pause_list[k].next = True
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yield clk.posedge
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select.next = 2
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield sink.wait()
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rx_frame = sink.recv()
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@ -538,19 +538,18 @@ def bench():
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yield clk.posedge
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while s_ip_payload_axis_tvalid:
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source_pause_list[0].next = True
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source_pause_list[1].next = True
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source_pause_list[2].next = True
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source_pause_list[3].next = True
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yield clk.posedge
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield clk.posedge
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source_pause_list[0].next = False
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source_pause_list[1].next = False
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source_pause_list[2].next = False
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source_pause_list[3].next = False
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for k in range(S_COUNT):
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source_pause_list[k].next = True
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield sink.wait()
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rx_frame = sink.recv()
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@ -538,19 +538,18 @@ def bench():
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yield clk.posedge
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while s_ip_payload_axis_tvalid:
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source_pause_list[0].next = True
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source_pause_list[1].next = True
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source_pause_list[2].next = True
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source_pause_list[3].next = True
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yield clk.posedge
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield clk.posedge
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source_pause_list[0].next = False
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source_pause_list[1].next = False
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source_pause_list[2].next = False
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source_pause_list[3].next = False
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for k in range(S_COUNT):
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source_pause_list[k].next = True
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yield clk.posedge
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for k in range(S_COUNT):
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source_pause_list[k].next = False
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yield sink.wait()
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rx_frame = sink.recv()
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@ -627,17 +627,13 @@ def bench():
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yield clk.posedge
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while s_ip_payload_axis_tvalid or s_ip_hdr_valid:
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sink_pause_list[0].next = True
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sink_pause_list[1].next = True
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sink_pause_list[2].next = True
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sink_pause_list[3].next = True
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for k in range(M_COUNT):
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sink_pause_list[k].next = False
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause_list[0].next = False
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sink_pause_list[1].next = False
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sink_pause_list[2].next = False
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sink_pause_list[3].next = False
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for k in range(M_COUNT):
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sink_pause_list[k].next = False
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yield clk.posedge
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select.next = 2
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@ -627,17 +627,13 @@ def bench():
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yield clk.posedge
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while s_ip_payload_axis_tvalid or s_ip_hdr_valid:
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sink_pause_list[0].next = True
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sink_pause_list[1].next = True
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sink_pause_list[2].next = True
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sink_pause_list[3].next = True
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for k in range(M_COUNT):
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sink_pause_list[k].next = False
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause_list[0].next = False
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sink_pause_list[1].next = False
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sink_pause_list[2].next = False
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sink_pause_list[3].next = False
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for k in range(M_COUNT):
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sink_pause_list[k].next = False
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yield clk.posedge
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select.next = 2
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@ -222,12 +222,14 @@ def bench():
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def wait_pause_source():
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while s_eth_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_eth_hdr_valid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_eth_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_eth_hdr_valid:
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@ -228,12 +228,14 @@ def bench():
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def wait_pause_source():
|
||||
while s_eth_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_eth_hdr_valid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
|
||||
source_pause.next = False
|
||||
|
||||
def wait_pause_sink():
|
||||
while s_eth_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_eth_hdr_valid:
|
||||
|
@ -198,12 +198,14 @@ def bench():
|
||||
|
||||
def wait_pause_source():
|
||||
while s_ip_payload_axis_tvalid or m_eth_payload_axis_tvalid or s_ip_hdr_valid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
|
||||
source_pause.next = False
|
||||
|
||||
def wait_pause_sink():
|
||||
while s_ip_payload_axis_tvalid or m_eth_payload_axis_tvalid or s_ip_hdr_valid:
|
||||
|
@ -204,12 +204,14 @@ def bench():
|
||||
|
||||
def wait_pause_source():
|
||||
while s_ip_payload_axis_tvalid or m_eth_payload_axis_tvalid or s_ip_hdr_valid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
|
||||
source_pause.next = False
|
||||
|
||||
def wait_pause_sink():
|
||||
while s_ip_payload_axis_tvalid or m_eth_payload_axis_tvalid or s_ip_hdr_valid:
|
||||
|
@ -557,20 +557,19 @@ def bench():
|
||||
yield clk.posedge
|
||||
|
||||
while s_ip_payload_axis_tvalid:
|
||||
source_pause_list[0].next = True
|
||||
source_pause_list[1].next = True
|
||||
source_pause_list[2].next = True
|
||||
source_pause_list[3].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
source_pause_list[0].next = False
|
||||
source_pause_list[1].next = False
|
||||
source_pause_list[2].next = False
|
||||
source_pause_list[3].next = False
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = True
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
|
||||
|
@ -557,20 +557,19 @@ def bench():
|
||||
yield clk.posedge
|
||||
|
||||
while s_ip_payload_axis_tvalid:
|
||||
source_pause_list[0].next = True
|
||||
source_pause_list[1].next = True
|
||||
source_pause_list[2].next = True
|
||||
source_pause_list[3].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
source_pause_list[0].next = False
|
||||
source_pause_list[1].next = False
|
||||
source_pause_list[2].next = False
|
||||
source_pause_list[3].next = False
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = True
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
|
||||
|
@ -598,19 +598,18 @@ def bench():
|
||||
yield clk.posedge
|
||||
|
||||
while s_udp_payload_axis_tvalid:
|
||||
source_pause_list[0].next = True
|
||||
source_pause_list[1].next = True
|
||||
source_pause_list[2].next = True
|
||||
source_pause_list[3].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
source_pause_list[0].next = False
|
||||
source_pause_list[1].next = False
|
||||
source_pause_list[2].next = False
|
||||
source_pause_list[3].next = False
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = True
|
||||
yield clk.posedge
|
||||
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
|
||||
|
@ -598,19 +598,18 @@ def bench():
|
||||
yield clk.posedge
|
||||
|
||||
while s_udp_payload_axis_tvalid:
|
||||
source_pause_list[0].next = True
|
||||
source_pause_list[1].next = True
|
||||
source_pause_list[2].next = True
|
||||
source_pause_list[3].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
source_pause_list[0].next = False
|
||||
source_pause_list[1].next = False
|
||||
source_pause_list[2].next = False
|
||||
source_pause_list[3].next = False
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = True
|
||||
yield clk.posedge
|
||||
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
|
||||
|
@ -695,17 +695,13 @@ def bench():
|
||||
yield clk.posedge
|
||||
|
||||
while s_udp_payload_axis_tvalid or s_udp_hdr_valid:
|
||||
sink_pause_list[0].next = True
|
||||
sink_pause_list[1].next = True
|
||||
sink_pause_list[2].next = True
|
||||
sink_pause_list[3].next = True
|
||||
for k in range(M_COUNT):
|
||||
sink_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
sink_pause_list[0].next = False
|
||||
sink_pause_list[1].next = False
|
||||
sink_pause_list[2].next = False
|
||||
sink_pause_list[3].next = False
|
||||
for k in range(M_COUNT):
|
||||
sink_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
|
@ -695,17 +695,13 @@ def bench():
|
||||
yield clk.posedge
|
||||
|
||||
while s_udp_payload_axis_tvalid or s_udp_hdr_valid:
|
||||
sink_pause_list[0].next = True
|
||||
sink_pause_list[1].next = True
|
||||
sink_pause_list[2].next = True
|
||||
sink_pause_list[3].next = True
|
||||
for k in range(M_COUNT):
|
||||
sink_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
sink_pause_list[0].next = False
|
||||
sink_pause_list[1].next = False
|
||||
sink_pause_list[2].next = False
|
||||
sink_pause_list[3].next = False
|
||||
for k in range(M_COUNT):
|
||||
sink_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
|
@ -264,12 +264,14 @@ def bench():
|
||||
|
||||
def wait_pause_source():
|
||||
while s_ip_payload_axis_tvalid or m_udp_payload_axis_tvalid or s_ip_hdr_valid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
|
||||
source_pause.next = False
|
||||
|
||||
def wait_pause_sink():
|
||||
while s_ip_payload_axis_tvalid or m_udp_payload_axis_tvalid or s_ip_hdr_valid:
|
||||
|
@ -270,12 +270,14 @@ def bench():
|
||||
|
||||
def wait_pause_source():
|
||||
while s_ip_payload_axis_tvalid or m_udp_payload_axis_tvalid or s_ip_hdr_valid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
|
||||
source_pause.next = False
|
||||
|
||||
def wait_pause_sink():
|
||||
while s_ip_payload_axis_tvalid or m_udp_payload_axis_tvalid or s_ip_hdr_valid:
|
||||
|
@ -256,12 +256,14 @@ def bench():
|
||||
|
||||
def wait_pause_source():
|
||||
while s_udp_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_udp_hdr_valid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
|
||||
source_pause.next = False
|
||||
|
||||
def wait_pause_sink():
|
||||
while s_udp_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_udp_hdr_valid:
|
||||
|
@ -262,12 +262,14 @@ def bench():
|
||||
|
||||
def wait_pause_source():
|
||||
while s_udp_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_udp_hdr_valid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
|
||||
source_pause.next = False
|
||||
|
||||
def wait_pause_sink():
|
||||
while s_udp_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_udp_hdr_valid:
|
||||
|
@ -617,20 +617,19 @@ def bench():
|
||||
yield clk.posedge
|
||||
|
||||
while s_udp_payload_axis_tvalid:
|
||||
source_pause_list[0].next = True
|
||||
source_pause_list[1].next = True
|
||||
source_pause_list[2].next = True
|
||||
source_pause_list[3].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
source_pause_list[0].next = False
|
||||
source_pause_list[1].next = False
|
||||
source_pause_list[2].next = False
|
||||
source_pause_list[3].next = False
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = True
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
|
||||
|
@ -617,20 +617,19 @@ def bench():
|
||||
yield clk.posedge
|
||||
|
||||
while s_udp_payload_axis_tvalid:
|
||||
source_pause_list[0].next = True
|
||||
source_pause_list[1].next = True
|
||||
source_pause_list[2].next = True
|
||||
source_pause_list[3].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
source_pause_list[0].next = False
|
||||
source_pause_list[1].next = False
|
||||
source_pause_list[2].next = False
|
||||
source_pause_list[3].next = False
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = True
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
for k in range(S_COUNT):
|
||||
source_pause_list[k].next = False
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user