diff --git a/tb/test_arp_eth_rx.py b/tb/test_arp_eth_rx.py index e793ef506..19303fac3 100755 --- a/tb/test_arp_eth_rx.py +++ b/tb/test_arp_eth_rx.py @@ -358,12 +358,14 @@ def bench(): yield clk.posedge while s_eth_payload_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_arp_eth_rx_64.py b/tb/test_arp_eth_rx_64.py index 998a6f007..0191157b8 100755 --- a/tb/test_arp_eth_rx_64.py +++ b/tb/test_arp_eth_rx_64.py @@ -361,12 +361,14 @@ def bench(): yield clk.posedge while s_eth_payload_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_axis_eth_fcs_check.py b/tb/test_axis_eth_fcs_check.py index 55b2729e2..620ecdcae 100755 --- a/tb/test_axis_eth_fcs_check.py +++ b/tb/test_axis_eth_fcs_check.py @@ -144,12 +144,14 @@ def bench(): def wait_pause_source(): while s_axis_tvalid or m_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_axis_tvalid or m_axis_tvalid: diff --git a/tb/test_axis_eth_fcs_check_64.py b/tb/test_axis_eth_fcs_check_64.py index 5c021ef67..67b3d92ef 100755 --- a/tb/test_axis_eth_fcs_check_64.py +++ b/tb/test_axis_eth_fcs_check_64.py @@ -150,12 +150,14 @@ def bench(): def wait_pause_source(): while s_axis_tvalid or m_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_axis_tvalid or m_axis_tvalid: diff --git a/tb/test_axis_eth_fcs_insert.py b/tb/test_axis_eth_fcs_insert.py index 8a5ee2477..e41a7379a 100755 --- a/tb/test_axis_eth_fcs_insert.py +++ b/tb/test_axis_eth_fcs_insert.py @@ -136,12 +136,14 @@ def bench(): def wait_pause_source(): while s_axis_tvalid or m_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_axis_tvalid or m_axis_tvalid: diff --git a/tb/test_axis_eth_fcs_insert_64.py b/tb/test_axis_eth_fcs_insert_64.py index d2bfb7583..6b276f353 100755 --- a/tb/test_axis_eth_fcs_insert_64.py +++ b/tb/test_axis_eth_fcs_insert_64.py @@ -142,12 +142,14 @@ def bench(): def wait_pause_source(): while s_axis_tvalid or m_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_axis_tvalid or m_axis_tvalid: diff --git a/tb/test_axis_eth_fcs_insert_64_pad.py b/tb/test_axis_eth_fcs_insert_64_pad.py index af81dcade..ce36959be 100755 --- a/tb/test_axis_eth_fcs_insert_64_pad.py +++ b/tb/test_axis_eth_fcs_insert_64_pad.py @@ -142,12 +142,14 @@ def bench(): def wait_pause_source(): while s_axis_tvalid or m_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_axis_tvalid or m_axis_tvalid: diff --git a/tb/test_axis_eth_fcs_insert_pad.py b/tb/test_axis_eth_fcs_insert_pad.py index e9133c3b8..b2d9393fa 100755 --- a/tb/test_axis_eth_fcs_insert_pad.py +++ b/tb/test_axis_eth_fcs_insert_pad.py @@ -136,12 +136,14 @@ def bench(): def wait_pause_source(): while s_axis_tvalid or m_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_axis_tvalid or m_axis_tvalid: diff --git a/tb/test_eth_arb_mux_4.py b/tb/test_eth_arb_mux_4.py index bd4c62c4b..f96e9b710 100755 --- a/tb/test_eth_arb_mux_4.py +++ b/tb/test_eth_arb_mux_4.py @@ -335,19 +335,18 @@ def bench(): yield clk.posedge while s_eth_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_eth_arb_mux_64_4.py b/tb/test_eth_arb_mux_64_4.py index 86104b6d6..75d321252 100755 --- a/tb/test_eth_arb_mux_64_4.py +++ b/tb/test_eth_arb_mux_64_4.py @@ -335,19 +335,18 @@ def bench(): yield clk.posedge while s_eth_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_eth_axis_rx.py b/tb/test_eth_axis_rx.py index fe6467aaf..bb6ad1e32 100755 --- a/tb/test_eth_axis_rx.py +++ b/tb/test_eth_axis_rx.py @@ -153,12 +153,14 @@ def bench(): def wait_pause_source(): while s_axis_tvalid or m_eth_payload_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_axis_tvalid or m_eth_payload_axis_tvalid: diff --git a/tb/test_eth_axis_rx_64.py b/tb/test_eth_axis_rx_64.py index f39d730b9..c7733a363 100755 --- a/tb/test_eth_axis_rx_64.py +++ b/tb/test_eth_axis_rx_64.py @@ -159,12 +159,14 @@ def bench(): def wait_pause_source(): while s_axis_tvalid or m_eth_payload_axis_tvalid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_axis_tvalid or m_eth_payload_axis_tvalid: diff --git a/tb/test_eth_axis_tx.py b/tb/test_eth_axis_tx.py index a5031ae0a..229712fe7 100755 --- a/tb/test_eth_axis_tx.py +++ b/tb/test_eth_axis_tx.py @@ -144,12 +144,14 @@ def bench(): def wait_pause_source(): while s_eth_payload_axis_tvalid or m_axis_tvalid or s_eth_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_eth_payload_axis_tvalid or m_axis_tvalid or s_eth_hdr_valid: diff --git a/tb/test_eth_axis_tx_64.py b/tb/test_eth_axis_tx_64.py index 105c24cba..f529c49f7 100755 --- a/tb/test_eth_axis_tx_64.py +++ b/tb/test_eth_axis_tx_64.py @@ -150,12 +150,14 @@ def bench(): def wait_pause_source(): while s_eth_payload_axis_tvalid or m_axis_tvalid or s_eth_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_eth_payload_axis_tvalid or m_axis_tvalid or s_eth_hdr_valid: diff --git a/tb/test_eth_demux_4.py b/tb/test_eth_demux_4.py index 16a1adb23..5b9e488ed 100755 --- a/tb/test_eth_demux_4.py +++ b/tb/test_eth_demux_4.py @@ -354,14 +354,16 @@ def bench(): yield clk.posedge while s_eth_payload_axis_tvalid or s_eth_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge select.next = 2 + source_pause.next = False + yield sink_list[1].wait() rx_frame = sink_list[1].recv() @@ -396,17 +398,13 @@ def bench(): yield clk.posedge while s_eth_payload_axis_tvalid or s_eth_hdr_valid: - sink_pause_list[0].next = True - sink_pause_list[1].next = True - sink_pause_list[2].next = True - sink_pause_list[3].next = True + for k in range(M_COUNT): + sink_pause_list[k].next = True yield clk.posedge yield clk.posedge yield clk.posedge - sink_pause_list[0].next = False - sink_pause_list[1].next = False - sink_pause_list[2].next = False - sink_pause_list[3].next = False + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge select.next = 2 diff --git a/tb/test_eth_demux_64_4.py b/tb/test_eth_demux_64_4.py index 1071089d3..6b5afe2a1 100755 --- a/tb/test_eth_demux_64_4.py +++ b/tb/test_eth_demux_64_4.py @@ -396,17 +396,13 @@ def bench(): yield clk.posedge while s_eth_payload_axis_tvalid or s_eth_hdr_valid: - sink_pause_list[0].next = True - sink_pause_list[1].next = True - sink_pause_list[2].next = True - sink_pause_list[3].next = True + for k in range(M_COUNT): + sink_pause_list[k].next = True yield clk.posedge yield clk.posedge yield clk.posedge - sink_pause_list[0].next = False - sink_pause_list[1].next = False - sink_pause_list[2].next = False - sink_pause_list[3].next = False + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge select.next = 2 diff --git a/tb/test_eth_mux_4.py b/tb/test_eth_mux_4.py index 7a7ef02f4..e96d41a38 100755 --- a/tb/test_eth_mux_4.py +++ b/tb/test_eth_mux_4.py @@ -354,20 +354,19 @@ def bench(): yield clk.posedge while s_eth_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge select.next = 2 + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_eth_mux_64_4.py b/tb/test_eth_mux_64_4.py index 8beb729eb..2b263523f 100755 --- a/tb/test_eth_mux_64_4.py +++ b/tb/test_eth_mux_64_4.py @@ -354,20 +354,19 @@ def bench(): yield clk.posedge while s_eth_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge select.next = 2 + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_ip_arb_mux_4.py b/tb/test_ip_arb_mux_4.py index ad3c3885a..2127c395c 100755 --- a/tb/test_ip_arb_mux_4.py +++ b/tb/test_ip_arb_mux_4.py @@ -538,19 +538,18 @@ def bench(): yield clk.posedge while s_ip_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_ip_arb_mux_64_4.py b/tb/test_ip_arb_mux_64_4.py index cf17d9654..ee633c952 100755 --- a/tb/test_ip_arb_mux_64_4.py +++ b/tb/test_ip_arb_mux_64_4.py @@ -538,19 +538,18 @@ def bench(): yield clk.posedge while s_ip_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_ip_demux_4.py b/tb/test_ip_demux_4.py index d4a51a1fd..a5d467d5d 100755 --- a/tb/test_ip_demux_4.py +++ b/tb/test_ip_demux_4.py @@ -627,17 +627,13 @@ def bench(): yield clk.posedge while s_ip_payload_axis_tvalid or s_ip_hdr_valid: - sink_pause_list[0].next = True - sink_pause_list[1].next = True - sink_pause_list[2].next = True - sink_pause_list[3].next = True + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge yield clk.posedge yield clk.posedge - sink_pause_list[0].next = False - sink_pause_list[1].next = False - sink_pause_list[2].next = False - sink_pause_list[3].next = False + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge select.next = 2 diff --git a/tb/test_ip_demux_64_4.py b/tb/test_ip_demux_64_4.py index 166ad0fce..69f65356b 100755 --- a/tb/test_ip_demux_64_4.py +++ b/tb/test_ip_demux_64_4.py @@ -627,17 +627,13 @@ def bench(): yield clk.posedge while s_ip_payload_axis_tvalid or s_ip_hdr_valid: - sink_pause_list[0].next = True - sink_pause_list[1].next = True - sink_pause_list[2].next = True - sink_pause_list[3].next = True + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge yield clk.posedge yield clk.posedge - sink_pause_list[0].next = False - sink_pause_list[1].next = False - sink_pause_list[2].next = False - sink_pause_list[3].next = False + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge select.next = 2 diff --git a/tb/test_ip_eth_rx.py b/tb/test_ip_eth_rx.py index 69fa513bf..2996f196d 100755 --- a/tb/test_ip_eth_rx.py +++ b/tb/test_ip_eth_rx.py @@ -222,12 +222,14 @@ def bench(): def wait_pause_source(): while s_eth_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_eth_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_eth_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_eth_hdr_valid: diff --git a/tb/test_ip_eth_rx_64.py b/tb/test_ip_eth_rx_64.py index 62b349566..e55cdbb3a 100755 --- a/tb/test_ip_eth_rx_64.py +++ b/tb/test_ip_eth_rx_64.py @@ -228,12 +228,14 @@ def bench(): def wait_pause_source(): while s_eth_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_eth_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_eth_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_eth_hdr_valid: diff --git a/tb/test_ip_eth_tx.py b/tb/test_ip_eth_tx.py index 50cbaaba1..799de5202 100755 --- a/tb/test_ip_eth_tx.py +++ b/tb/test_ip_eth_tx.py @@ -198,12 +198,14 @@ def bench(): def wait_pause_source(): while s_ip_payload_axis_tvalid or m_eth_payload_axis_tvalid or s_ip_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_ip_payload_axis_tvalid or m_eth_payload_axis_tvalid or s_ip_hdr_valid: diff --git a/tb/test_ip_eth_tx_64.py b/tb/test_ip_eth_tx_64.py index d528db9a3..185fb140f 100755 --- a/tb/test_ip_eth_tx_64.py +++ b/tb/test_ip_eth_tx_64.py @@ -204,12 +204,14 @@ def bench(): def wait_pause_source(): while s_ip_payload_axis_tvalid or m_eth_payload_axis_tvalid or s_ip_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_ip_payload_axis_tvalid or m_eth_payload_axis_tvalid or s_ip_hdr_valid: diff --git a/tb/test_ip_mux_4.py b/tb/test_ip_mux_4.py index 178589b0e..c19349bec 100755 --- a/tb/test_ip_mux_4.py +++ b/tb/test_ip_mux_4.py @@ -557,20 +557,19 @@ def bench(): yield clk.posedge while s_ip_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge select.next = 2 + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_ip_mux_64_4.py b/tb/test_ip_mux_64_4.py index b1920fdfd..ea7ca2f19 100755 --- a/tb/test_ip_mux_64_4.py +++ b/tb/test_ip_mux_64_4.py @@ -557,20 +557,19 @@ def bench(): yield clk.posedge while s_ip_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge select.next = 2 + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_udp_arb_mux_4.py b/tb/test_udp_arb_mux_4.py index 6b98097e0..69c07767e 100755 --- a/tb/test_udp_arb_mux_4.py +++ b/tb/test_udp_arb_mux_4.py @@ -598,19 +598,18 @@ def bench(): yield clk.posedge while s_udp_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_udp_arb_mux_64_4.py b/tb/test_udp_arb_mux_64_4.py index c28ac25c4..a4d0b3de8 100755 --- a/tb/test_udp_arb_mux_64_4.py +++ b/tb/test_udp_arb_mux_64_4.py @@ -598,19 +598,18 @@ def bench(): yield clk.posedge while s_udp_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_udp_demux_4.py b/tb/test_udp_demux_4.py index 45a2c0b1b..16352cb08 100755 --- a/tb/test_udp_demux_4.py +++ b/tb/test_udp_demux_4.py @@ -695,17 +695,13 @@ def bench(): yield clk.posedge while s_udp_payload_axis_tvalid or s_udp_hdr_valid: - sink_pause_list[0].next = True - sink_pause_list[1].next = True - sink_pause_list[2].next = True - sink_pause_list[3].next = True + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge yield clk.posedge yield clk.posedge - sink_pause_list[0].next = False - sink_pause_list[1].next = False - sink_pause_list[2].next = False - sink_pause_list[3].next = False + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge select.next = 2 diff --git a/tb/test_udp_demux_64_4.py b/tb/test_udp_demux_64_4.py index f99169b75..5b0e0935b 100755 --- a/tb/test_udp_demux_64_4.py +++ b/tb/test_udp_demux_64_4.py @@ -695,17 +695,13 @@ def bench(): yield clk.posedge while s_udp_payload_axis_tvalid or s_udp_hdr_valid: - sink_pause_list[0].next = True - sink_pause_list[1].next = True - sink_pause_list[2].next = True - sink_pause_list[3].next = True + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge yield clk.posedge yield clk.posedge - sink_pause_list[0].next = False - sink_pause_list[1].next = False - sink_pause_list[2].next = False - sink_pause_list[3].next = False + for k in range(M_COUNT): + sink_pause_list[k].next = False yield clk.posedge select.next = 2 diff --git a/tb/test_udp_ip_rx.py b/tb/test_udp_ip_rx.py index 69c43a3bc..c4b1e9c4e 100755 --- a/tb/test_udp_ip_rx.py +++ b/tb/test_udp_ip_rx.py @@ -264,12 +264,14 @@ def bench(): def wait_pause_source(): while s_ip_payload_axis_tvalid or m_udp_payload_axis_tvalid or s_ip_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_ip_payload_axis_tvalid or m_udp_payload_axis_tvalid or s_ip_hdr_valid: diff --git a/tb/test_udp_ip_rx_64.py b/tb/test_udp_ip_rx_64.py index 763fba805..6d4ea37a7 100755 --- a/tb/test_udp_ip_rx_64.py +++ b/tb/test_udp_ip_rx_64.py @@ -270,12 +270,14 @@ def bench(): def wait_pause_source(): while s_ip_payload_axis_tvalid or m_udp_payload_axis_tvalid or s_ip_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_ip_payload_axis_tvalid or m_udp_payload_axis_tvalid or s_ip_hdr_valid: diff --git a/tb/test_udp_ip_tx.py b/tb/test_udp_ip_tx.py index 2197ab41d..4a34589d7 100755 --- a/tb/test_udp_ip_tx.py +++ b/tb/test_udp_ip_tx.py @@ -256,12 +256,14 @@ def bench(): def wait_pause_source(): while s_udp_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_udp_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_udp_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_udp_hdr_valid: diff --git a/tb/test_udp_ip_tx_64.py b/tb/test_udp_ip_tx_64.py index ee6562acf..474adbaea 100755 --- a/tb/test_udp_ip_tx_64.py +++ b/tb/test_udp_ip_tx_64.py @@ -262,12 +262,14 @@ def bench(): def wait_pause_source(): while s_udp_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_udp_hdr_valid: - source_pause.next = True - yield clk.posedge yield clk.posedge yield clk.posedge source_pause.next = False yield clk.posedge + source_pause.next = True + yield clk.posedge + + source_pause.next = False def wait_pause_sink(): while s_udp_payload_axis_tvalid or m_ip_payload_axis_tvalid or s_udp_hdr_valid: diff --git a/tb/test_udp_mux_4.py b/tb/test_udp_mux_4.py index 1399c50af..e1355b0d6 100755 --- a/tb/test_udp_mux_4.py +++ b/tb/test_udp_mux_4.py @@ -617,20 +617,19 @@ def bench(): yield clk.posedge while s_udp_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge select.next = 2 + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_udp_mux_64_4.py b/tb/test_udp_mux_64_4.py index 162f658ce..64c5af4c9 100755 --- a/tb/test_udp_mux_64_4.py +++ b/tb/test_udp_mux_64_4.py @@ -617,20 +617,19 @@ def bench(): yield clk.posedge while s_udp_payload_axis_tvalid: - source_pause_list[0].next = True - source_pause_list[1].next = True - source_pause_list[2].next = True - source_pause_list[3].next = True yield clk.posedge yield clk.posedge + for k in range(S_COUNT): + source_pause_list[k].next = False yield clk.posedge - source_pause_list[0].next = False - source_pause_list[1].next = False - source_pause_list[2].next = False - source_pause_list[3].next = False + for k in range(S_COUNT): + source_pause_list[k].next = True yield clk.posedge select.next = 2 + for k in range(S_COUNT): + source_pause_list[k].next = False + yield sink.wait() rx_frame = sink.recv()