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Fix reg to wire declaration

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Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
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Andreas Braun 2021-10-07 17:18:08 +02:00 committed by Alex Forencich
parent bac4e4066f
commit 01b97322c1
1 changed files with 1 additions and 1 deletions
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rtl/dma_if_axi_rd.v
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@ -280,7 +280,7 @@ reg [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] ram_wr_cmd_be_int;
reg [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr_int;
reg [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_wr_cmd_data_int;
reg [RAM_SEG_COUNT-1:0] ram_wr_cmd_valid_int;
reg [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready_int;
wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready_int;
wire [RAM_SEG_COUNT-1:0] out_done;
reg [RAM_SEG_COUNT-1:0] out_done_ack;