diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile index d52c3e3b8..a76cb3203 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile @@ -117,7 +117,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl index 05c6257e2..04512c1e1 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v index 76a761192..e38fc72a8 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v @@ -111,7 +111,7 @@ module fpga # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v index ad45c722a..88afa0904 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile index 078ad2056..1ee054be4 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile @@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl index 3929a6827..0491ecfa0 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile index 078ad2056..1ee054be4 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile @@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl index 014623dc1..b28ad5626 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v index 6e8671d40..d04270040 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v index be3e61657..5937fca0d 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index 694f11f92..c3539c713 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -119,7 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl index 64280337c..da7278275 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile index ed7fb41bc..8e0f098f0 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile @@ -121,7 +121,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl index 2cdcd5cbf..e2d9fcc13 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v index 67593ffe4..851d28117 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v @@ -111,7 +111,7 @@ module fpga # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 33, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index fc2f42ad5..dcc969d89 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 33, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 27703739c..693de57bd 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl index aee9005c5..12f9b9cc1 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index 27703739c..693de57bd 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl index 8411fe320..0c28ba4af 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile index 9028375ae..71688a663 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile @@ -140,7 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index 2b6ba0a37..f8886e076 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 7ea8c6d3c..3c62f2722 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 33, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index dd8d628e9..4042769fa 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 33, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile index f13ace56c..01013779a 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile @@ -125,7 +125,7 @@ IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl index bc354ac6d..91e17d681 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v index 08ac520c4..6ed1184bb 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v @@ -111,7 +111,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 02088d212..709cedcbb 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile index fe1f365d1..6b4f2d6bc 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile @@ -145,7 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl index c8815c906..8d9adec01 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile index fe1f365d1..6b4f2d6bc 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile @@ -145,7 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl index aa9bef37e..6c44b2dde 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index d86cbf41e..cb256a990 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 9bf1044e3..1a21164b4 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile index a7ceeb9d5..a41aa1e8c 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile @@ -125,7 +125,7 @@ IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl index 00879da2e..d4d102e75 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v index 061cdb895..5ed4e4767 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v @@ -111,7 +111,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index 34831b2ce..b5804182c 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile index 1cd444bb6..c1d2add7c 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile @@ -145,7 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl index ec821353f..c80b11807 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile index 1cd444bb6..c1d2add7c 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile @@ -145,7 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl index 2365599ae..6a25357d3 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index 7b63e22ec..af639874b 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v index ee697be04..d82687402 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile index a361c50b5..6b880159a 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -117,15 +117,15 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl -XDC_FILES += hbm.xdc +#XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/hbm_0.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/hbm_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl index 813e19316..c228d7218 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl @@ -139,11 +139,11 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" dict set params HBM_CH "32" -dict set params HBM_ENABLE "1" +dict set params HBM_ENABLE "0" dict set params HBM_GROUP_SIZE "32" dict set params AXI_HBM_ADDR_WIDTH "33" dict set params AXI_HBM_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v index 5f26ff790..f853f0055 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v @@ -111,14 +111,14 @@ module fpga # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, parameter AXI_DDR_MAX_BURST_LEN = 256, parameter AXI_DDR_NARROW_BURST = 0, parameter HBM_CH = 32, - parameter HBM_ENABLE = 1, + parameter HBM_ENABLE = 0, parameter HBM_GROUP_SIZE = 32, parameter AXI_HBM_ADDR_WIDTH = 33, parameter AXI_HBM_MAX_BURST_LEN = 256, diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index e7b2aecc6..b4fa15cff 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), @@ -125,7 +125,7 @@ module fpga_core # parameter AXI_DDR_MAX_BURST_LEN = 256, parameter AXI_DDR_NARROW_BURST = 0, parameter HBM_CH = 32, - parameter HBM_ENABLE = 1, + parameter HBM_ENABLE = 0, parameter HBM_GROUP_SIZE = 32, parameter AXI_HBM_DATA_WIDTH = 256, parameter AXI_HBM_ADDR_WIDTH = 33, diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile index 2d4b56e1a..305f927e7 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile @@ -138,14 +138,14 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl -XDC_FILES += hbm.xdc +#XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/hbm_0.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/hbm_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl index 1a1b373b8..a1399dccc 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl @@ -151,11 +151,11 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" dict set params HBM_CH "32" -dict set params HBM_ENABLE "1" +dict set params HBM_ENABLE "0" dict set params HBM_GROUP_SIZE "32" dict set params AXI_HBM_ADDR_WIDTH "33" dict set params AXI_HBM_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile index 2d4b56e1a..305f927e7 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile @@ -138,14 +138,14 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl -XDC_FILES += hbm.xdc +#XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/hbm_0.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/hbm_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl index c372953d0..e3952ea88 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl @@ -151,11 +151,11 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" dict set params HBM_CH "32" -dict set params HBM_ENABLE "1" +dict set params HBM_ENABLE "0" dict set params HBM_GROUP_SIZE "32" dict set params AXI_HBM_ADDR_WIDTH "33" dict set params AXI_HBM_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v index 82acfb468..d7454047c 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v @@ -114,14 +114,14 @@ module fpga # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, parameter AXI_DDR_MAX_BURST_LEN = 256, parameter AXI_DDR_NARROW_BURST = 0, parameter HBM_CH = 32, - parameter HBM_ENABLE = 1, + parameter HBM_ENABLE = 0, parameter HBM_GROUP_SIZE = 32, parameter AXI_HBM_ADDR_WIDTH = 33, parameter AXI_HBM_MAX_BURST_LEN = 256, diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v index 097e915cf..eb3f954e5 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), @@ -132,7 +132,7 @@ module fpga_core # parameter AXI_DDR_MAX_BURST_LEN = 256, parameter AXI_DDR_NARROW_BURST = 0, parameter HBM_CH = 32, - parameter HBM_ENABLE = 1, + parameter HBM_ENABLE = 0, parameter HBM_GROUP_SIZE = 32, parameter AXI_HBM_DATA_WIDTH = 256, parameter AXI_HBM_ADDR_WIDTH = 33, diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile index a3b21841d..24a9adeb9 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile @@ -117,13 +117,13 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl -XDC_FILES += hbm.xdc +#XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/hbm_0.tcl +#IP_TCL_FILES += ip/hbm_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl index 641a00ff9..93fba0834 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params HBM_CH "32" -dict set params HBM_ENABLE "1" +dict set params HBM_ENABLE "0" dict set params HBM_GROUP_SIZE "32" dict set params AXI_HBM_ADDR_WIDTH "33" dict set params AXI_HBM_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v index 19fc83f83..efeb7f344 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v @@ -111,7 +111,7 @@ module fpga # // RAM configuration parameter HBM_CH = 32, - parameter HBM_ENABLE = 1, + parameter HBM_ENABLE = 0, parameter HBM_GROUP_SIZE = 32, parameter AXI_HBM_ADDR_WIDTH = 33, parameter AXI_HBM_MAX_BURST_LEN = 256, diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index 85f2472e2..eee392c9d 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter HBM_CH = 32, - parameter HBM_ENABLE = 1, + parameter HBM_ENABLE = 0, parameter HBM_GROUP_SIZE = 32, parameter AXI_HBM_DATA_WIDTH = 256, parameter AXI_HBM_ADDR_WIDTH = 33, diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile index b19f66874..662f2c21b 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile @@ -138,13 +138,13 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl -XDC_FILES += hbm.xdc +#XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/hbm_0.tcl +#IP_TCL_FILES += ip/hbm_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl index 0dda5836b..d76d66a75 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params HBM_CH "32" -dict set params HBM_ENABLE "1" +dict set params HBM_ENABLE "0" dict set params HBM_GROUP_SIZE "32" dict set params AXI_HBM_ADDR_WIDTH "33" dict set params AXI_HBM_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile index b19f66874..662f2c21b 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile @@ -138,13 +138,13 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl -XDC_FILES += hbm.xdc +#XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl -IP_TCL_FILES += ip/hbm_0.tcl +#IP_TCL_FILES += ip/hbm_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl index a9c4e90e9..498f57898 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params HBM_CH "32" -dict set params HBM_ENABLE "1" +dict set params HBM_ENABLE "0" dict set params HBM_GROUP_SIZE "32" dict set params AXI_HBM_ADDR_WIDTH "33" dict set params AXI_HBM_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v index 8639a2368..238aadb28 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v @@ -117,7 +117,7 @@ module fpga # // RAM configuration parameter HBM_CH = 32, - parameter HBM_ENABLE = 1, + parameter HBM_ENABLE = 0, parameter HBM_GROUP_SIZE = 32, parameter AXI_HBM_ADDR_WIDTH = 33, parameter AXI_HBM_MAX_BURST_LEN = 256, diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v index b33996265..6210ae808 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter HBM_CH = 32, - parameter HBM_ENABLE = 1, + parameter HBM_ENABLE = 0, parameter HBM_GROUP_SIZE = 32, parameter AXI_HBM_DATA_WIDTH = 256, parameter AXI_HBM_ADDR_WIDTH = 33, diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile index 42219130f..aecd5d989 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile @@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl index 9b573de3e..03d7698ab 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl @@ -142,7 +142,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile index dbc8591f7..6a21a643e 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile @@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl index 195c136c3..1aa0fbb6c 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl @@ -142,7 +142,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index 5554a5d02..31ebe99f9 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v index 09a0734b2..faf864b62 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile index 96758c53e..36e3a5f33 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile @@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl index 116d2f22b..75e20ad68 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile index 96758c53e..36e3a5f33 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile @@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl index 5a03ff521..3c963d67b 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index d3a3b299d..2eb5a958b 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 33, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v index e99729e9c..45cc821d8 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 33, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile index 0f127246f..808d84187 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile @@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl index 2dae67146..9e92eb736 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile index 0f127246f..808d84187 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile @@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl index 04cba5fa7..12715fe48 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v index b78a50cee..08aa0e42c 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v index 5910e50ca..6ca084ef8 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile index 099b76790..a3cd7bcba 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile @@ -119,7 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl index f909a9235..6266e2c9d 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v index 251357016..5f9813ed0 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v @@ -111,7 +111,7 @@ module fpga # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index 5a81f72fa..5ff7ab5cb 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile index 9cceffb8c..e500c5b9b 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile @@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl index 9124de325..8e0a5c429 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile index 9cceffb8c..e500c5b9b 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile @@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl index 782d4ea7c..acc8330f1 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "2" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index 30f60177f..3d3587b7f 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v index 7c2ebe33f..1043d129a 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 2, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile index cc9c6f502..61af50895 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile @@ -120,7 +120,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl index d25cc59be..e2c460080 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v index 30d5e35c6..dc2cf893c 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v @@ -111,7 +111,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index 31d680816..c012468b8 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile index 9fe016fa7..672d62335 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile @@ -140,7 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl index e4f635640..3f436a8c3 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile index 9fe016fa7..672d62335 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile @@ -140,7 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl index 37e8a700f..8e8f7b768 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v index 68804b8b5..26a7a256f 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v index 749539699..441992db7 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile index 40bea31a5..4a93efe05 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile @@ -120,7 +120,7 @@ IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl IP_TCL_FILES += ip/cmac_usplus_2.tcl IP_TCL_FILES += ip/cmac_usplus_3.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl index a1e6b0d5c..86d1a5969 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v index 076f82530..016d8dac0 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v @@ -111,7 +111,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index 7a5f306c8..3f17c0e18 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile index 0e43bbeef..a7880a465 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile @@ -138,7 +138,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl index 88b8678b3..a21411961 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile index 0e43bbeef..a7880a465 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile @@ -138,7 +138,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl index ebf31a7dd..3867fdc8c 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index b2727f5fd..462baa350 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index af8648c17..eb64787df 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 34, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/ZCU102/fpga/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/fpga/Makefile index 4657ea844..f9a8b5317 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga/Makefile @@ -119,7 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/zynq_ps.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl index e3d79240d..d4c99a878 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl +++ b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl @@ -134,7 +134,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v index 15d0c9fef..372e5ed8b 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 128, parameter AXI_DDR_ADDR_WIDTH = 29, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v index 1d08e6747..803b65d2f 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 128, parameter AXI_DDR_ADDR_WIDTH = 29, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile index acf2bfe22..6fa3066dc 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile @@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl index 8892be565..d69530e63 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl @@ -142,7 +142,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index cd3b80d56..1e428346a 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index 551ec97fc..317d171de 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile index c69e19fc1..cac5116dc 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile @@ -119,7 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/zynq_ps.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl index 87133e832..0ed2af7ef 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl @@ -134,7 +134,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "1" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index 31de649a0..2a0a19922 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v index 86c4a1f6b..e0a81cc8a 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 1, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 31, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index 7cae09d8c..9dc690a4b 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -121,7 +121,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl index f8580e72f..dddae149d 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile index 5b64e0cb4..b767dfc0d 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile @@ -123,7 +123,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl index 176dec750..23c1a10df 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl @@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v index 1efe7b990..3a2478b7b 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v @@ -111,7 +111,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 7146a3957..805cd38dd 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -117,7 +117,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index a82125da2..6b51347d1 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -141,7 +141,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index 324df9f07..e4667cc35 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile index a82125da2..6b51347d1 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile @@ -141,7 +141,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl index 97c4931d6..ee44106fe 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile index 0fe0e04ce..f950737d2 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile @@ -142,7 +142,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl index 923a99fa7..bba7ecf7b 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl @@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" -dict set params DDR_ENABLE "1" +dict set params DDR_ENABLE "0" dict set params AXI_DDR_ID_WIDTH "8" dict set params AXI_DDR_MAX_BURST_LEN "256" diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index 53cb53bbb..67d88be58 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -114,7 +114,7 @@ module fpga # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_ID_WIDTH = 8, diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 5dd0ee842..45909f424 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -124,7 +124,7 @@ module fpga_core # // RAM configuration parameter DDR_CH = 4, - parameter DDR_ENABLE = 1, + parameter DDR_ENABLE = 0, parameter AXI_DDR_DATA_WIDTH = 512, parameter AXI_DDR_ADDR_WIDTH = 32, parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),