fpga/mqnic: Disable MIGs by default

Signed-off-by: Alex Forencich <alex@alexforencich.com>

fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile

@@ -117,7 +117,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_1.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl

@@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "1"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v

@@ -111,7 +111,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 1,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 32,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v

@@ -117,7 +117,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 1,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 32,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile

@@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "1"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile

@@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "1"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v

@@ -114,7 +114,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 1,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 32,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 1,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 32,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile

@@ -119,7 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_1.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl

@@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile

@@ -121,7 +121,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_1.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl

@@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v

@@ -111,7 +111,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 33,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v

@@ -117,7 +117,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 33,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile

@@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile

@@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile

@@ -140,7 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v

@@ -114,7 +114,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 33,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 33,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/AU200/fpga_100g/fpga/Makefile

@@ -125,7 +125,7 @@ IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_1.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU200/fpga_100g/fpga/config.tcl

@@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "4"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/AU200/fpga_100g/rtl/fpga.v

@@ -111,7 +111,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v

@@ -117,7 +117,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/AU200/fpga_25g/fpga/Makefile

@@ -145,7 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU200/fpga_25g/fpga/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "4"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile

@@ -145,7 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "4"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/AU200/fpga_25g/rtl/fpga.v

@@ -114,7 +114,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/AU250/fpga_100g/fpga/Makefile

@@ -125,7 +125,7 @@ IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_1.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU250/fpga_100g/fpga/config.tcl

@@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "4"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/AU250/fpga_100g/rtl/fpga.v

@@ -111,7 +111,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v

@@ -117,7 +117,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/AU250/fpga_25g/fpga/Makefile

@@ -145,7 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU250/fpga_25g/fpga/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "4"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile

@@ -145,7 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "4"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/AU250/fpga_25g/rtl/fpga.v

@@ -114,7 +114,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/AU280/fpga_100g/fpga/Makefile

@@ -117,15 +117,15 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
-XDC_FILES += hbm.xdc
+#XDC_FILES += hbm.xdc
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_1.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/hbm_0.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/hbm_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU280/fpga_100g/fpga/config.tcl

@@ -139,11 +139,11 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
 dict set params HBM_CH "32"
-dict set params HBM_ENABLE "1"
+dict set params HBM_ENABLE "0"
 dict set params HBM_GROUP_SIZE "32"
 dict set params AXI_HBM_ADDR_WIDTH "33"
 dict set params AXI_HBM_MAX_BURST_LEN "256"

fpga/mqnic/AU280/fpga_100g/rtl/fpga.v

@@ -111,14 +111,14 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_ID_WIDTH = 8,
     parameter AXI_DDR_MAX_BURST_LEN = 256,
     parameter AXI_DDR_NARROW_BURST = 0,
     parameter HBM_CH = 32,
-    parameter HBM_ENABLE = 1,
+    parameter HBM_ENABLE = 0,
     parameter HBM_GROUP_SIZE = 32,
     parameter AXI_HBM_ADDR_WIDTH = 33,
     parameter AXI_HBM_MAX_BURST_LEN = 256,

fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v

@@ -117,7 +117,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
@@ -125,7 +125,7 @@ module fpga_core #
     parameter AXI_DDR_MAX_BURST_LEN = 256,
     parameter AXI_DDR_NARROW_BURST = 0,
     parameter HBM_CH = 32,
-    parameter HBM_ENABLE = 1,
+    parameter HBM_ENABLE = 0,
     parameter HBM_GROUP_SIZE = 32,
     parameter AXI_HBM_DATA_WIDTH = 256,
     parameter AXI_HBM_ADDR_WIDTH = 33,

fpga/mqnic/AU280/fpga_25g/fpga/Makefile

@@ -138,14 +138,14 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
-XDC_FILES += hbm.xdc
+#XDC_FILES += hbm.xdc
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/hbm_0.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/hbm_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU280/fpga_25g/fpga/config.tcl

@@ -151,11 +151,11 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
 dict set params HBM_CH "32"
-dict set params HBM_ENABLE "1"
+dict set params HBM_ENABLE "0"
 dict set params HBM_GROUP_SIZE "32"
 dict set params AXI_HBM_ADDR_WIDTH "33"
 dict set params AXI_HBM_MAX_BURST_LEN "256"

fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile

@@ -138,14 +138,14 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
-XDC_FILES += hbm.xdc
+#XDC_FILES += hbm.xdc
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/hbm_0.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/hbm_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl

@@ -151,11 +151,11 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
 dict set params HBM_CH "32"
-dict set params HBM_ENABLE "1"
+dict set params HBM_ENABLE "0"
 dict set params HBM_GROUP_SIZE "32"
 dict set params AXI_HBM_ADDR_WIDTH "33"
 dict set params AXI_HBM_MAX_BURST_LEN "256"

fpga/mqnic/AU280/fpga_25g/rtl/fpga.v

@@ -114,14 +114,14 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_ID_WIDTH = 8,
     parameter AXI_DDR_MAX_BURST_LEN = 256,
     parameter AXI_DDR_NARROW_BURST = 0,
     parameter HBM_CH = 32,
-    parameter HBM_ENABLE = 1,
+    parameter HBM_ENABLE = 0,
     parameter HBM_GROUP_SIZE = 32,
     parameter AXI_HBM_ADDR_WIDTH = 33,
     parameter AXI_HBM_MAX_BURST_LEN = 256,

fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
@@ -132,7 +132,7 @@ module fpga_core #
     parameter AXI_DDR_MAX_BURST_LEN = 256,
     parameter AXI_DDR_NARROW_BURST = 0,
     parameter HBM_CH = 32,
-    parameter HBM_ENABLE = 1,
+    parameter HBM_ENABLE = 0,
     parameter HBM_GROUP_SIZE = 32,
     parameter AXI_HBM_DATA_WIDTH = 256,
     parameter AXI_HBM_ADDR_WIDTH = 33,

fpga/mqnic/AU50/fpga_100g/fpga/Makefile

@@ -117,13 +117,13 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
-XDC_FILES += hbm.xdc
+#XDC_FILES += hbm.xdc
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_0.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/hbm_0.tcl
+#IP_TCL_FILES += ip/hbm_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU50/fpga_100g/fpga/config.tcl

@@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params HBM_CH "32"
-dict set params HBM_ENABLE "1"
+dict set params HBM_ENABLE "0"
 dict set params HBM_GROUP_SIZE "32"
 dict set params AXI_HBM_ADDR_WIDTH "33"
 dict set params AXI_HBM_MAX_BURST_LEN "256"

fpga/mqnic/AU50/fpga_100g/rtl/fpga.v

@@ -111,7 +111,7 @@ module fpga #
 
     // RAM configuration
     parameter HBM_CH = 32,
-    parameter HBM_ENABLE = 1,
+    parameter HBM_ENABLE = 0,
     parameter HBM_GROUP_SIZE = 32,
     parameter AXI_HBM_ADDR_WIDTH = 33,
     parameter AXI_HBM_MAX_BURST_LEN = 256,

fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v

@@ -117,7 +117,7 @@ module fpga_core #
 
     // RAM configuration
     parameter HBM_CH = 32,
-    parameter HBM_ENABLE = 1,
+    parameter HBM_ENABLE = 0,
     parameter HBM_GROUP_SIZE = 32,
     parameter AXI_HBM_DATA_WIDTH = 256,
     parameter AXI_HBM_ADDR_WIDTH = 33,

fpga/mqnic/AU50/fpga_25g/fpga/Makefile

@@ -138,13 +138,13 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
-XDC_FILES += hbm.xdc
+#XDC_FILES += hbm.xdc
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/hbm_0.tcl
+#IP_TCL_FILES += ip/hbm_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU50/fpga_25g/fpga/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params HBM_CH "32"
-dict set params HBM_ENABLE "1"
+dict set params HBM_ENABLE "0"
 dict set params HBM_GROUP_SIZE "32"
 dict set params AXI_HBM_ADDR_WIDTH "33"
 dict set params AXI_HBM_MAX_BURST_LEN "256"

fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile

@@ -138,13 +138,13 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
-XDC_FILES += hbm.xdc
+#XDC_FILES += hbm.xdc
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
-IP_TCL_FILES += ip/hbm_0.tcl
+#IP_TCL_FILES += ip/hbm_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params HBM_CH "32"
-dict set params HBM_ENABLE "1"
+dict set params HBM_ENABLE "0"
 dict set params HBM_GROUP_SIZE "32"
 dict set params AXI_HBM_ADDR_WIDTH "33"
 dict set params AXI_HBM_MAX_BURST_LEN "256"

fpga/mqnic/AU50/fpga_25g/rtl/fpga.v

@@ -117,7 +117,7 @@ module fpga #
 
     // RAM configuration
     parameter HBM_CH = 32,
-    parameter HBM_ENABLE = 1,
+    parameter HBM_ENABLE = 0,
     parameter HBM_GROUP_SIZE = 32,
     parameter AXI_HBM_ADDR_WIDTH = 33,
     parameter AXI_HBM_MAX_BURST_LEN = 256,

fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter HBM_CH = 32,
-    parameter HBM_ENABLE = 1,
+    parameter HBM_ENABLE = 0,
     parameter HBM_GROUP_SIZE = 32,
     parameter AXI_HBM_DATA_WIDTH = 256,
     parameter AXI_HBM_ADDR_WIDTH = 33,

fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile

@@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gth.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl

@@ -142,7 +142,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "1"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile

@@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gth.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl

@@ -142,7 +142,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "1"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v

@@ -114,7 +114,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 1,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 32,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 1,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 32,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile

@@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "1"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile

@@ -137,7 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "1"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v

@@ -114,7 +114,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 1,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 33,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 1,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 33,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/VCU108/fpga_25g/fpga/Makefile

@@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile

@@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v

@@ -114,7 +114,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 31,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 31,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/VCU118/fpga_100g/fpga/Makefile

@@ -119,7 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_1.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl

@@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v

@@ -111,7 +111,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 31,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v

@@ -117,7 +117,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 31,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/VCU118/fpga_25g/fpga/Makefile

@@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile

@@ -139,7 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "2"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v

@@ -114,7 +114,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 31,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v

@@ -124,7 +124,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 2,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 31,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile

@@ -120,7 +120,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_0.tcl
 IP_TCL_FILES += ip/cmac_usplus_1.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl

@@ -139,7 +139,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "4"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v

@@ -111,7 +111,7 @@ module fpga #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_ID_WIDTH = 8,

fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v

@@ -117,7 +117,7 @@ module fpga_core #
 
     // RAM configuration
     parameter DDR_CH = 4,
-    parameter DDR_ENABLE = 1,
+    parameter DDR_ENABLE = 0,
     parameter AXI_DDR_DATA_WIDTH = 512,
     parameter AXI_DDR_ADDR_WIDTH = 34,
     parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),

fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile

@@ -140,7 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "4"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
  

fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile

@@ -140,7 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
 IP_TCL_FILES += ip/eth_xcvr_gty.tcl
-IP_TCL_FILES += ip/ddr4_0.tcl
+#IP_TCL_FILES += ip/ddr4_0.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl

@@ -151,7 +151,7 @@ dict set params RX_RAM_SIZE "32768"
 
 # RAM configuration
 dict set params DDR_CH "4"
-dict set params DDR_ENABLE "1"
+dict set params DDR_ENABLE "0"
 dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"